JPS63142734A - Clock reproduction circuit - Google Patents

Abstract

PURPOSE:To eliminate a preamble signal from a signal string which a master station transmits and to improve a transmission efficiency by using an output from a PLL circuit, whose phase is synchronized at the time of arrival, as a clock when the signal string does not arrive. CONSTITUTION:When a delayed squelch signal 102 is outputted to a holding circuit 8, a signal from a phase comparator 5 is outputted to a voltage control oscillator 6 via the holding circuit 8 and the phase adjustment of the voltage control oscillator output is executed with the signal. When the time slot of radio electromagnetic wave is completed and the radio wave 100 pauses, the squelch signal 102 is cut without delaying and the holding circuit 8 becomes in a holding state, so that the outgoing frequency of the voltage control oscillator 6 is fixed. When the next radio electromagnetic wave arrives, the preamble signal need not to be put before the following signal string of the radio electromagnetic waves by using the fixed output clock of the voltage control oscillator 6 while the clock component extracted in a clock extraction tuning circuit 3 is made to be stabilized.

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial Field of Application 1] The present invention relates to a clock recovery circuit used in a slave station in a time division digital radio system.

[Prior Art] Conventionally, this type of clock regeneration circuit has a tuning circuit composed of a capacitor, a coil, etc., and has a general configuration in which a clock frequency component included in a demodulated signal string is extracted by this tuning circuit. Met.

[Problems to be solved] In the conventional clock recovery circuit described above, when the resonance selectivity (Q) of the built-in tuning circuit is high, it takes time to extract the clock component, and when it is low, a shifter occurs in the recovered clock. There was a problem in that errors occurred when capturing the signal train. In particular, when a burst signal train arrives as in time division multiplex communication, the above problem is a problem! was big.

For this reason, by inserting a preamble signal containing a large number of clock components at the front stage of an intermittent information signal train, the time required to extract the clock component of a high-Q tuning circuit is protected.

However, in this case, since a preamble signal unrelated to information is inserted into the signal train, there is a problem in that the transmission efficiency decreases.

The present invention has been made in view of the above-mentioned problems.
An object of the present invention is to provide a clock recovery circuit that can quickly extract a clock component and reduce a preamble signal from an information signal train to improve transmission efficiency.

[Means for Solving Problems] In order to achieve the above object, the glow 2 regeneration circuit of the present invention provides a detection demodulated signal sequence of radio waves arriving in burst form from a master station in a slave station of a time-division digital radio system. a PLL circuit comprising means for extracting a clock component from the clock signal, and means for synchronizing the phase with the extracted clock signal and maintaining the phase synchronized with the previous operation when the radio wave is not received; Until the clock signal extracted from the incoming detection demodulation signal sequence becomes stable,
The structure includes a delay means for controlling the PLL circuit so that the PLL circuit maintains a phase synchronized with the previous operation.

[Example] An example of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram of the clock recovery circuit according to the first embodiment, and FIG. 2 is a time chart explaining the operation of the circuit.
FIG. 3 is a block diagram of the claw reproducing circuit according to the second embodiment, and FIG. 4 is a time chart illustrating the operation of the circuit.

First, a first embodiment will be described based on FIGS. 1 and 2. In FIG. 1, l is an antenna, 2 is a receiver, and 3 is a clock extraction tuning circuit. The receiver a2 has a built-in squelch circuit (not shown). In addition, 10 in the figure is P
Phase comparator (PD) in LL circuit5. Voltage controlled oscillator (
The zero phase comparator 5, which is composed of a VCO) 6, a low frequency filter (LPF) 7, and a hold circuit 8, receives the clock signal extracted by the clock extraction tuning circuit 3 via the waveform shaping comparator 4. At the same time, the output of the voltage controlled oscillator 6 is also input, and their phases are compared.

9 in the figure is a delay circuit, which is provided to fix the oscillation frequency of the voltage controlled oscillator 6 to the previously synchronized phase until the clock signal extracted by the clock extraction tuning circuit 3 becomes stable. ing. That is, focusing on the fact that the squelch signal output from the squelch circuit in the receiver z indicates the arrival of radio waves from the master station, the hold circuit 8 is released using this squelch signal. However, since the arriving radio waves remain unstable for a while, the squelch signal is blocked by the delay circuit 8 during that time.

Next, the operation will be explained.

When time-divided radio waves arrive from the master station.

A receiver 2 inputs this radio wave 100 via an antenna 1, detects and demodulates it, and sends it to a tuning circuit 3 for clock extraction.
Output to. The clock extraction tuning circuit 3 extracts a clock component from the input detection demodulated signal sequence lOO. The extracted clock signal is output to the phase comparator 5 via the waveform shaping comparator 4. The phase comparator 5 compares the phase of the input clock signal with the output of the voltage controlled oscillator 6, and The output of the 0-phase comparator 5, which matches the output phase with the phase of the clock signal, is converted into a direct current by a low frequency waveform generator 7, and is passed through a hold circuit 8 to control the oscillation frequency of the voltage controlled oscillator 6.

Here, as shown in FIG. 2, the hold circuit 8 receives the squelch signal l output from the squelch circuit in the receiving ALZ.
Only the rising edge of ot is controlled by a signal 102 delayed by the delay circuit 9, and is in a pass state while this signal 102 is input, and is in a hold state when not input. Therefore, the delayed squelch signal 102
is output to the hold circuit, a signal from the phase comparator 5 is output to the voltage controlled oscillator 6 via the hold circuit 8, and the phase of the voltage controlled oscillator output is adjusted by this signal.

When the radio wave time slot ends and the radio wave 100 is interrupted, the squelch signal 102 is interrupted without delay (second
(see figure), therefore, the hold circuit 8 enters the hold state and fixes the oscillation frequency of the voltage controlled oscillator 6.

When the next radio wave arrives, the fixed output clock of the voltage controlled oscillator 6 is used until the clock component extracted by the clock extraction tuning circuit 3 becomes stable. Therefore, it is not necessary to preamble a preamble signal to the subsequent radio wave signal train.

Note that the voltage controlled oscillator 6 only needs to have an oscillation frequency that does not fluctuate while the radio waves are interrupted, and therefore does not need to be highly stable.

Next, a second embodiment will be described based on FIGS. 3 and 4. Note that the same parts as in the first embodiment are given the same reference numerals, and a detailed explanation of the parts will be omitted.

Generally, the signal train sent from the master station in a time division multiplexed radio transmission system includes a synchronization signal train with a predetermined pattern in order to synchronize the entire system or to indicate the beginning of each time slot. A signal train is often used.

Focusing on this, the present embodiment detects a synchronization signal train of the above predetermined pattern instead of the squelch signal in the first embodiment, and generates a clock component that continues for a predetermined time after the synchronization signal train. Extract. Then, the voltage controlled oscillator 6 is activated for the duration of the clock component.
The configuration is such that the output frequency of the voltage controlled oscillator 6 is fixed at the end of the information signal sequence.

That is, radio waves arriving from the master station are input to the receiver 23 via the antenna 1, where they are detected.

It is demodulated and becomes a signal sequence 103. The demodulated signal sequence 103 periodically includes a preamble signal 104 and a claim synchronization signal 105. The clock extraction circuit 3 stably extracts the clock during the period of the preamble signal 104,
The demodulated signal sequence 103 is correctly sent to the frame synchronization signal detection circuit 21.

The frame synchronization signal detection circuit 21 detects the frame synchronization signal 1
05 and sends a trigger signal 106 to the timer 22.

In response to this trigger signal 106, the tire 22 outputs a control signal 107 to the hold circuit 8 for turning on the hold circuit 8 for a predetermined period of time.

Since the control signal 107 makes the hold circuit 8 pass through I1T, the signal train from the master station continues, so the clock component is extracted correctly, and therefore, voltage control is applied to this clock signal. Match the output phase of oscillator 6.

In the figure, a detector 23 detects a time slot synchronization signal 108 indicating the beginning of the first succeeding time slot. This detector 23 takes in the demodulated signal train 103 by the output of the voltage controlled oscillator 6, and when a synchronization signal is detected, trigger signal 1
06 is output to the timer 22. In this way, the hold circuit 8 is turned on only for the time when the control signal 107 is output from the timer 22 again, and the output phase of the voltage controlled oscillator 6 is adjusted. Therefore, the preamble signal only needs to be placed in front of the first time slot and is not needed for the next time slot.

[Effects of the Invention] As explained above, the present invention not only extracts the clock of an incoming signal, but also uses the output of a PLL circuit whose phase is synchronized at the time of arrival as a clock when a signal train has not arrived. By doing this, the preamble signal can be removed as unnecessary from the signal train sent by the master station.
This has the effect of increasing signal transmission efficiency, promoting effective use of radio waves, especially in the case of wireless transmission, and reducing device power consumption.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of a claw regeneration circuit according to a first embodiment of the present invention, FIG. 2 is a time chart explaining the operation of the circuit, and FIG. 3 is a clock diagram according to a second embodiment of the present invention. A block diagram of the reproducing circuit, and FIG. 4 is a time chart explaining the operation of the circuit. 1: Antenna 2: Receiver 3: Clock extraction tuning circuit 4: Waveform shaping comparator 5: Phase comparator 6: Voltage controlled oscillator 7: Low frequency filter 8: Hold circuit
9: Delay circuit 10: PLL circuit

Claims (3)

[Claims] (1) In a slave station of a time-division digital radio system, a means for extracting a clock component from a detection demodulated signal sequence of radio waves arriving in burst form from a master station, synchronizing the phase with the extracted clock signal, and When a radio wave is not arriving, a PLL circuit is equipped with a means for maintaining the phase synchronized with the previous operation, and until the clock signal extracted from the incoming detection demodulation signal sequence is stabilized,
A clock recovery circuit comprising: delay means for controlling the PLL circuit so that the PLL circuit maintains a phase synchronized with the previous operation. (2) The delay means includes a squelch circuit that detects the arrival of radio waves from the master station, and a delay circuit that performs the above control of the PLL circuit for a required time from when the squelch circuit detects the arrival of the radio waves. A clock regeneration circuit according to claim 1, characterized in that the clock regeneration circuit comprises: (3) The delay means includes a synchronization signal detection circuit that detects a synchronization signal from a signal train containing a predetermined pattern of synchronization signals, and a synchronization signal detection circuit that is activated from the time when the synchronization signal is detected and waits for the required time. 2. The clock recovery circuit according to claim 1, further comprising a timer for controlling the PLL circuit.