JPH0621933A - Clock recovery circuit - Google Patents

Abstract

(57) [Summary] [Purpose] A clock recovery circuit that can obtain a stable symbol clock even when the zero cross is not located at the center of the decision point of the symbol and the position fluctuates drastically with time. [Configuration] A received signal is a transmission signal in which a predetermined known signal is periodically inserted, and a signal substantially the same as the known signal is input as a reference signal to perform a correlation calculation between the two. , A peak detector 2 for detecting a peak of the correlation output to generate a pulse train signal, a filter 3 for reducing temporal fluctuations of the pulse train signal, a filter output signal and a received signal And a digital PLL circuit 5 for receiving the symbol frequency signal and receiving the symbol frequency signal, averaging the phase fluctuations, and regenerating the transmission symbol clock signal. Clock recovery circuit having a.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a clock recovery circuit for recovering a transmission symbol clock from a received signal in a receiver for digital communication, and particularly in mobile radio such as a portable radio, the time variation of a transmission line is high. The present invention also relates to a clock recovery circuit for recovering a transmission symbol clock from a reception signal, which is suitable for the case where the reception side must be synchronized with the signal on the transmission side.

[0002]

2. Description of the Related Art Conventionally, in a communication system such as a digital radio communication in which it is necessary to recover the transmission symbol clock on the receiving side, the polarity change point (hereinafter referred to as zero cross) of the received signal or the signal demodulated from it is averaged. In general, a method has been generally used in which the symbol clock is regenerated by utilizing the fact that the symbol clock exists at the center of the decision point of the symbol and using the zero cross as a trigger. This conventional clock recovery circuit is shown in FIG. The clock recovery circuit of FIG. 3 receives the received signal and operates by using the zero-cross detector 7 that detects the zero-cross of the demodulated signal and the zero-cross as a trigger, receives the oscillation frequency from the oscillator 6, and regenerates the symbol clock. And a digital PLL circuit 5 for outputting as a reproduction clock output. An example of the received signal (eye pattern) in this case is shown in FIG.

[0003]

However, in the above-described conventional clock recovery circuit, it was possible to easily recover the symbol clock by using the zero cross. However, the transmission path used at this time is mobile. In the case of a transmission line in which the signal in wireless communication is distorted and its characteristics change with time, the received signal is distorted due to the influence of the transmission line, so that the zero cross is not always located at the center position of the decision point of the symbol. In addition, the position of the zero cross may fluctuate extremely due to the influence of time fluctuation, etc. Therefore, there is a drawback that an accurate and stable symbol clock cannot be reproduced.

In view of the above-mentioned drawbacks, the technical problem of the present invention is to provide a stable symbol clock even when the zero cross is not located at the center of the decision point of the symbol and the position fluctuates drastically with time. Is to provide a clock recovery circuit.

[0005]

According to the present invention, the position of a predetermined pattern periodically sent from the transmitting side is detected from the received signal, and the detected position is used as a reference,
A clock recovery circuit is obtained which recovers the symbol clock of a transmission signal.

Further, according to the present invention, in the clock recovery circuit for recovering a transmission symbol clock from a reception signal, the reception signal is a transmission signal in which a predetermined known signal is periodically inserted, Receive the received signal,
A signal that is substantially the same as the known signal is input as a reference signal, a correlator that performs a correlation operation between the two to generate a correlation output, and a peak of the correlation output are detected to generate a pulse train signal. A phase detector that receives a peak detector, the pulse train signal, and a clock signal that is n times the symbol frequency of the received signal to generate a symbol frequency signal, and receives the symbol frequency signal And a digital PLL circuit for regenerating the transmission symbol clock signal by averaging fluctuations.

Also, according to the present invention, there is provided a clock recovery circuit characterized in that the clock recovery circuit is provided with a filter for reducing temporal fluctuations of the pulse train signal.

That is, the present invention comprises a correlator for performing a correlation operation between the received signal and the reference signal, and the correlator detects the position of a previously known pattern which is periodically transmitted from the transmitting side on the receiving side. Then, the symbol clock is regenerated based on the detected position.

[0009]

In the clock recovery circuit of the present invention, the clock recovery circuit does not operate by the zero cross, but operates based on the position of the known pattern that is periodically transmitted, the zero cross of the received signal is not located in the center of the symbol, and , The symbol clock is stably supplied even when the position fluctuates drastically with time.

[0010]

Embodiments of the present invention will now be described with reference to the drawings.

FIG. 1 shows a clock recovery circuit according to an embodiment of the present invention. This clock recovery circuit comprises a correlator 1, a peak detector 2, a filter 3, a frequency divider 4, a digital PLL circuit 5, and an oscillator 6.

As shown in FIG. 2, on the transmitting side, a known signal with a very sharp predetermined autocorrelation is inserted into the transmitting signal at both the transmitting and receiving sides in advance and transmitted. The length of this known signal is such that the cross-correlation with the transmission signal to be actually transmitted is sufficiently small, and the interval of inserting this known signal is as small as possible in the total transmission signal, and , Insert at sufficiently short intervals for fluctuations in the transmission path.

Returning to FIG. 1, the correlator 1 inputs all the above-mentioned transmission signals as reception signals, and the other input of the correlator 1 is the same signal as the known signal inserted on the transmission side. Is input as a reference signal, correlation calculation is performed between the two, and a correlation output (absolute value, the same applies hereinafter) is generated.

As described above, since the known signal has a sharp autocorrelation, the correlation output becomes very large in the part of the signal inserted in the transmission signal and becomes small in the other parts. This correlation output is not easily affected even when the received signal is distorted due to the transmission line characteristics.

The peak detector 2 receives the correlation output, detects a peak, generates a pulse at the position of the peak, and generates a signal which becomes 0 in the other parts. That is, the position of this pulse represents the position of the signal inserted on the transmission side.

The position of this pulse occurs at the interval at which a known signal is inserted on the transmission side when the transmission line does not change and the signal delay between transmission and reception does not change, but the transmission line changes, Alternatively, when the delay between transmission and reception changes, the pulse position also changes, but the change in pulse position with respect to the interval at which a known signal is inserted is very small compared to the change in zero cross with respect to the symbol interval.

The filter 3 receives the signal of this pulse train. The filter 3 is not a frequency domain filter such as an ordinary low pass filter but a time domain filter that reduces the time variation of the pulse train, and can be realized by a digital circuit such as a random walk counter. In this filter 3, the fluctuation of the interval of the input pulse train is set to about 1 symbol. That is, the temporary fluctuation of the pulse train caused by the fluctuation of the characteristics of the transmission path is absorbed by the filter 3 and the distance between the transmitting side and the receiving side gradually changes in a predetermined direction, that is, When the delay amount in the transmission line increases or decreases by a substantially constant amount, the pulse train also shifts following the fluctuation. Therefore, if the output of the peak detector 2 has already changed by 1 symbol or less, the filter 3 can be omitted.

The signal of the pulse train whose fluctuation has become small becomes the phase set input of the frequency divider 4. The output of the oscillator 6 is input to the clock input of the frequency divider 4. The oscillation frequency of the oscillator 6 is n times the symbol frequency of the received signal, and the frequency divider 4 divides this signal by n to generate a signal of the symbol frequency. The phase of the signal of this symbol frequency is set by the pulse train input from the phase setting input. In addition, since this pulse train has an interval variation of about 1 symbol, the clock of the symbol frequency output from one pulse to the next pulse must be the number of symbols in the interval of the known signal inserted on the transmission side. A number of cycles equal to is output. That is, this is
It is the source of the regenerated symbol clock signal.

However, this clock signal cannot be used as a symbol clock signal as it is because the phase of the clock signal changes very greatly at intervals at which known signals are inserted.

Therefore, this signal is input to the digital PLL circuit 5, and by this digital PLL circuit 5,
The phase fluctuations are averaged and output as the final regenerated symbol clock signal. In addition, this digital PL
The output of the oscillator 6 used as the input of the frequency divider 4 can be used to drive the L circuit 5. Therefore, the oscillation frequency of the oscillator 6 needs to be 16 times the symbol clock frequency or higher.

[0021]

As described above, the clock recovery circuit of the present invention is capable of recovering a stable symbol clock with little deterioration even when the received signal is distorted due to the characteristics of the transmission line. Further, even when it is necessary to synchronize with the transmitting side by mobile radio or the like, it is possible to follow the change in the delay between transmission and reception, so that the synchronization can be established based on the regenerated symbol clock.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of a clock recovery circuit according to an embodiment of the present invention.

FIG. 2 is a configuration diagram of a signal transmitted from a transmission side when the clock recovery circuit of the present invention is used.

FIG. 3 is a block diagram showing a configuration of a conventional clock recovery circuit.

FIG. 4 is a diagram showing a received signal eye pattern in the case where there is no deterioration in the transmission path.

[Explanation of Codes] 1 Correlator 2 Peak detector 3 Filter 4 Frequency divider 5 Digital PLL circuit 6 Oscillator 7 Zero cross detector

Claims (3)

[Claims] 1. A clock recovery, characterized in that the position of a predetermined pattern that is periodically sent from the transmitting side is detected from the received signal, and the symbol clock of the transmitted signal is recovered based on the detected position. circuit. 2. A clock recovery circuit for recovering a transmission symbol clock from a reception signal, wherein the reception signal is a transmission signal in which a predetermined known signal is periodically inserted, and the reception signal is received, A signal that is substantially the same as a known signal is input as a reference signal, a correlator that performs a correlation operation between the two to generate a correlation output, and a peak that detects the peak of the correlation output and generates a pulse train signal. A detector, a phase resettable frequency divider that receives the pulse train signal and a clock signal that is n times the symbol frequency of the received signal to generate a symbol frequency signal, and receives the symbol frequency signal and changes the phase And a digital PLL circuit for regenerating the transmission symbol clock signal. 3. The clock recovery circuit according to claim 2, further comprising a filter for reducing temporal fluctuations of the pulse train signal.