JPS63142453A - Semiconductor integrated circuit device - Google Patents

Abstract

PURPOSE:To reduce power consumption by selectively operating first and second oscillating circuits in accordance with an operation mode to generate a display timing signal. CONSTITUTION:Only one of two oscillating circuits OSC1 and OSC2 is selectively operated in accordance with the operation mode of a microcomputer. For example, when the microcomputer performs the operation like calculation, the oscillating circuit OSC1 is operated to generate a clock signal required for this calculation and a timing signal required for the operation of a liquid crystal clock circuit. When the microcomputer does not perform the operation like calculation, the oscillating circuit OSC2 is operated to generate a timing signal required for the display operation and the operation of a timer circuit.

Description

[Detailed Description of the Invention] [Industrial Application] The present invention relates to a semiconductor integrated circuit device that has an information processing function and a display function, such as an electronic desktop calculator or a portable microcomputer. The present invention relates to a technology that is effective for use in semiconductor integrated circuit devices having the following characteristics.

[Conventional technology]

For example, a one-chip microcomputer with a built-in liquid crystal drive circuit is known (#@Hitachi, September 1982).
"Liquid crystal drive type LCDI [Refer to [User's Manual]" published in March).

This semiconductor integrated circuit device LcDIII has a function to reduce power consumption by stopping the operation of the clock oscillation circuit by a program or an external control signal and stopping the operation of the internal circuit. It is provided. The above operation stoppage is canceled by a predetermined time signal generated by a separately provided timer oscillation circuit.

[Problem that the invention seeks to solve]

When, for example, an electronic desktop calculator is configured with a 1-chip microcomputer as described above, the time during which the microcomputer actually performs calculations is extremely short. On the other hand, a display device always needs to perform a display operation in an operating state. Therefore, the inventor of the present application first provided a clock oscillation circuit for forming a clock signal for a microcomputer that performs information processing such as arithmetic operations, and a display oscillation circuit for forming a timing signal for the liquid crystal display. Therefore, we considered reducing power consumption by stopping the operation of the clock cycle light a circuit when the above-mentioned arithmetic operation is not performed.

Even in this case, the zero oscillation circuit, which is a display oscillation circuit that is always in operation, consumes a relatively large amount of current, which causes an increase in the current consumption of the semiconductor integrated circuit device. There is.

An object of the present invention is to provide a semiconductor integrated circuit device that includes a built-in display circuit and achieves low power consumption.

The above and other objects and novel features of the present invention will become apparent from the description of this specification and the accompanying drawings.

[Means for solving problems]

A brief summary of typical inventions disclosed in this application is as follows.

That is, a frequency dividing circuit is provided that forms a display timing signal using a first oscillation circuit that forms a clock signal necessary for the operation of an internal circuit that performs an information processing operation, and this display timing signal and a second oscillation circuit are provided. A display timing signal formed by the circuit is supplied to the display circuit via an OR circuit, and the first oscillation circuit and the second oscillation circuit are selectively brought into operation according to the operation mode.

[For production]

According to the above means, when the internal circuit is in the operating state, the first oscillation circuit that forms the clock signal is put into the operating state to form the clock signal and the display timing signal, and when only the display operation is performed, the first oscillation circuit is in the operating state. 2 oscillation circuit is activated to form a display timing signal.
Power consumption can be reduced by selectively keeping one oscillation circuit in operation at all times.

〔Example〕

FIG. 2 shows a block diagram of an embodiment of a 1-chip microcomputer to which the present invention is applied. In the figure, the part surrounded by the dotted line is an integrated circuit LSI, and each circuit block formed here is one
It constitutes a chip microcomputer and is formed on a single semiconductor substrate such as silicon by a known semiconductor FFI circuit manufacturing technique.

The symbol CPU is a microprocessor, and its main constituent blocks are exemplarily shown as a representative.

A is accumulator, X is index register, CC
is the condition code register, SP is the stack pointer, PCI, PCL are the program counters, CPU-
C0NT is a CPU controller, and ALU is an arithmetic and logic operation unit.

The configuration of such a microprocessor CPU is described, for example, in
Since it is well known from the book ``Basics of Microcomputers'' 174 J, written by Mitsuharu Yada, detailed explanation thereof will be omitted. Note that a cutting signal supplied from the outside or various signals sent to the outside is shown as a signal C.

Denoted by symbol I10 is an input/output boat,
It contains a data transmission direction register therein. Further, the symbol I indicates an input-only port.

What is indicated by the symbol 03CI is an oscillation circuit for forming a clock signal for the microcomputer, and includes, but is not limited to, an external crystal resonator Xtal.
This forms an oscillation signal with a relatively high frequency. This oscillation signal is supplied on the one hand to a clock generation circuit CPG which forms a clock signal. The oscillation signal is used on the other hand as a timing signal for display. Note that since the display timing signal has a relatively low frequency, a frequency dividing circuit as described later is used.

Counter C0UT, frequency divider PR and controller C0
NT constitutes a timer circuit. Although not particularly limited,
In order to keep the timer circuit in constant operation, the timer circuit receives a clock signal formed based on the oscillation signal of the oscillation circuit 0SCI and an oscillation signal formed by the display oscillation circuit 03C2 via a gate circuit as described later. A logical sum signal is supplied. That is, the frequency dividing circuit PR receives the OR signal and forms a one-second pulse. Counter circuit C0UT
counts these 1 second pulses to form time information. The controller C0NT is for setting time and controlling various timers.

The relatively low frequency signal formed by the oscillation circuit 03C2 is passed through the gate circuit to the oscillation circuit 03CI.
The signal is supplied to the liquid crystal drive circuit LCD-DRV together with a display timing signal formed based on the oscillation signal.

This liquid crystal drive circuit L'CD-DRV includes a shift register and a latch circuit that receive display information, a drive circuit that receives the output of the latch circuit, drives segment electrodes of the liquid crystal, and a drive circuit that drives a common electrode. Contains.

One of the two oscillation circuits 03CI and 03C2 is selectively activated depending on the operating mode of the microcomputer. For example, when the microcomputer performs an operation such as calculation, the oscillation circuit 03C1 is activated and forms a clock signal necessary for the calculation and a timing signal necessary for the operation of the liquid crystal clock circuit LDC-DV. Furthermore, when the microcomputer is not performing operations such as arithmetic operations, the oscillation circuit 03C2 is activated and forms timing signals necessary for display operations and timer circuit operations.

The symbol RAM is a random access
It is a memory and is mainly used as a temporary data storage circuit.

The symbol ROM is a read-only memory in which programs for various information processing are stored.

The above circuit blocks are connected to each other by a bus BUS, with the microprocessor CPU as the center. This bus BUS includes a data bus and an address bus.

FIG. 2 shows a block diagram of an embodiment of the oscillation circuits 03CI and 0SC2.

The oscillation circuit 0801 is configured by the following circuit, although it is not particularly limited. CMO3 (complementary MO3) Noah (N
A bias resistor R1 is provided between one input and the output of the OR) gate circuit G1. The gate circuit G1 is
When the control signal C1 supplied to the other input is at a low level (logic "0"), it operates as an inverter circuit (inverting amplifier circuit), and the crystal resonator connected to the above-mentioned human power and output via external terminals, respectively. X1 and capacitor C1, C
2 is provided to perform an oscillating operation.

Further, when the control signal C1 is set to a high level, the gate circuit G1 fixes its output signal to a low level, and therefore stops the oscillation operation.

The oscillation output obtained from the output of the gate circuit G1 is waveform-shaped by the inverter circuit N1.

Although not particularly limited, the output signal of the inverter circuit N1 is frequency-divided via the first frequency dividing circuit DVI and supplied to the clock generation circuit CPG. Clock generation circuit CP
G receives the frequency-divided output φl and generates a clock signal CP necessary for the operation of the internal circuits constituting the microcomputer.
I, CP2, etc. are formed.

The output signal φ1 of the first frequency divider circuit DVI is further frequency-divided by the second frequency divider circuit DV2 to produce a relatively low frequency timing signal φ2° necessary for display operation.

The oscillation circuit 03C2 is composed of the following circuit. C
MO3 (complementary MO3) NOR gate circuit G2
A bias resistor R2 is provided between one input and the output. The gate circuit G2 operates as an inverter circuit (inverting amplifier circuit) when the control signal C2 supplied to the other input is at a low level (logic "0"), and the input and output are connected to each other via external terminals. By providing the connected crystal resonator X2 and capacitors C3 and C4, an oscillation signal φ2 of a relatively low frequency necessary for the above display operation is formed. The gate circuit G2 has a control signal C2
When set to high level, the output signal is fixed to low level, and the above oscillation operation is stopped.

The display timing signal φ2° formed by the frequency dividing circuit DV2 and the display timing signal φ2 formed by the oscillation circuit 03C2 are supplied to an OR gate circuit G3. A timing signal CP3, which is supplied to the liquid crystal drive circuit LCD-DV and the timer circuit, is output from the output of the OR gate circuit G3. In addition, 2
If it is necessary to synchronize two timing signals φ2° and φ2, in other words, if it is necessary to prevent whisker-like pulses from being formed when switching between timing signals φ2 and φ2'', A suitable synchronization circuit may also be provided.

In this embodiment, when the microcomputer performs an operation such as calculation, the control signal C1 is set to low level,
Control signal C2 is set to high level. As a result, the oscillation circuit 03CI becomes operational and forms the clock signals CPI and CP2 necessary for the above-mentioned arithmetic operation. At this time, the output signal of the oscillation circuit 03C2 is fixed at a low level due to the high level of the control signal C2, and is placed in a non-operating state. Therefore, the first and second frequency dividing circuits DVI are activated by the operation of the oscillation circuit 0801.

Display timing signal φ2° formed via DV2
is outputted as a timing signal CP3 via an OR gate circuit G3. This timing signal CP3 also puts the liquid crystal drive circuit LCD-DV and the timer circuit into operation.

On the other hand, when the microcomputer does not perform an operation such as calculation, the control signal CI is at a high level, and the control signal C
2 is set to low level. As a result, the oscillation circuit 03
C2 becomes active and forms a timing signal φ2 necessary for the above display operation. At this time, the oscillation circuit osc
The output signal of i is fixed to a low level by the high level of the control signal CI, and it is placed in a non-operating state. Therefore, the levels of the clock signals CPI and CP2 are fixed at a high level or a low level, so that the microcomputer is placed in a low power consumption mode (halt state).

The display timing signal φ2 generated by the operation of the oscillation circuit 03C2 is outputted as a timing signal CP3 via the OR gate circuit G3. This timing signal CP3 maintains the operating state of the liquid crystal drive circuit LCD-DV and the timer circuit. In this embodiment, since only one of the two oscillation circuits is selectively put into operation according to its operating mode, it is possible to reduce power consumption in the oscillation circuit.

The effects obtained from the above examples are as follows. That is, (1) a frequency dividing circuit is provided that forms a display timing signal using the output signal of the first oscillation circuit that forms a clock signal necessary for the operation of an internal circuit that performs an information processing operation; and a display timing signal formed by a second display oscillation circuit are logically summed and supplied to the display circuit, and the first oscillation circuit and the second oscillation circuit are selectively operated according to the operation mode. put it into working condition. Thereby, when the internal circuit is in the operating state, the first oscillation circuit that forms the clock signal is put into the operating state to form the clock signal and the display timing signal, and when only the display operation is performed, the second oscillation circuit is activated. By controlling so that one oscillation circuit is always selectively activated so that the oscillation circuit is activated to form a display timing signal, it is possible to achieve the effect of reducing power consumption.

By the way, the NOR gate circuit, etc. that make up the above oscillation circuit consumes a relatively large DC current by being biased near the logic threshold voltage in its operating state, so the power consumption of one oscillation circuit is , the current consumption is increased to more than 10% of the entire current consumption of a one-chip microcomputer. Therefore, by applying the present invention, power consumption can be reduced by about 10%.

(2) According to (1) above, it is possible to obtain the effect that the battery life of battery-powered electronic desk calculators and portable microcomputers can be extended.

Although the invention made by the present inventor has been specifically explained above based on Examples, it goes without saying that this invention is not limited to the above Examples and can be modified in various ways without departing from the gist thereof. Nor. For example, the oscillation circuit is
In addition to the crystal oscillation circuits mentioned above, ceramic oscillation circuits and CR
Any oscillation circuit (including a ring oscillator) may be used. Furthermore, a method for selectively controlling the oscillation operation of an oscillation circuit uses a gate circuit as described above, and various embodiments may be employed, such as a method in which the above control signal is supplied to a clock terminal of a clocked inverter circuit. It is something that can be done.

The present invention can be widely used in various semiconductor integrated circuit devices incorporating display circuits and information processing circuits.

〔Effect of the invention〕

A brief explanation of the effects obtained by typical inventions disclosed in this application is as follows. That is, a frequency dividing circuit is provided that forms a display timing signal using the output signal of the first oscillation circuit that forms a clock signal necessary for the operation of an internal circuit that performs an information processing operation, and this display timing signal and a display timing signal are used. The display timing signal formed by the second oscillation circuit of
The oscillation circuit and the second oscillation circuit are selectively activated. Thereby, when the internal circuit is in the operating state, the first oscillation circuit that forms the clock signal is put into the operating state to form the clock signal and the display timing signal, and when only the display operation is performed, the second oscillation circuit is activated. is always set to 1 so that it is in operation and forms the display timing signal.
Power consumption can be reduced by controlling the two oscillation circuits so that they are selectively activated.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an embodiment of an oscillation circuit according to the invention, and FIG. 2 is a block diagram showing an embodiment of the invention applied to a one-chip microcomputer. LSI...Semiconductor integrated circuit device CPU...Microprocessor, CPU-C0NT...CPU controller, A
LU: Arithmetic logic unit, A: Accumulator, X
・Index register, CC ・Status register, S
P...Stack pointer, PCH, PCL...Program counter, RAM...Random access memory,
ROM...read-only memory, Ilo...input/output boat, ■...input-only boat, 03CI...clock oscillation circuit, 03C2...display oscillation circuit, C0UT
・・Counter, C0NT・・Controller, PR・・Frequency dividing circuit, BUS・・Pass, cpc・・Clock generation circuit, LCD‐DRV‐・Liquid crystal drive circuit, DVI, DV2・
・Frequency divider circuit pa＼,

Claims (1)

[Claims] 1. A first oscillation circuit that forms a clock signal necessary for the operation of an internal circuit that performs information processing operations, and a built-in display circuit that receives an output signal from the first oscillation circuit. a frequency dividing circuit that forms a display timing signal; a second oscillation circuit that forms a display timing signal for the display circuit; and a display timing signal formed by the frequency dividing circuit or a display signal formed by the second oscillation circuit. a gate circuit for supplying a timing signal to the display circuit, the first oscillation circuit and the second oscillation circuit;
1. A semiconductor integrated circuit device, wherein an oscillation circuit of the semiconductor device is selectively put into an operating state according to its operating mode. 2. The semiconductor integrated circuit device according to claim 1, wherein the display circuit forms a display signal for dynamically driving a liquid crystal display device. 3. The semiconductor integrated circuit device according to claim 1 or 2, wherein the internal circuit that performs the information processing operation is constituted by a CMOS circuit.