JPS61113303A - Semiconductor integrated circuit - Google Patents
Semiconductor integrated circuitInfo
- Publication number
- JPS61113303A JPS61113303A JP23445784A JP23445784A JPS61113303A JP S61113303 A JPS61113303 A JP S61113303A JP 23445784 A JP23445784 A JP 23445784A JP 23445784 A JP23445784 A JP 23445784A JP S61113303 A JPS61113303 A JP S61113303A
- Authority
- JP
- Japan
- Prior art keywords
- capacitor
- microcomputer
- oscillator
- capacitors
- oscillating frequency
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Inductance-Capacitance Distribution Constants And Capacitance-Resistance Oscillators (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は、CMOS トランジスタをアクティブ素子と
し、容量を含めて同−半婆体基板上に形成し、マイクロ
コンピュータのクロックを発生する半導体集積回路に関
する。[Detailed Description of the Invention] [Industrial Application Field] The present invention provides a semiconductor integrated circuit which uses a CMOS transistor as an active element, is formed on the same half-circuit substrate including a capacitor, and generates a clock for a microcomputer. Regarding.
従来、マイクロコンピュータのシステムクロックとして
は、@2図のようなCR発振器が便用されていた〇
インバータ1.2に用いるトランジスタとしては、電力
消費の少ないこと刀)らCM OS l−ランジスタケ
使用しているOこのCR発k &はCRの時定数できす
る無安定マルチバイブレータで、その発振周及数fは
v v −v
f= 1 /[: C,R(An V、。”th ”
” 2V。。−v、h)’3となる。こ\でvccは或
詠1圧、Vthけインバータの論理スレショルド電圧で
ある。Conventionally, a CR oscillator like the one shown in Figure @2 has been conveniently used as the system clock of a microcomputer.As for the transistor used in the inverter 1.2, a CM OS l-transistor transistor was used because of its low power consumption. This CR oscillation k & is an astable multivibrator whose oscillation frequency and number f are v v - v f = 1 / [: C, R (An V,."th"
"2V..-v,h)'3. Here, vcc is the voltage, and Vth is the logic threshold voltage of the inverter.
■th=1/2VccのときVCは f中172.2CR となる。■When th=1/2Vcc, VC is 172.2CR in f becomes.
ところで、従来のマイクロコンピュータのCR発振器の
発振周波数は、CおよびRヶ一定値として、一義的に固
定されていた。この発掘周111jtdi マイクロコ
ンピュータの処理する最も早い処理速匿に合わせてきめ
る0し刀)しマイクロコンピュータは必ずしも常lCN
市運度ヲ必費とする処a奮行なうものでにない6CMO
8トランジスタは、動作周波数が商くなると、1力消費
が増加し、低消費電力のメリットがなくなる〇従ってマ
イクロコンピュータの処理が最高速襄でない場@vcは
、C8発振器の発振数周仮数を低下することができれば
、′電力消費の点で憔めて有利である。Incidentally, the oscillation frequency of the CR oscillator of a conventional microcomputer was uniquely fixed as C and R being constant values. This excavation period 111jtdi is determined according to the fastest processing speed of microcomputers), and microcomputers are not necessarily always 1CN.
6CMO is not working hard to make city management a necessity.
When the operating frequency of the 8 transistor increases, the power consumption increases and the advantage of low power consumption disappears. Therefore, if the microcomputer's processing speed is not the highest, @vc reduces the oscillation frequency mantissa of the C8 oscillator. If it were possible to do so, it would be extremely advantageous in terms of power consumption.
本発明の目的は、上記の事情に謹み、マイクロコンピュ
ータのS作状況により、発振周波数ケ’g )A VC
可変となしうるCR発撮器?半導体集債回路として提供
することにある。The purpose of the present invention is to reduce the oscillation frequency by adjusting the oscillation frequency by considering the above-mentioned circumstances,
A variable CR transmitter? The purpose is to provide it as a semiconductor integrated circuit.
CtOJ題点r解決するための手段〕
本@明の半導体集積回路は、0MO8トランジスタをア
クティブ素子とし、同−基板上に構成したCR@振器[
訃いて、発振周波数ケ定める複数個の固矩の容量と、前
記容量のおの2のの電気的接続をなすトランスファゲー
トと、前dピトランスファグート金制何する制御回路と
全設置/7たちのであるO
CF’F= 用〕
マイクロコンピュータの必要処理速度VC@−わせて、
プログラマブルに制御回路を動作(、各トランスファゲ
ートのオンオフの組会わせをすることで、発掘周波数?
変化させる。これによって、発振回路の消費電力を最小
にすることができる。Means for solving the CtOJ problem] This semiconductor integrated circuit uses a 0MO8 transistor as an active element and is a CR@oscillator constructed on the same substrate.
Finally, a plurality of fixed rectangular capacitors that determine the oscillation frequency, a transfer gate that electrically connects each two of the capacitors, a control circuit that controls the transfer cost, and all installations/7. The required processing speed of the microcomputer is VC@-.
Programmably operate the control circuit (by turning each transfer gate on and off, you can find the frequency?
change. This allows the power consumption of the oscillation circuit to be minimized.
巣1図に、本発明の一実施例の回路ブロック図金示す。 Figure 1 shows a circuit block diagram of an embodiment of the present invention.
C8発振器の構成は従来例と同じで、インバータ1,2
を直列接続し、その両端3゜4間に容量C1およびイン
バータ1の両端間に抵抗Rを埃絖している。ただし容量
Cは図示のように、複数個の容量C5〜CMの並夕1」
からなり、各容tcs〜CWはトランスファゲート5〜
Nによりその接続がきする◎すなわちトランスファケー
ト5〜Nが制御回路10の制御信号によりオンオフされ
、オンのとき、その対応する容量が接続される。The configuration of the C8 oscillator is the same as the conventional example, with inverters 1 and 2
are connected in series, and a capacitor C1 is connected between both ends thereof, and a resistor R is connected between both ends of the inverter 1. However, the capacitance C is the same as the one shown in the figure, consisting of multiple capacitances C5 to CM1.
Each volume tcs~CW is a transfer gate 5~
The connection is activated by N. In other words, transfers 5 to N are turned on and off by a control signal from the control circuit 10, and when they are on, their corresponding capacitors are connected.
上記の回路では、マイクロコンピュータ(図示してbな
い)から信号10aが制御回路10に入力し・・適宜容
量05〜CNの接続がき19.曾成容量Cが@まる〇
〔全面の効果〕
以上、詳しく述べたように、マイクロコンピュータの処
理速度に応じて、CR@振器の周波数?変化することが
できるから、速い処理速度i必要としない処理実行中に
もクロック周波数を発生する発l#i器が固定していて
最高周波数奮発熾しつづけて、不必要に電力全消賛する
ようなことがない。したがって、少しでも低消費゛電力
を図らなければならないマイクロコンピュータシステム
に、最iMな@振器?得ることができる0In the above circuit, a signal 10a is input from the microcomputer (not shown) to the control circuit 10, and the capacitors 05 to CN are connected as appropriate. The generated capacitance C is @Maru〇 [Overall effect] As detailed above, depending on the processing speed of the microcomputer, CR@frequency of the oscillator? Since the clock frequency can be changed even during processing that does not require high processing speed, the generator that generates the clock frequency is fixed and continues to generate the highest frequency, causing unnecessary consumption of power. Never happened. Therefore, for microcomputer systems that must reduce power consumption as much as possible, is this the most suitable @oscillator? can get 0
第1図は本発明の一実施例、第2図は従来例の回路ブロ
ック図である。
1、2・・、インバータ、 5〜N・−・トランスフ
ァケート、10 ・・・制御回路
C,C5〜CN・・・各首、 R・・・砥仇。
第 1 日
第 2 図FIG. 1 is a circuit block diagram of an embodiment of the present invention, and FIG. 2 is a circuit block diagram of a conventional example. 1, 2..., inverter, 5~N...transfer, 10...control circuit C, C5~CN...each head, R...tooth. Day 1 Figure 2
Claims (1)
上に構成したCR発振器において、発振周波数を定める
複数個の固定の容量と、前記容量のおのおのの電気的接
続をなすトランスファゲートと、前記トランスファゲー
トを制御する制御回路とを設けたことを特徴とする半導
体集積回路。A CR oscillator using a CMOS transistor as an active element and configured on the same substrate includes a plurality of fixed capacitors that determine an oscillation frequency, a transfer gate that electrically connects each of the capacitors, and a control that controls the transfer gate. A semiconductor integrated circuit characterized by being provided with a circuit.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP23445784A JPS61113303A (en) | 1984-11-07 | 1984-11-07 | Semiconductor integrated circuit |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP23445784A JPS61113303A (en) | 1984-11-07 | 1984-11-07 | Semiconductor integrated circuit |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS61113303A true JPS61113303A (en) | 1986-05-31 |
Family
ID=16971297
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP23445784A Pending JPS61113303A (en) | 1984-11-07 | 1984-11-07 | Semiconductor integrated circuit |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS61113303A (en) |
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH04302217A (en) * | 1991-03-29 | 1992-10-26 | Sanyo Electric Co Ltd | Voltage controlled oscillation circuit |
DE4221304C1 (en) * | 1992-06-29 | 1993-09-16 | Siemens Audiologische Technik Gmbh, 91058 Erlangen, De | |
JP2012124807A (en) * | 2010-12-10 | 2012-06-28 | Panasonic Corp | Semiconductor relay |
-
1984
- 1984-11-07 JP JP23445784A patent/JPS61113303A/en active Pending
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH04302217A (en) * | 1991-03-29 | 1992-10-26 | Sanyo Electric Co Ltd | Voltage controlled oscillation circuit |
DE4221304C1 (en) * | 1992-06-29 | 1993-09-16 | Siemens Audiologische Technik Gmbh, 91058 Erlangen, De | |
JP2012124807A (en) * | 2010-12-10 | 2012-06-28 | Panasonic Corp | Semiconductor relay |
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