JPS63140362A - System program loading method for multi-cpu system - Google Patents

Abstract

PURPOSE:To require no exchange of a memory by loading a system program for every CPU to an attached local RAM based on a loaded system program by a main CPU. CONSTITUTION:When a power source is charged, the respective CPUs 20-1-20-n simultaneously make access to a shared loading ROM 50, execute a TAS instruc tion, checks and sets a semaphore flag for the FD of a TAS memory 55 only and one of the CPUs 20-1-20-n initially checking can set the semaphore flag for the FD. The CPU 20-2 obtaining the access right to a floppy disk board 60 refers to specific information and corresponding information according to a next reading processing program and loads the system program in the local RAM 30-1 of the main CPU. Thereafter, the system programs for respective CPUs 20-1-20-n are loaded to the local RAMs 30-1-30-n based on the loaded system program.

Description

[Detailed Description of the Invention] <Industrial Application> The present invention relates to a system program loading method for a tri multi-CPU system, and particularly relates to a method for loading a system program stored in an external storage device into an internal memory provided commonly to each CPU. The present invention relates to a system program loading method for a multi-CPU system in which a loading program stored in a ROM is transferred to each CPU.

<Prior Art> In a multi-CPU system, it is necessary for each CPU to store an execution slot system program in the local memory of each CPU board.

For this reason, each CPU constituting a conventional multi-CPU system
U stores a system program in his own local ROM, and reads a user program from an external storage device such as a floppy according to a loader included in the system program, and writes it into his local RAM.

However, this method has the problem of requiring a large number of ROMs, increasing the burden on the hardware, and making it difficult to change the software.

In order to improve this drawback, the main CPU for loading is determined at the time of system design, and all cP is stored in that ROM.
A program that loads the system program of U is stored, and a program that waits until the loading is completed is stored in the ROM of other CPUs, and then transfers processing to the loaded program when the loading is completed. It is possible to leave it there.

<Problem to be solved by the invention> However, in the method of Party B, the system program transfer process must be executed by the main CPU, but an identification code that designates this main CPU, for example, can be identified by hardware. If you write the slot number (0゜1.2...,n) or board-specific identifier into the shared ROM,
After all, when the system configuration changes, the type of board of the main CPU changes, or the number of the inserted slot changes, the ROM must be replaced with a ROM in which a new program is written, as described above. It requires a huge amount of effort.

In view of the above, an object of the present invention is to provide a system program loading method for a multi-CPU system that can be configured with a small number of ROMs and eliminates the need to replace the ROMs even if the system is changed.

<Means for Solving the Problems> FIG. 1 is a block diagram of a system embodying an embodiment of a system program loading method for a multi-CPU system according to the present invention.

In the figure, 10-1 to 10-n are CPU boards, 20
-1 to 20-n are CPUs, 30-1 to 30-n are local RAMs, 40 is a shared loading ROM board, 50
is a shared loading FLOM.

55 is a TAS memory, 60 is a floppy disk board, 70 is a floppy disk (FD), and 80 is a system bus.

Function> In addition to the system programs necessary for each CPU 20-1 to 20-n, the FD contains information on the correspondence between the identification code and the system program for each CPU, and the main CPU that loads the system program. Including specific information, the shared loading ROM 50 also contains T.
AS (test and set) command, read command to read main CPU specific information etc. from FD70, and FD70
From the main CPU, the system program of the main CPU is
A loading program to be loaded into the local RAM of the PU is included.

When the power is turned on, all CPUs 20-1 to 20-n
accesses the shared loading ROM 50 in terms of hardware, performs RAM check, initializes each register, obtains slot number, etc., and then attempts to execute the TAS instruction.

Each of the CPUs 20-1 to 20-n attempts to execute a TAS command to access the ROM 50 and check and set the FD semaphore flag of the TAS board 90. At this time, the one CPU that performed the first check (the first CPU that executed the TAS instruction) retains control of the semaphore operation and can set the flag, and other CPUs
U judges that the hour and minute are not number 1 and waits for each one.
state.

For example, the CPU 20-2, which has gained access to the FD 70, reads the FD 70 in accordance with the command to read the shared loading ROM 50.
The main CPU specific information and CPU-system program correspondence information are read from the D70, and the system program of the main CPU is read from the FD70 based on the loading program stored in the shared loading ROM 50 by referring to the specific information and correspondence information. Load it into local RAM.

After that, the main CPU loads each CPU to the local RAMs 30-1 to 30-n attached to each CPU 20-1 to 20-n based on the loaded system program.
20-1 to 20-n Load another system program. As a result, the above-mentioned ``wait'' is released, and each CPU becomes capable of processing.

<Embodiment> Next, a multi-CPU system embodying an embodiment of a program loading method for a multi-CPU system according to the present invention will be described with reference to FIGS. 1 and 2.

In FIG. 1, the multi-CPU system includes a shared loading ROM boat 40 connected to a system bus 80;
CPU boards 10-1 to 10-n.

It has a floppy disk board 60.

Each board is specified by the position where it is connected to the system bus 80, that is, by the slot number (0, 1, . . . n, n+1°n+2).

In this embodiment, each CPU board 10-1 to 10-n is a Motorola 68000 series CPU 20-1 to 20-n.
, local RAMs 30-1 to 30-n are installed, and in addition to loading system programs for each CPU, the local RAMs 30-1 to 30-n are also provided with working areas.

The floppy disk board 60 has each CPU 20-1~
A floppy disk (FD) 70 containing a system program for the 20-n can be set. Although not shown, the floppy disk board 60 includes a floppy disk controller (FDC) and a floppy disk drive (FDD).

In addition to the system program for each CPU, the FD70 contains
Correspondence information indicating the correspondence between the identification codes (slot numbers) of the CPUs 20-1 to 20-n and system programs and specific information specifying the main CPU are stored.

=7- The shared loading ROM board 40 is equipped with a shared loading ROM 50, and as shown in FIG. 2, the shared loading ROM 50 stores an initialization program,
A read program for reading TAS commands, main CPU specific information and correspondence information, and a loading program for loading the main CPU system program are stored.

After power-on reset, each of the 68000 series CPUs 20-1 to 20-n accesses the shared loading ROM 50 and executes the program.

The shared loading ROM board 40 includes a TAS memory 55 which is a shared RAM, and allows exclusive access to the floppy disk board 60 by setting a semaphore flag for the FD by the CPU.

FIG. 3 is a flowchart showing the operation of the above embodiment.

First, when the system is powered on, a power-on reset is applied, and each CPU 20-1 to 20-n simultaneously accesses the shared loading ROM 50 and executes the system initialization program stored in the first area. Local R for each CPU board 10-1 to 10-n
A M 30-1 to 30-n are cleared (steps 100 to 104).

Next, each CPU 20-1 to 2o-n reads and executes the TAS command in preparation for accessing the FD 70 (step 106).

At this time, each of the CPUs 20-1 to 20-n tries to check and set the FD semaphore flag in the TAS memory 55 based on the TAS instruction, but only the one CPU that checked first uses the semaphore flag. It is possible to set the FD semaphore flag while retaining control of the operation, and other CPUs enter a "waiting state" (step 10).
8).

Then, the CPU that has gained access to the floppy disk board 60, for example, the CPU 20-2, follows the program for the next read process of the shared loading ROM 50.
Step 110) to read main CPU special hole information and CPU-system program correspondence information from D70;
Referring to this specific information and corresponding information, F according to the program for loading processing of the shared loading ROM 50.
From D70, the system for the main CPU is loaded into the local RAM 30-1 of the main CPU (for example, CPU 2O-1) (step 112).

After that, the main CPU 20-1 uses the local RAM 30.
The local RAM 30- of each CPU 20-2 to 20-n is
The system program for each CPU is sequentially loaded into the CPUs 2 to 30-n (step 114).

After the loading is completed, the main CPU 20-1 sets the bootable flag of the TAS memory 55, and each CPU 20-1
0-1 to 20-n are local RAMs 30-1 to 30-n
Allows you to start the system programs inside. As a result, the wait state of each CPU is released, and CPU20-
1 is the main CPU, and the other CPUs 20-2~CPU
20-n is used as a sub-processor to perform multi-CPU processing in the system (step 116).

Note that when the system configuration is changed, it is only necessary to appropriately rewrite the correspondence information, main CPU identification information, and system program in the FD 70, and there is no need to replace the shared loading ROM 50.

<Effects of the Invention> As explained above, according to the present invention, even if the system configuration changes, a new CPU board is added, or a CPU board is deleted, the information stored in the external storage device can be simply rewritten. Since there is no need to replace the shared ROM, the effort required to change the system is greatly reduced.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing a multi-CPU system according to an embodiment of the present invention, FIG. 2 is an explanatory diagram of the storage contents of a shared loading ROM, and FIG. 3 is a flowchart showing the processing of the multi-CPU system shown in FIG. be. 10-1 to 10-n, , CPU boards 20-1 to 20-n, , CPU 30-1 to 3O-no, local SRAM2O3, shared loading ROM board 500. Shared loading ROM 55...TAS memory 600. Floppy disk board 70, FD (floppy disk) 800. System Bus Patent Applicant Fanuc Co., Ltd. Agent Patent Attorney Chiki Saito ~12-

Claims (1)

[Claims] A main CPU that loads the identification code of each CPU and the correspondence information of the system program in advance into an external storage device that stores the system program to be executed by each CPU.
A shared ROM is provided that stores a program that can be accessed by all CPUs and causes each CPU to perform a specified process after the power is turned on. one CPU that reads specific information of the main CPU from the external storage device by executing an exclusive access instruction stored in the CPU;
U is determined, the main CPU specific information included in the external storage device is read by this selected one CPU, and then the local RA of the main CPU indicated by this specific information is read.
The system program is loaded into M, and the main CPU then refers to the correspondence information and transfers the system program used by each CPU from the external storage device to the local RAM provided in each CPU. A system program loading method for a multi-CPU system characterized by: