JPS63140337A - Instruction taking out device - Google Patents

Abstract

PURPOSE:To easily take out an instruction word in a specific condition, by holding the readout history of the instruction word positioning at the final word of an instruction buffer, and information representing the fact that no branch instruction exists. CONSTITUTION:The instruction word read out from a memory device is held in the instruction buffer 3 at every block unit. And the high-order bit of the address of the instruction word read out from the buffer 3 is held in an instruction counter 10. Next, the block number and the in-block address of the instruction word read out from the buffer 3 are indicated by an instruction pointer register 6. Also, a branch instruction bit FF8 which represents the branch instruction exists in instructions being positioned within a prescribed number of instructions in advance from the end of the block of the buffer 3, and history bits FF7 and 7' which represent the instruction being positioned within the number of instructions has been read out from the buffer 3 previously, are provided. In such way, it is possible to easily take out the instruction word in the specific condition.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to an instruction fetching device in a high-speed information processing device.

(Prior Art) In recent years, high-speed information processing devices are equipped with an instruction buffer for reading an instruction sequence subsequent to an instruction sequence currently being executed from a cache memory and temporarily storing it in parallel with the execution of an instruction. There are many. In addition, the pipeline is equipped with a series of processing stages corresponding to each process of fetching instructions from the instruction buffer, decoding instructions, and preparatory operations on operands, and processes instructions by sequentially passing them through the above series of stages at the cycle of the machine cycle. Processing is often performed.

Conventionally, the following first and second methods are known as methods for fetching instructions in processing devices dedicated to scientific and technical calculations. One such method is to increase the capacity of the instruction buffer to, for example, several bytes, divide it into multiple blocks, and transfer the instruction word being executed in the instruction word area of the storage device to the instruction buffer. At the same time, an address holding means is provided for holding the instruction address of the instruction word held in the above block for each block of the instruction buffer, and the instruction address of the instruction word to be decoded is transferred to the upper block in units of blocks. The clock number on the instruction buffer is determined by searching the address of the address holding means, and instructions are sequentially taken out from the block to the decode stage. The first method according to the prior art is as described above.

In this case, the address on the instruction buffer is different from the address on the main memory, and consists of a block number on the instruction buffer, a word number within the block, and sometimes a word number within the word.

When moving from the end of a certain block to the first instruction word of another block (hereinafter referred to as block crossing), there may be a case where the destination block does not exist on the instruction buffer. In such cases, the conventional method is to read the instruction word at the end of the block from the instruction buffer and then retrieve it from the main memory, or to read the instruction word located within a predetermined number of instructions from the end of the block from the instruction buffer. When issued, this causes an unconditional request to the main memory. This method is the second method according to the prior art.

(Problems to be Solved by the Invention) In the conventional instruction fetching method described above, in the case of the first method, there is a problem that a delay occurs in reading the first instruction word of the transfer destination block. .

In the case of the second method, if the instruction stream changes due to a branch instruction near the end of a block after sending a request, there is a problem in that the request signal that has already been sent must be canceled.

An object of the present invention is to hold an instruction word read from a storage device in a block position in an instruction buffer, hold the upper bit of the address of the instruction word read from the instruction buffer in an instruction counter, and store the instruction word in the instruction buffer. The instruction pointer indicates the block number and intra-block address of the instruction word being read from the instruction buffer, and indicates that a branch instruction exists among the instructions located within a predetermined number of instructions from the end of the block in the instruction buffer. The above disadvantages can be eliminated by having a branch instruction bit indicating that the instructions located within the above number of instructions have been previously read (from the instruction buffer), and an access history bit indicating that there is a history that instructions located within the instruction number have been previously read (from the instruction buffer). An object of the present invention is to provide an instruction retrieval device configured to easily retrieve instruction words in the above.

(Means for Solving the Problems) An instruction fetching device according to the present invention includes an instruction buffer, an instruction counter, an instruction pointer register, an instruction register, a branch instruction bit F/F, an access history F/F, and a control The device is configured to include means.

The instruction buffer is for holding instruction words read from the storage device in units of blocks.

The instruction counter is for holding the upper bits of the address of the instruction word being read from the instruction buffer.

The instruction pointer register is used to indicate the block number and intra-block address of the instruction word being read from the instruction buffer. The instruction register is used to hold the instruction word read from the instruction buffer.

The branch instruction bit F/F' is used to indicate that a branch instruction exists among the instructions located within a predetermined number of instructions from the end of the block of the instruction buffer.

The access history bit F/F is used to indicate that there is a history that the instruction located within the number of instructions has been previously read from the instruction buffer.

The control means detects that the address of the instruction word being read from the block on the instruction buffer is located within a predetermined number of instructions from the end of the block, and also detects that the address of the instruction word being read from the block on the instruction buffer is located within a predetermined number of instructions from the end of the block, and also detects that the address of the instruction word being read from the block on the instruction buffer is located within a predetermined number of instructions from the end of the block, and If the block to be executed does not exist on the instruction buffer, the branch instruction bit F/ corresponding to the block on the instruction buffer is set.
The contents of F and the contents of the Oyohi access history bit F/F are checked, and the conditions are met that all subsequent instructions up to the end of the block have a history that has been previously read from the instruction buffer, and that no branch instructions are included. This is to send a request to the cache memory at times, and to suppress requests to the cache memory when the above conditions are not satisfied.

(Example) Next, the present invention will be described with reference to the drawings. ′
1 is a block diagram showing an embodiment of an instruction fetching device according to the present invention. In FIG. 1, 1 is an instruction buffer write address register, 2 is an instruction buffer write data register, 3 is an instruction buffer, and 4 is an instruction buffer write address register. .14.20 are respectively switching circuits, 5 is an instruction register, 6 is an instruction pointer register, 7 and F are access history bits,
8 is a branch instruction bit F/F, 9 is an instruction register, 10 is an instruction counter, 1] is a block beyond search circuit, 12
13. is a control circuit; Is, 16, 17, and 19 are decoders, respectively, and 21 is a +1 adder.

In this embodiment, the instruction length is 4 bytes, or 32 bits, and the logical address of the instruction is an 80-bit byte address.

The instruction buffer 3 has a configuration of 82 bytes x 64 words, and is realized with a memory element that can be read/written simultaneously.
Each word is used as block o1, block 1, block 2, and block 8, respectively. Each block is loaded with one block of instruction word information in a cache memory (not shown), ie, 512 bytes of information starting on a 512 byte boundary. The instruction buffer write address register 2 is a register for receiving information from the cache memory all at once at the time of loading and writing it to the instruction buffer 3, and has a width of 82 bytes.

The switching circuit 4 selects one of the read outputs comprising 308 words of the instruction buffer, and that output is strobed into the 4-byte instruction register S.

The read address counter 6 of the instruction buffer 3 is called an instruction pointer register. FIG. 2(a) is an explanatory diagram showing the format of the contents of the instruction pointer register 6. Second
In figure (a), bit o.

1 indicates the block number, bits 2 to 5 indicate the word number within the block, and bits 6 to 8 indicate the word number within the word.

When instruction words are read out sequentially from instruction buffer 3, bits 2 to 8 are incremented by +1. The format of the write address counter 1 of the instruction buffer 3 is the same. FIG. 2(b) is an explanatory diagram showing the format of the contents of the address counter l.・In Figure 2(b), bit o
, 1 is the block number, and bits 2 to 5 are the word number. When instruction word information is being loaded from the main memory (not shown) or cache memory to the instruction buffer 3, bits 2 to 5 are incremented by +1, and the instruction words are sequentially written to the instruction buffer 3. .

The control circuit 12 is a control circuit for generating signals for reading instructions from the instruction buffer 3, writing instructions, strobe the instruction register 9, and switching the input/output of the instruction register 9.

The upper 28 bits of the address on the storage device of the instruction word being read from the instruction buffer 3 and the upper 23 bits of the initial value of the instruction counter are set in the instruction counter 10. Inside the plot look-ahead search circuit 11, the upper 28 addresses on the storage device of the instruction words held in blocks 0 to 8 of the instruction buffer 3 are stored.
Bits are retained. When crossing a block, the value of the instruction counter IO is sent to the block stray light search circuit 11,
Compare with the start address of each block in the instruction buffer 3. When the two match, the block number in which the block stray light command is placed is determined from the match output.

Next, the operation of the instruction fetching device according to this embodiment will be explained with reference to FIG.

When the control circuit 12 receives an instruction to start fetching an instruction, it sets the upper 23 bits of the initial value of the instruction counter in the instruction counter 10 via the switching circuit 20, and sets the lower 7 bits of the initial value of the instruction counter to the block of the instruction pointer register 6. Set in the internal word number section and the internal word number section. At the time when the start instruction is received, no valid instruction words are loaded into the instruction buffer 3. Therefore, since there is no hit among blocks θ to 8, the value of the instruction counter 10 is used as the request address, and a block load request is sent to the cache memory.

Since the smallest load destination block number in a block to which no valid command has been loaded is selected preferentially, block O is selected first. The instruction register 8 is a register that supplies a load destination block number to the block number portion of the instruction pointer 6 via the switching circuit 14, and is incremented by 1 each time a request is sent to the cache memory.

When the control circuit 12 receives a response from the cache memory,
32 pi 1-X sent through the entire data signal line 22
I Write 6 pieces of information into each word of block 0 of instruction buffer 3. The information is indicated by the request address8.
It is sent 16 times starting with 2 bytes.

Branch instruction bit F/F8 and access history bit F/
F7, 7 are provided corresponding to each block. After a memory request is sent to the cache memory, the branch instruction bit F/ of the block to be replaced
F8 is set.

When a branch instruction is read in the last word of the block corresponding to the set branch instruction bit, the branch instruction bit F/
F8 is reset.

That is, the instruction word read into the instruction register 5 is checked by the decoder 13 to see if it is a branch instruction. If it is a branch instruction, it is sent to the decoder 1 via the signal line 33.
6, a branch instruction detection signal is sent out. The decoder 16 looks at the information on the signal line 33 and the value set in the instruction pointer register 6 sent via the signal line 18, and if there is a branch instruction in the final word, a corresponding branch is sent via the signal line 34. Sends a reset signal to instruction bit F/F8.

When the lower 7 bits of the instruction pointer register 6 indicate 120, the address of the eighth instruction word from the end of the block is set, and the access history bit F/F7 of the block is output from the decoder 15 onto the signal line 35. is set. Similarly, when the lower 7 bits of the instruction pointer register 6 indicate 127, the address of the last instruction word of the block is set, and the access history bit F of the block is set by the output sent from the decoder 15 on the output signal 36. /F7 is set.

A branch to the middle of the final word (a word in which the lower 7 bits of the instruction pointer register 6 indicate 120 to 127) is caused by another word in the block or a branch instruction existing in another block, and a branch to the final word is executed. Assume that no access has been made previously.

In this case, when the last instruction word of the block is read, the corresponding access history bit F/F7zI is set and the access history bit F/F7 is reset. This state is detected by the decoder 17 and the set access history bit F/
F7 is reset.

Here I will talk about searching for stray blocks.

The lower 7 bits of instruction pointer register 6 are 120 to 12.
7 is detected by the decoder 17,
An instruction is sent via signal line 28 to instruction counter 10 to increment by +1. The instruction pointer register 6 is still accessing block 0, but the upper 28 address pits of the instruction word in the main memory are set to the address of the instruction word of the preceding block. As a result of the search, the block with stray light is instruction buffer 3.
If the block number exists on the instruction pointer register 6, the stray block number is set to the upper two bits of the instruction pointer register 6 via the signal line 24 and the switching circuit 14. If a stray block does not exist on the instruction buffer 3, that is, if the instruction buffer 3 misses, a memory request is sent to the cache memory, and the block number indicated by the instruction register 9 is sent to the signal line. 2
5 and the switching circuit 14.
will be set to the top two pits.

At this time, the present invention is characterized by the timing of the memory request to the cache memory.

The above request timing will be explained below.

As described above, when reading from the instruction buffer 3 approaches the end of a block, the block stray light search circuit 11 searches for the next block. When the instruction buffer 3 misses, a memo IJ IJ quest instruction is sent to the control circuit 12 via the signal line 33. In parallel with this sequence, the decoder 17 checks whether there is a branch instruction among the instructions from the address indicated by the instruction pointer register 6 to the end of the block.

If a branch instruction exists, there is a possibility that the instruction stream will be switched, so it may be useless to send a memory request to load the next block into the cache memory. A decoder 17 is provided corresponding to a block of the instruction buffer 3, and an instruction pointer register 6
If the lower 7 bits of the block indicate a value between 120 and 127, the branch instruction bit F/F8 and access history bit F/F7.7 corresponding to the block are referenced, and control is performed only when all of the above bits are set. A request permission signal is sent to the circuit 12 via the signal line 27. When this permission signal is being sent, there are instructions remaining in the relevant block on the instruction buffer 3 that have not yet been read out, but there are no branch instructions among the remaining instructions.
A request for cache memory is granted to control circuit 12. The control circuit 12 receives a signal from the block stray light search circuit 11 when there is a mismatch between the permission signal and the instruction buffer 3. Look at the memory request,
Send a memory request to cache memory.

If even one bit of the branch instruction bit F/F8 and access history bits F/F7, 7 of the block is reset, a branch instruction exists among the instructions that have not been read from the instruction buffer 3. This indicates that there is a possibility that it exists.

Therefore, even if a memory request is sent from the block stray light search circuit 11 without sending a request permission signal, it is confirmed that the instruction stream of the request to the cache memory has not changed, and all instructions of the block are read out. will be suppressed until

(Effects of the Invention) As explained above, the present invention can improve block crossing quests by retaining the read history of the instruction word located in the final word of the instruction buffer and the information that there is no branch instruction. It can also send several machine cycles earlier.

Another advantage is that there is no need to cancel the request.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an embodiment of an instruction fetching device according to the present invention. FIG. 2 is an explanatory diagram showing the format of data set in the instruction pointer register and address counter shown in FIG. 1. 1■■■1to1-t 1...Instruction buffer write address register 2...
Instruction buffer write data register 3...Instruction buffer 4, IS, ]7.31...Switching circuit 5@...Instruction register 6...Instruction pointer register ff, F...Access history bit F/F8...・Branch instruction bit F/F 9 ・Instruction register 10 ・Instruction counter 11 ・Block stray light search circuit 12 ・Control circuit

Claims (1)

[Claims] an instruction buffer for holding instruction words read from a storage device in units of blocks; an instruction counter for holding high-order bits of the address of the instruction word being read from the instruction buffer; an instruction pointer register for indicating the block number and intra-block address of the instruction word read from the instruction buffer; and an instruction register for holding the instruction word read from the instruction buffer; A branch instruction bit F/F to indicate that a branch instruction exists among the instructions located within the instruction number, and an instruction located within the instruction number that was previously read from the instruction buffer. an access history bit F/F indicating that a history exists, and that the address of the instruction word read from the block on the instruction buffer is located within a predetermined number of instructions from the end of the block; , and if there is no block on the instruction buffer that follows the block from the cache address, the contents of the branch instruction bit F/F corresponding to the block on the instruction buffer and the access history bit are detected. The contents of the F/F are checked, and if the conditions are met that all subsequent instructions up to the end of the block have a history of having been previously read from the instruction buffer and do not include the branch instruction, then the contents of the F/F are stored in the cache memory. 1. An instruction fetching device comprising: control means for sending a request to the cache memory, and suppressing a request to the cache memory when the condition is not satisfied.