JPS63137874U - - Google Patents
Info
- Publication number
- JPS63137874U JPS63137874U JP3081387U JP3081387U JPS63137874U JP S63137874 U JPS63137874 U JP S63137874U JP 3081387 U JP3081387 U JP 3081387U JP 3081387 U JP3081387 U JP 3081387U JP S63137874 U JPS63137874 U JP S63137874U
- Authority
- JP
- Japan
- Prior art keywords
- signal processing
- test
- circuit
- processing circuit
- connector
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000012360 testing method Methods 0.000 claims description 10
- 238000010586 diagram Methods 0.000 description 2
Landscapes
- Tests Of Electronic Circuits (AREA)
Description
第１図は本考案に係る信号処理装置の試験回路
の一実施例を示すブロツク図、第２図は第１図に
示した実施例における各信号処理回路の構成を示
すブロツク図である。
１……入力信号処理回路、２……主要信号処理
回路、３……出力信号処理回路、４……ライン、
５……試験用入力コネクタ、６……試験用出力コ
ネクタ、７……入力切替回路、８……出力ラツチ
、９……プルアツプ抵抗、１０……フラツトケー
ブル。
FIG. 1 is a block diagram showing an embodiment of a test circuit for a signal processing device according to the present invention, and FIG. 2 is a block diagram showing the configuration of each signal processing circuit in the embodiment shown in FIG. 1... Input signal processing circuit, 2... Main signal processing circuit, 3... Output signal processing circuit, 4... Line,
5... Input connector for testing, 6... Output connector for testing, 7... Input switching circuit, 8... Output latch, 9... Pull-up resistor, 10... Flat cable.
Claims (1)
験回路において、 前記一連の信号処理回路の各々に試験用入力コ
ネクタおよび試験用出力コネクタを設けるととも
に、該信号処理回路の前記試験用入力コネクタに
加えられた試験信号を該信号処理回路に加えられ
る前段の信号処理回路からの出力に代えて入力す
る入力切替手段を設け、前記信号処理回路の試験
用出力コネクタと他の信号処理回路の試験用入力
コネクタをケーブルで適宜接続することにより各
信号処理回路を選択的に試験するようにしたこと
を特徴とする信号処理装置の試験回路。[Claims for Utility Model Registration] In a test circuit for a signal processing device having a series of signal processing circuits, each of the series of signal processing circuits is provided with a test input connector and a test output connector; An input switching means is provided for inputting the test signal applied to the test input connector in place of the output from the previous stage signal processing circuit applied to the signal processing circuit, and 1. A test circuit for a signal processing device, characterized in that each signal processing circuit is selectively tested by appropriately connecting test input connectors of the signal processing circuit with a cable.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3081387U JPS63137874U (en) | 1987-03-03 | 1987-03-03 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3081387U JPS63137874U (en) | 1987-03-03 | 1987-03-03 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS63137874U true JPS63137874U (en) | 1988-09-12 |
Family
ID=30835971
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP3081387U Pending JPS63137874U (en) | 1987-03-03 | 1987-03-03 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS63137874U (en) |
-
1987
- 1987-03-03 JP JP3081387U patent/JPS63137874U/ja active Pending
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