JPH038781U - - Google Patents

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Publication number
JPH038781U
JPH038781U JP7029989U JP7029989U JPH038781U JP H038781 U JPH038781 U JP H038781U JP 7029989 U JP7029989 U JP 7029989U JP 7029989 U JP7029989 U JP 7029989U JP H038781 U JPH038781 U JP H038781U
Authority
JP
Japan
Prior art keywords
input
output terminal
output
cable
driver
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP7029989U
Other languages
Japanese (ja)
Other versions
JP2547017Y2 (en
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP1989070299U priority Critical patent/JP2547017Y2/en
Publication of JPH038781U publication Critical patent/JPH038781U/ja
Application granted granted Critical
Publication of JP2547017Y2 publication Critical patent/JP2547017Y2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

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  • Tests Of Electronic Circuits (AREA)

Description

【図面の簡単な説明】[Brief explanation of drawings]

第１図はこの考案の実施例を示す接続図、第２
図及び第３図はそれぞれ従来の出力のみのピンに
関する終端方式を示す接続図、第４図は従来の入
出力伝送路を示す接続図である。 Figure 1 is a connection diagram showing an embodiment of this invention, Figure 2
3 and 3 are connection diagrams showing a conventional termination method for pins for output only, respectively, and FIG. 4 is a connection diagram showing a conventional input/output transmission line.

Claims (1)

【実用新案登録請求の範囲】 ドライバ及びレシーバが接続された第１入出力
端子と、ドライバ及びレシーバが接続された第２
入出力端子とがケーブルで接続された入出力伝送
路において、 上記ケーブルと上記第１入出力端子との間に、
抵抗素子及びインダクタンス素子の並列回路が直
列に挿入され、 その抵抗素子の抵抗値は、これと上記第１入出
力端子に接続されたドライバの出力インピーダン
スとの和が上記ケーブルの抵抗値とほゞ等しくな
るように選定され、 上記インダクタンス素子のインダクタンス値は
上記第１入出力端子の浮遊容量とほゞ共振するよ
うに選定されている入出力伝送路。[Claims for Utility Model Registration] A first input/output terminal to which a driver and a receiver are connected, and a second input/output terminal to which a driver and a receiver are connected.
In an input/output transmission line in which input/output terminals are connected by a cable, between the cable and the first input/output terminal,
A parallel circuit of a resistance element and an inductance element is inserted in series, and the resistance value of the resistance element is approximately equal to the resistance value of the cable, which is the sum of this and the output impedance of the driver connected to the first input/output terminal. The input/output transmission line is such that the inductance value of the inductance element is selected to be equal to the stray capacitance of the first input/output terminal.
JP1989070299U 1989-06-14 1989-06-14 Input / output transmission line of IC tester Expired - Fee Related JP2547017Y2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1989070299U JP2547017Y2 (en) 1989-06-14 1989-06-14 Input / output transmission line of IC tester

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1989070299U JP2547017Y2 (en) 1989-06-14 1989-06-14 Input / output transmission line of IC tester

Publications (2)

Publication Number Publication Date
JPH038781U true JPH038781U (en) 1991-01-28
JP2547017Y2 JP2547017Y2 (en) 1997-09-03

Family

ID=31606341

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1989070299U Expired - Fee Related JP2547017Y2 (en) 1989-06-14 1989-06-14 Input / output transmission line of IC tester

Country Status (1)

Country Link
JP (1) JP2547017Y2 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2006075516A1 (en) * 2005-01-11 2006-07-20 Advantest Corporation Signal transmission system, signal output circuit board, signal receiving circuit board, signal output method and signal receiving method

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2006075516A1 (en) * 2005-01-11 2006-07-20 Advantest Corporation Signal transmission system, signal output circuit board, signal receiving circuit board, signal output method and signal receiving method

Also Published As

Publication number Publication date
JP2547017Y2 (en) 1997-09-03

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Legal Events

Date Code Title Description
LAPS Cancellation because of no payment of annual fees