JPS63136548A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPS63136548A JPS63136548A JP28059186A JP28059186A JPS63136548A JP S63136548 A JPS63136548 A JP S63136548A JP 28059186 A JP28059186 A JP 28059186A JP 28059186 A JP28059186 A JP 28059186A JP S63136548 A JPS63136548 A JP S63136548A
- Authority
- JP
- Japan
- Prior art keywords
- film
- oxidation
- nitride film
- resistant film
- oxide film
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 20
- 238000004519 manufacturing process Methods 0.000 title claims description 8
- 150000004767 nitrides Chemical class 0.000 claims abstract description 32
- 230000003647 oxidation Effects 0.000 claims abstract description 31
- 238000007254 oxidation reaction Methods 0.000 claims abstract description 31
- 238000000034 method Methods 0.000 claims abstract description 16
- 239000000758 substrate Substances 0.000 claims abstract description 15
- 238000002955 isolation Methods 0.000 claims abstract description 9
- 238000005530 etching Methods 0.000 claims abstract description 4
- 239000000463 material Substances 0.000 claims description 6
- 238000000151 deposition Methods 0.000 claims description 5
- 238000000059 patterning Methods 0.000 claims description 5
- 239000013078 crystal Substances 0.000 abstract description 6
- 230000007547 defect Effects 0.000 abstract description 6
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 abstract description 5
- 229910052710 silicon Inorganic materials 0.000 abstract description 5
- 239000010703 silicon Substances 0.000 abstract description 5
- 238000001312 dry etching Methods 0.000 abstract description 2
- 230000008719 thickening Effects 0.000 abstract description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 abstract 2
- 210000003323 beak Anatomy 0.000 abstract 1
- 229910052681 coesite Inorganic materials 0.000 abstract 1
- 229910052906 cristobalite Inorganic materials 0.000 abstract 1
- 239000000377 silicon dioxide Substances 0.000 abstract 1
- 235000012239 silicon dioxide Nutrition 0.000 abstract 1
- 229910052682 stishovite Inorganic materials 0.000 abstract 1
- 229910052905 tridymite Inorganic materials 0.000 abstract 1
- 241000293849 Cordylanthus Species 0.000 description 8
- 229910052581 Si3N4 Inorganic materials 0.000 description 4
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 4
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 4
- 238000010586 diagram Methods 0.000 description 3
- 238000001020 plasma etching Methods 0.000 description 3
- 238000000206 photolithography Methods 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 1
- 239000003795 chemical substances by application Substances 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000002757 inflammatory effect Effects 0.000 description 1
- 230000001590 oxidative effect Effects 0.000 description 1
Landscapes
- Local Oxidation Of Silicon (AREA)
- Element Separation (AREA)
Abstract
Description
【発明の詳細な説明】
〔発明の目的〕
（産業上の利用分野）
本発明は半導体装置の製造方法に関するもので、特に素
子分離法に使用されるものである。DETAILED DESCRIPTION OF THE INVENTION [Object of the Invention] (Industrial Application Field) The present invention relates to a method for manufacturing a semiconductor device, and is particularly used in an element isolation method.
（従来の技術）
従来、半導体集積回路の素子分離には選択酸化法が用い
られていた。この選択酸化法を第４図ないし第６図を用
いて説明する。(Prior Art) Conventionally, a selective oxidation method has been used for element isolation of semiconductor integrated circuits. This selective oxidation method will be explained using FIGS. 4 to 6.
まず第４図に示すようにシリコン基板１１を熱酸化して
パッド酸化膜１２を例えば９００に成長させる。その後
シリコン窒化膜ノ３を例えば３ｏｏｏＫ堆積する。次い
で第５図に示すように写真蝕刻法によってシリコン窒化
膜１３をパターニングして開口部を設ける。次いで第６
図に示すようにシリコン窒化膜１３を耐酸化膜として１
選択酸化を行ない、酸化膜１４を例えば５ｏｏｏ＆成長
させ、その後シリコン窒化膜１３をＲＩＥ（反応性イオ
ンエツチング）によって除去して、素子分離用のフィー
ルドは化膜か完成した。First, as shown in FIG. 4, a silicon substrate 11 is thermally oxidized to grow a pad oxide film 12 to a thickness of, for example, 900 mm. After that, a silicon nitride film 3, for example, 300K is deposited. Next, as shown in FIG. 5, the silicon nitride film 13 is patterned by photolithography to form openings. Then the 6th
As shown in the figure, a silicon nitride film 13 is used as an oxidation-resistant film.
Selective oxidation is performed to grow the oxide film 14 by, for example, 500 mm, and then the silicon nitride film 13 is removed by RIE (reactive ion etching) to complete the field for element isolation.
（発明か解決しようとする問題点）
従来技術であるＬＯＣＯ８法は、素子分離技術として半
導体技術にひろく用いられている。し〃・し、いわゆる
「バーズビーク」のため素子分離領域の微細化の障害と
なっている。そのため、耐酸化膜である窒化膜厚を厚く
すればバーズビークをお芒えることができるか、窒化、
膜厚が厚すき′ると、窒化膜開口部のエツジ部でのシリ
コン基板へのストレスが大きくなυ、シリコン基叛１１
に結晶欠陥か入っ１しまりという問題か起きてくる。ま
た窒化膜開口部が微細化してくると、バーズビーク形成
のため、フィールド酸化膜が窒化膜開口部での嘔化剤不
足のため、フィールド膜減シする問題もおこっている。(Problems to be Solved by the Invention) The LOCO8 method, which is a conventional technique, is widely used in semiconductor technology as an element isolation technique. However, the so-called "bird's beak" is an obstacle to miniaturization of element isolation regions. Therefore, it is possible to eliminate the bird's beak by increasing the thickness of the nitride film, which is an oxidation-resistant film.
As the film thickness increases, stress on the silicon substrate at the edge of the nitride film opening increases.
However, problems such as crystal defects or lumps may occur. Further, as the openings in the nitride film become finer, a problem arises in that the field oxide film is reduced due to the lack of an inflammatory agent in the openings of the nitride film due to the formation of bird's beaks.
本発明は上記実情に鑑みてなされたもので、バーズビー
クを抑えかつ半導体基板の結晶欠陥のない微細化可能な
選択酸化法を有した半導体装置の製造方法を提供しよう
とするものである。The present invention has been made in view of the above-mentioned circumstances, and it is an object of the present invention to provide a method for manufacturing a semiconductor device using a selective oxidation method that suppresses bird's beak and allows miniaturization without crystal defects in a semiconductor substrate.
〔発明の構成）
（問題点を解決するための手段と作用）本発明は、耐酸
化膜パターンのエツジ部のみを薄くシ、その他の領域を
厚くすることで、半導体基板にかかるストレスを極少化
して結晶欠陥を防ぎかつバーズビークを抑える。そのた
めに半導体基板上の第１の薄い耐酸化膜（窒化膜等）上
に。[Structure of the Invention] (Means and Effects for Solving the Problems) The present invention minimizes the stress applied to the semiconductor substrate by thinning only the edge portion of the oxidation-resistant film pattern and thickening the other regions. to prevent crystal defects and suppress bird's beak. For this purpose, a first thin oxidation-resistant film (nitride film, etc.) is formed on the semiconductor substrate.
耐酸化膜削除時に削除しにくい物質膜を介して厚い＃！
２の耐酸化膜を堆積し、該膜をパターニング後、該膜の
開口より狭い開口で第１の耐酸化膜をバターニング稜、
フィールド酸化するものである。# Thick through the material film that is difficult to remove when removing the oxidation resistant film!
After depositing the second oxidation-resistant film and patterning the film, the first oxidation-resistant film is patterned with an opening narrower than the opening of the first oxidation-resistant film.
It is field oxidized.
（実施例）
以下図面を参照して本発明の一実施例全説明する。ｗＪ
１図（ａ）に示される如くシリコン基板２１を酸化して
、パッド酸化膜２２を例えば５００−Ｘ、成長させ、そ
の上に第１の窒化膜２３を１ｏｏｏＵ堆、ｆｆｔＬ、（
−（Ｄ後ＣＶＤ ８１０．ｉ （ＣＶＤ Ｋ ！ ル８
１０２，１２４を５００人堆積する。次に第１図（ｂ）
に示すように第２の窒化膜２５を堆積し、その上にレジ
スト膜２６を設けてこれをパターニング後、ＣＤＥ（等
方性ドライエツチング）で等方的に第２の窒化膜２５を
エツチングパターニングする。次に第１図（Ｃ）に示す
ようにＲＩｇ （反応性イオンエツチング）によってＣ
ＶＤ ｓｉｏ、膜２４と第１の窒化膜２３をエツチング
パターニングする。これにより第２の窒化膜２５の開口
部２５．より狭い開口部２３ｍを第１の窒化膜２３につ
くることができる。その後第１図（ｄ）の如くレジスト
膜２６をエツチング除去して選択酸化を行ない、フィー
ルド酸化膜２７を例えば８０００Ａ成長てせて素子分離
領域が完成するものである。(Embodiment) An embodiment of the present invention will be fully described below with reference to the drawings. wJ
As shown in FIG. 1(a), the silicon substrate 21 is oxidized to grow a pad oxide film 22 with a thickness of, for example, 500X, and a first nitride film 23 is deposited thereon with a thickness of 1oooU, fftL, (
-(CVD 810.i (CVD K! Le 8
Deposit 102,124 for 500 people. Next, Figure 1(b)
As shown in FIG. 2, a second nitride film 25 is deposited, a resist film 26 is provided thereon, and this is patterned.The second nitride film 25 is isotropically etched and patterned using CDE (isotropic dry etching). do. Next, as shown in FIG. 1(C), C
Using VD sio, the film 24 and the first nitride film 23 are etched and patterned. As a result, the opening 25 of the second nitride film 25. A narrower opening 23m can be formed in the first nitride film 23. Thereafter, as shown in FIG. 1(d), the resist film 26 is removed by etching and selective oxidation is performed, and the field oxide film 27 is grown to a thickness of, for example, 8000 Å, thereby completing the element isolation region.
第２図は本発明の異なる実施例でおる。即ち第２の窒化
膜２５を堆積後、これを写真蝕刻法等によりパターニン
グし、第２の窒化膜２５上にＣＶＤ８１０、 ヲ例えば
２０００Ａ堆積後、 ＲＴＥｆＣＶＤ８１０２をエッチ
パックすることにより、第２の窒化膜２５にＣＶＤ 、
ＳｉＯ，膜よりなる側壁２８を形成する。FIG. 2 shows a different embodiment of the invention. That is, after depositing the second nitride film 25, it is patterned by photolithography or the like, and after CVD810 is deposited on the second nitride film 25 for, for example, 2000A, RTEfCVD8102 is etch-packed to form the second nitride film. CVD on 25,
A side wall 28 made of SiO film is formed.
その後ＲＩＥによって第１の窒化膜２３をパターニング
し、フィールド酸化を行なうものである。Thereafter, the first nitride film 23 is patterned by RIE, and field oxidation is performed.
第３図は本発明の更に異なる実施例である。即ち第２の
窒化膜２５を堆積後、多結晶シリコン膜２９を例えば４
０００Ａ堆積し、写真蝕刻法で第２の窒化膜２５．多結
晶シリコン膜２９をパターニングする。（第３図（ａ）
）。その後多結晶シリコン膜２９を熱酸化後（これによ
り熱酸化膜３０は膨張する）、その酸化膜３０をマスク
にして第１の窒化膜２３をパターニングしく第３図（ｂ
） ） ％その後フィールド酸化するものである。FIG. 3 shows a further different embodiment of the invention. That is, after depositing the second nitride film 25, the polycrystalline silicon film 29 is
A second nitride film 25.000A is deposited and photolithographically etched. The polycrystalline silicon film 29 is patterned. (Figure 3(a)
). Thereafter, after thermally oxidizing the polycrystalline silicon film 29 (this causes the thermal oxide film 30 to expand), the first nitride film 23 is patterned using the oxide film 30 as a mask, as shown in FIG.
) ) % is then field oxidized.
前記第１図の実施例で示したように、窒化膜開口エツジ
部では第１の窒化膜２３は薄く、その他の領域では第１
の窒化膜２３及び第２の窒化膜２５で覆われて厚いため
、窒化膜開口エツジ部でのストレスが緩和され、従って
Ｓｉ基板２１の結晶欠陥を防ぎ、かつバーズビークを抑
えることができる。ま次第２因、第３図の方法では、第
２の窒化膜２５をパターニング後、第１の窒化膜開口部
２３、を形成するためのマスクとなる開口部を。As shown in the embodiment of FIG. 1, the first nitride film 23 is thin at the edge of the nitride film opening, and is thin in other regions.
Since it is covered with a thick nitride film 23 and a second nitride film 25, the stress at the edge of the nitride film opening is alleviated, thereby preventing crystal defects in the Si substrate 21 and suppressing bird's beak. Second, in the method shown in FIG. 3, after patterning the second nitride film 25, an opening to serve as a mask for forming the first nitride film opening 23 is formed.
側壁２８．酸化膜３０の膨出部で狭くしたため。Side wall 28. This is because the bulge of the oxide film 30 narrows the area.
レジストパターンより微細化が可能で、より微細化され
た素子分離が実現できる。その上パッド酸化膜２２がな
いと、一段とバーズビークを抑えることができるもので
ある。It can be made finer than a resist pattern, and it is possible to achieve finer element isolation. Moreover, without the pad oxide film 22, bird's beak can be further suppressed.
以上説明した如く本発明によれば、バーズビークを抑え
、半導体基板の結晶欠陥がなく、微細化が可能な選択酸
化法を有した半導体装置の製造方法が提供できるもので
ある。As described above, according to the present invention, it is possible to provide a method for manufacturing a semiconductor device using a selective oxidation method that suppresses bird's beak, has no crystal defects in the semiconductor substrate, and allows miniaturization.
第１図は本発明の一実施例の工程説明図、第２図、第３
図は本発明の異なる実施例の工程説明図、第４図ないし
第６図は従来例の工程説明図である。
２１・・・シリコン基板、２２・・・パッド酸化膜、２
３・・・第１の窒化膜（第１の耐酸化膜）、２３ｍ。
２５、−・・開口部、 ２４ 、２８−・ＣＶＤ ８
１０．膜。
２６・・・レジスト膜、２７・・・フィールド酸化膜。
２９・・・多結晶シリコン、３０・・・酸化膜。
第１区
第 ２ ロ
第 ３ 図Figure 1 is a process explanatory diagram of one embodiment of the present invention, Figures 2 and 3 are
The figures are process explanatory diagrams of different embodiments of the present invention, and FIGS. 4 to 6 are process explanatory diagrams of conventional examples. 21... Silicon substrate, 22... Pad oxide film, 2
3...First nitride film (first oxidation-resistant film), 23m. 25, --- opening, 24, 28-, CVD 8
10. film. 26...Resist film, 27...Field oxide film. 29... Polycrystalline silicon, 30... Oxide film. 1st ward, 2nd ro, 3rd figure
Claims (3)
半導体基板を選択的に酸化して素子分離を行なう半導体
装置の製造方法において、前記半導体基板上に第１の耐
酸化膜を堆積後、耐酸化膜に対してエッチングに関して
選択性のある第１の物質膜を前記第１の耐酸化膜上に形
成し、前記第１の物質膜上に前記第１の耐酸化膜より厚
い第２の耐酸化膜を堆積し、該第２の耐酸化膜をパター
ニング後、前記第１の耐酸化膜、第１の物質膜をエッチ
ング、パターニングして前記第２の耐酸化膜開口部より
狭い開口部を前記第１の耐酸化膜に形成することを特徴
とする半導体装置の製造方法。(1) In a method for manufacturing a semiconductor device in which an oxidation-resistant film pattern is formed on the surface of a semiconductor substrate and then the semiconductor substrate is selectively oxidized to perform element isolation, after depositing a first oxidation-resistant film on the semiconductor substrate; , a first material film having etching selectivity with respect to the oxidation-resistant film is formed on the first oxidation-resistant film, and a second material film thicker than the first oxidation-resistant film is formed on the first material film. After depositing an oxidation resistant film and patterning the second oxidation resistant film, etching and patterning the first oxidation resistant film and the first material film to form an opening narrower than the second oxidation resistant film opening. A method for manufacturing a semiconductor device, characterized in that a portion is formed on the first oxidation-resistant film.
の物質膜がＣＶＤＳｉＯ＿２膜であることを特徴とする
特許請求の範囲第１項に記載の半導体装置の製造方法。(2) the first and second oxidation-resistant films are nitride films;
2. The method of manufacturing a semiconductor device according to claim 1, wherein the material film is a CVDSiO_2 film.
の耐酸化膜開口部を形成するためのマスクとなる開口部
を狭くする工程を具備することを特徴とする特許請求の
範囲第１項に記載の半導体装置の製造方法。(3) After patterning the second oxidation-resistant film,
2. The method of manufacturing a semiconductor device according to claim 1, further comprising the step of narrowing an opening serving as a mask for forming an oxidation-resistant film opening.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP28059186A JPS63136548A (en) | 1986-11-27 | 1986-11-27 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP28059186A JPS63136548A (en) | 1986-11-27 | 1986-11-27 | Manufacture of semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS63136548A true JPS63136548A (en) | 1988-06-08 |
| JPH0338733B2 JPH0338733B2 (en) | 1991-06-11 |
Family
ID=17627162
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP28059186A Granted JPS63136548A (en) | 1986-11-27 | 1986-11-27 | Manufacture of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS63136548A (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5397733A (en) * | 1993-05-21 | 1995-03-14 | Hyundai Electronics Industries Co., Ltd. | Method for the construction of field oxide film in semiconductor device |
| US5403770A (en) * | 1993-04-22 | 1995-04-04 | Hyundai Electronics Industries Co., Ltd. | Method for forming a field oxide film in a semiconductor device |
| US5445990A (en) * | 1993-05-21 | 1995-08-29 | Hyundai Electronics Industries Co., Ltd. | Method for forming a field oxide film in a semiconductor device |
| US5679600A (en) * | 1995-10-11 | 1997-10-21 | Micron Technology, Inc. | Double locos for submicron isolation |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6068631A (en) * | 1983-09-26 | 1985-04-19 | Toshiba Corp | Manufacture of semiconductor device |
| JPS6144442A (en) * | 1984-08-08 | 1986-03-04 | Nec Corp | Manufacture of semiconductor device |
-
1986
- 1986-11-27 JP JP28059186A patent/JPS63136548A/en active Granted
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6068631A (en) * | 1983-09-26 | 1985-04-19 | Toshiba Corp | Manufacture of semiconductor device |
| JPS6144442A (en) * | 1984-08-08 | 1986-03-04 | Nec Corp | Manufacture of semiconductor device |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5403770A (en) * | 1993-04-22 | 1995-04-04 | Hyundai Electronics Industries Co., Ltd. | Method for forming a field oxide film in a semiconductor device |
| US5397733A (en) * | 1993-05-21 | 1995-03-14 | Hyundai Electronics Industries Co., Ltd. | Method for the construction of field oxide film in semiconductor device |
| JPH0799190A (en) * | 1993-05-21 | 1995-04-11 | Hyundai Electron Ind Co Ltd | Preparation of semiconductor element field oxide film |
| US5445990A (en) * | 1993-05-21 | 1995-08-29 | Hyundai Electronics Industries Co., Ltd. | Method for forming a field oxide film in a semiconductor device |
| US5679600A (en) * | 1995-10-11 | 1997-10-21 | Micron Technology, Inc. | Double locos for submicron isolation |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0338733B2 (en) | 1991-06-11 |
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