JPS63134749U - - Google Patents
Info
- Publication number
- JPS63134749U JPS63134749U JP1987028451U JP2845187U JPS63134749U JP S63134749 U JPS63134749 U JP S63134749U JP 1987028451 U JP1987028451 U JP 1987028451U JP 2845187 U JP2845187 U JP 2845187U JP S63134749 U JPS63134749 U JP S63134749U
- Authority
- JP
- Japan
- Prior art keywords
- light emitting
- emitting diode
- line
- power line
- control signal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 230000003287 optical effect Effects 0.000 claims description 4
- 239000000758 substrate Substances 0.000 claims 2
- 238000010292 electrical insulation Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/42—Wire connectors; Manufacturing methods related thereto
- H01L24/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L24/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4912—Layout
- H01L2224/49175—Parallel arrangements
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Dot-Matrix Printers And Others (AREA)
- Printers Or Recording Devices Using Electromagnetic And Radiation Means (AREA)
- Exposure Or Original Feeding In Electrophotography (AREA)
Description
第１図は本考案の光プリンタヘツドの一実施例
を示す部分拡大平面図、第２図は第１図のＹ―Ｙ
線拡大断面図、第３図は従来の光プリンタヘツド
の部分拡大平面図である。
１：電気絶縁基板、２：共通電力線、３：個別
駆動線、４：制御信号線、５：個別電力線、６：
発光ダイオード素子、７：スイツチング用集積回
路素子。
FIG. 1 is a partially enlarged plan view showing an embodiment of the optical printer head of the present invention, and FIG. 2 is a Y-Y line in FIG.
FIG. 3 is a partially enlarged plan view of a conventional optical printer head. 1: Electrical insulation board, 2: Common power line, 3: Individual drive line, 4: Control signal line, 5: Individual power line, 6:
Light emitting diode element, 7: Integrated circuit element for switching.
Claims (1)
電極を有する複数個の発光ダイオード素子と、ｂ
該発光ダイオード素子の一方の電極に共通に接続
される共通電力線と、ｃ前記発光ダイオード素子
の他方の電極に接続される個別駆動線と、ｄ前記
個別駆動線の他端に接続されるスイツチング用集
積回路素子と、ｅ該集積回路素子に接続される制
御信号線及び個別電力線とを取着形成して成る光
プリンタヘツドにおいて、前記共通電力線及び制
御信号線の一端を電気絶縁基板の長片側端部及び
短片側端部にそれぞれ分離して導出させたことを
特徴とする光プリンタヘツド。 A plurality of light emitting diode elements having a pair of electrodes on one surface of a rectangular electrically insulating substrate; b
a common power line commonly connected to one electrode of the light emitting diode element, c an individual drive line connected to the other electrode of the light emitting diode element, and d a switching line connected to the other end of the individual drive line. In an optical printer head formed by attaching and forming an integrated circuit element and a control signal line and an individual power line connected to the integrated circuit element, one end of the common power line and the control signal line is connected to one end of the long side of the electrically insulating substrate. What is claimed is: 1. An optical printer head, characterized in that it is separated into a short end and a short end.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1987028451U JPS63134749U (en) | 1987-02-26 | 1987-02-26 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1987028451U JPS63134749U (en) | 1987-02-26 | 1987-02-26 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS63134749U true JPS63134749U (en) | 1988-09-05 |
Family
ID=30831424
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1987028451U Pending JPS63134749U (en) | 1987-02-26 | 1987-02-26 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS63134749U (en) |
-
1987
- 1987-02-26 JP JP1987028451U patent/JPS63134749U/ja active Pending