JPS63133578A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPS63133578A JPS63133578A JP61281045A JP28104586A JPS63133578A JP S63133578 A JPS63133578 A JP S63133578A JP 61281045 A JP61281045 A JP 61281045A JP 28104586 A JP28104586 A JP 28104586A JP S63133578 A JPS63133578 A JP S63133578A
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor
- light
- junction
- type semiconductor
- photoelectric conversion
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 97
- 238000006243 chemical reaction Methods 0.000 claims abstract description 21
- 239000000758 substrate Substances 0.000 claims abstract description 12
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 claims abstract description 9
- 229910052736 halogen Inorganic materials 0.000 claims abstract description 9
- 150000002367 halogens Chemical class 0.000 claims abstract description 9
- 229910052739 hydrogen Inorganic materials 0.000 claims abstract description 9
- 239000001257 hydrogen Substances 0.000 claims abstract description 9
- 239000013078 crystal Substances 0.000 claims description 12
- 238000002425 crystallisation Methods 0.000 claims description 8
- 230000008025 crystallization Effects 0.000 claims description 8
- 238000000034 method Methods 0.000 abstract description 14
- 229910021417 amorphous silicon Inorganic materials 0.000 abstract description 3
- 239000011521 glass Substances 0.000 abstract description 3
- 230000015572 biosynthetic process Effects 0.000 abstract 2
- 238000000137 annealing Methods 0.000 description 9
- 238000005224 laser annealing Methods 0.000 description 4
- 238000004519 manufacturing process Methods 0.000 description 4
- 238000002955 isolation Methods 0.000 description 3
- 238000005268 plasma chemical vapour deposition Methods 0.000 description 3
- 230000006866 deterioration Effects 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 239000013081 microcrystal Substances 0.000 description 2
- 230000003287 optical effect Effects 0.000 description 2
- 230000002093 peripheral effect Effects 0.000 description 2
- 230000001737 promoting effect Effects 0.000 description 2
- 238000004544 sputter deposition Methods 0.000 description 2
- 239000012808 vapor phase Substances 0.000 description 2
- PXGOKWXKJXAPGV-UHFFFAOYSA-N Fluorine Chemical compound FF PXGOKWXKJXAPGV-UHFFFAOYSA-N 0.000 description 1
- 238000001069 Raman spectroscopy Methods 0.000 description 1
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical group [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- DYRBFMPPJATHRF-UHFFFAOYSA-N chromium silicon Chemical compound [Si].[Cr] DYRBFMPPJATHRF-UHFFFAOYSA-N 0.000 description 1
- 239000002131 composite material Substances 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 238000005520 cutting process Methods 0.000 description 1
- 238000007872 degassing Methods 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 238000005566 electron beam evaporation Methods 0.000 description 1
- 238000000605 extraction Methods 0.000 description 1
- 229910052731 fluorine Inorganic materials 0.000 description 1
- 239000011737 fluorine Substances 0.000 description 1
- AMGQUBHHOARCQH-UHFFFAOYSA-N indium;oxotin Chemical compound [In].[Sn]=O AMGQUBHHOARCQH-UHFFFAOYSA-N 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 230000001678 irradiating effect Effects 0.000 description 1
- 230000031700 light absorption Effects 0.000 description 1
- 238000004518 low pressure chemical vapour deposition Methods 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 229910052760 oxygen Inorganic materials 0.000 description 1
- 239000001301 oxygen Substances 0.000 description 1
- 238000002161 passivation Methods 0.000 description 1
- 238000001782 photodegradation Methods 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 239000010453 quartz Substances 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N silicon dioxide Inorganic materials O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
- 238000001179 sorption measurement Methods 0.000 description 1
- 238000005507 spraying Methods 0.000 description 1
- XOLBLPGZBRYERU-UHFFFAOYSA-N tin dioxide Chemical group O=[Sn]=O XOLBLPGZBRYERU-UHFFFAOYSA-N 0.000 description 1
- 229910001887 tin oxide Inorganic materials 0.000 description 1
Classifications
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02E—REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
- Y02E10/00—Energy generation through renewable energy sources
- Y02E10/50—Photovoltaic [PV] energy
- Y02E10/545—Microcrystalline silicon PV cells
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02E—REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
- Y02E10/00—Energy generation through renewable energy sources
- Y02E10/50—Photovoltaic [PV] energy
- Y02E10/546—Polycrystalline silicon PV cells
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02E—REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
- Y02E10/00—Energy generation through renewable energy sources
- Y02E10/50—Photovoltaic [PV] energy
- Y02E10/548—Amorphous silicon PV cells
Landscapes
- Photovoltaic Devices (AREA)
Abstract
Description
【発明の詳細な説明】
「発明の利用分野」
この発明は、光照射により光起電力を発生し得る接合を
少なくとも1つ有するアモルファス半導体を含む非単結
晶半導体を、絶縁表面を有する基板に設けた光電変換素
子(単に素子ともいう)を複数個電気的に直列接続した
、高い電圧の発生の可能な光電変換装置に関する。DETAILED DESCRIPTION OF THE INVENTION Field of Application of the Invention The present invention is directed to a method in which a non-single crystal semiconductor including an amorphous semiconductor having at least one junction capable of generating photovoltaic force upon irradiation with light is provided on a substrate having an insulating surface. The present invention relates to a photoelectric conversion device that is capable of generating high voltage and has a plurality of photoelectric conversion elements (also simply referred to as elements) electrically connected in series.
「従来の技術」
従来、水素またはハロゲン元素が添加された非単結晶半
導体としてアモルファス半導体が知られている。しかし
、かかる半導体はアモルファス構造を有し、結晶性を積
極的に用いていないため、PIN接合におけるI型半導
体層のキャリアの空乏層が0.3μ以下と狭く、またA
Ml 、 5 (100mW/cmりでの光照射に対し
空乏層がさらに短くなり、劣化が生じてしまった。"Prior Art" Conventionally, amorphous semiconductors are known as non-single crystal semiconductors to which hydrogen or halogen elements are added. However, since such semiconductors have an amorphous structure and do not actively use crystallinity, the carrier depletion layer of the I-type semiconductor layer in the PIN junction is as narrow as 0.3μ or less, and the A
Ml, 5 (The depletion layer became even shorter when irradiated with light at about 100 mW/cm, resulting in deterioration.
「本発明が解決しようとする問題点」
かかるアモルファス半導体を含む非単結晶半導体に対し
、光照射により電子およびホールを発生させる活性のI
型半導体領域での結晶化を助長せしめて、特に長波長光
に対する集収効率を向上せしめ、変換効率の向上が求め
られている。更に、PIN接合を有する光電変換装置に
あっては、■型半導体での空乏層の幅を1μ以上と大き
くするとともに、集積化のための連結部は結晶化をせず
にアモルファス構造の高抵抗領域のまま残存せしめ、こ
の領域での半導体を介してのリークの発生を防ぐことが
求められている。"Problems to be Solved by the Present Invention" Active I which generates electrons and holes by light irradiation is applied to non-single crystal semiconductors including such amorphous semiconductors.
There is a need to improve the conversion efficiency by promoting crystallization in the semiconductor region to improve the collection efficiency, especially for long wavelength light. Furthermore, in photoelectric conversion devices with PIN junctions, the width of the depletion layer in the ■-type semiconductor is increased to 1μ or more, and the connection parts for integration are made of a high-resistance amorphous structure without crystallization. There is a need to prevent leakage from occurring through the semiconductor in this region by allowing the region to remain as it is.
「問題を解決しようとする手段」
本発明は、N型またはP型半導体層を作る前または後に
裏面電極側より非単結晶半導体に対し、400nm以下
の波長のパルス状の強光(パルス中10〜100n秒)
を照射して、■型半導体層またはこのI型半導体層とそ
れに近接した裏面側のNまたはP型半導体層とを水素ま
たはハロゲン元素を内部に保存しつつ結晶性を促しめる
ものである。``Means for Solving the Problem'' The present invention applies pulsed intense light (with a wavelength of 400 nm or less) to a non-single crystal semiconductor from the back electrode side before or after forming an N-type or P-type semiconductor layer. ~100ns)
By irradiating the 2-type semiconductor layer or this I-type semiconductor layer and the N or P-type semiconductor layer on the back side adjacent thereto, crystallinity can be promoted while preserving hydrogen or halogen elements inside.
結果として、珪素を主成分とする半導体にあっては、1
.3〜1.6eVとアモルファス半導体の1.7〜1.
8eVよりも狭いエネルギバンド巾とし得る。As a result, in semiconductors whose main component is silicon, 1
.. 3-1.6 eV and 1.7-1.
The energy band width may be narrower than 8 eV.
このため、長波長光の集収効率を向上せしめることが可
能となった。Therefore, it has become possible to improve the collection efficiency of long wavelength light.
特に本発明は、その光吸収が小さい400 nm以下例
えばKrFまたはXeC1を用いたエキシマレーザのパ
ルス状の強光を、内部の十分深い領域(光照射面と反対
側の裏面電極側)のみのI型半導体の結晶性を半導体を
形成させた後に裏面側より照射して促進させ、いわゆる
光アニールを行った。このため、光は半導体の光吸収係
数の比較的大きな400nm以下の波長を用いた。In particular, the present invention is capable of transmitting strong pulsed light from an excimer laser using KrF or After the semiconductor was formed, the crystallinity of the type semiconductor was promoted by irradiation from the back side, and so-called photo-annealing was performed. For this reason, a wavelength of 400 nm or less, which has a relatively large light absorption coefficient of the semiconductor, was used as the light.
本発明は、本発明人による特許層(特願昭59−181
097 半導体装置 昭和59年8月24日出願)を
さらに改良したものである。The present invention is based on the patent layer (Japanese Patent Application No. 59-181) by the inventor.
This is a further improvement of 097 Semiconductor Device (filed on August 24, 1980).
本発明は、この光アニールにより、同時に伴う電気伝導
度の増加が周辺部でのリークを許容してはならない。こ
のため集積化構造にあっては、連結部でのアイソレイシ
ョンの妨げになってはならない。このため本発明におい
ては、この光アニールを光電変換素子を構成する領域の
みに対して行った。In the present invention, the accompanying increase in electrical conductivity due to this photoannealing must not allow leakage at the periphery. Therefore, in an integrated structure, isolation at the connecting portion must not be hindered. Therefore, in the present invention, this optical annealing was performed only on the region constituting the photoelectric conversion element.
「作用」
その結果、レーザアニールにより得られる結晶化助長領
域は、各セル(素子)間のアイソレイション領域および
その外周辺に対しては何等行わないため、集積化光電変
換装置の製造に他の余分の工程を伴わずに完了させるこ
とができるという特長を有する。"Effect" As a result, the crystallization promoting region obtained by laser annealing does not affect the isolation region between each cell (element) or its outer periphery. It has the advantage of being able to be completed without any extra steps.
本発明の装置における素子の配置、大きさ、形状は設計
仕様によって決められる。しかし本発明の内容を簡単に
するため、以下の詳細な説明においては、第1の素子の
下側(基板側)の第1の電極と、その右隣りに配置した
第2の素子の第2の電極(半導体上即ち基板から離れた
裏面側)とを電気的に直列接続させた場合のパターンを
基として記す。The arrangement, size, and shape of elements in the device of the present invention are determined by design specifications. However, in order to simplify the content of the present invention, in the following detailed description, the first electrode on the lower side (substrate side) of the first element and the second electrode of the second element disposed on the right side thereof will be described. The pattern is based on the case where the electrodes (on the semiconductor, that is, on the back side away from the substrate) are electrically connected in series.
この規定された位置に例えばKrFまたはXeC1を用
いたエキシマレーザ、例えば波長248nmを照射させ
る。本発明は、基板が透光性のガラス上に半導体を形成
し、その上面の光照射側に対し、裏面側より400nm
以下のレーザ光アニールを行ったもので、製造工程を増
加させることなしに歩留りを従来の約60%より87%
にまで高めることができるという画期的な光電変換装置
の作製方法を提供することにある。This defined position is irradiated with an excimer laser using, for example, KrF or XeC1, for example, a wavelength of 248 nm. In the present invention, a semiconductor is formed on a transparent glass substrate, and a distance of 400 nm from the back surface side to the light irradiation side of the top surface.
The following laser beam annealing was performed, and the yield was increased from about 60% to 87% without increasing the manufacturing process.
The object of the present invention is to provide an innovative method for manufacturing a photoelectric conversion device that can increase the performance of the photoelectric conversion device.
以下に図面に従って本発明の詳細を示す。The details of the invention are shown below in accordance with the drawings.
「実施例1」 第1図は本発明の製造工程を示す縦断面図である。"Example 1" FIG. 1 is a longitudinal sectional view showing the manufacturing process of the present invention.
第1図(A)においては、絶縁表面を有する基板例えば
ガラス基板(1)であって、長さく図面では左右方向)
10cm、巾10cmを用いた。さらにこの上面に、
全面にわたって第1の導電膜(2)を透光性導電膜によ
り0.1〜0.5μの厚さに形成させた。In FIG. 1(A), a substrate having an insulating surface, such as a glass substrate (1), is shown (in the left-right direction in the drawing).
A size of 10 cm and a width of 10 cm was used. Furthermore, on this top surface,
A first conductive film (2) was formed over the entire surface using a transparent conductive film to a thickness of 0.1 to 0.5 μm.
この透光性導電膜(2)として弗素等のハロゲン元素が
添加された酸化スズを主成分とする透光性導電膜または
ITO(酸化スズ・インジューム)(500〜5000
人代表的には500〜1500人)をスパッタ法または
スプレー法により形成させた。This transparent conductive film (2) is a transparent conductive film whose main component is tin oxide to which a halogen element such as fluorine is added, or ITO (tin oxide indium) (500 to 5000
(typically 500 to 1,500 people) were formed by sputtering or spraying.
この後、この基板の上側より、YAGレーザ(波長1.
06μm(パルス巾80n秒)加工機(日本電気型))
により平均出力0.3〜舖(焦点距離40mm)を加え
、直径5mmφのレーザ光を集光し、スポット径20〜
70μφ代表的には40μφをマイクロコンピュータに
より制御して、上方よりレーザ光を照射し、その走査に
より、スクライブライン用の第1の開溝(13)を形成
させ、各素子領域(31) 、 (11)に第1の電極
(15)をレーザスクライブ(LSという)により作製
した。After this, a YAG laser (wavelength 1.
06μm (pulse width 80ns) processing machine (Nippon Denki type))
By adding an average output of 0.3 to 40 mm (focal length 40 mm), a laser beam with a diameter of 5 mmφ is focused, and a spot diameter of 20 to
A laser beam of 70 μφ, typically 40 μφ, is controlled by a microcomputer and irradiated with a laser beam from above, and by scanning, a first groove (13) for a scribe line is formed, and each element region (31), ( 11) A first electrode (15) was produced by laser scribing (referred to as LS).
LSにより形成された開溝(13)は、巾約50μ長さ
10cmであり、深さはそれぞれ第1の電極を構成させ
るために完全に切断分離した。The open grooves (13) formed by LS had a width of about 50 μm and a length of 10 cm, and the depths were completely cut and separated to form the first electrodes.
かくして第一1の素子(31)および第2の素子(11
)を構成する領域の巾は5〜40mm例えば10mmと
して形成させた。Thus, the first element (31) and the second element (11
) The width of the area constituting the area is 5 to 40 mm, for example 10 mm.
この後、この上面にプラズマCVD法、フォトCVD法
またはLPCV D法により、光照射により光起電力を
発生する非単結晶半導体即ちPIN接合、NIP接合、
またはPI接合またはNI接合を有し、水素またはハロ
ゲン元素が添加された非単結晶半導体層(3)を■型半
導体中の最低酸素濃度を5 XIO”cm−″以下とし
、かつその厚さを0.3〜3.0μ代表的には1.5μ
に形成させた。After that, a non-single crystal semiconductor, that is, a PIN junction, a NIP junction, which generates a photovoltaic force by light irradiation, is formed on the upper surface by plasma CVD, photoCVD, or LPCVD.
Alternatively, the non-single crystal semiconductor layer (3) having a PI junction or NI junction and doped with hydrogen or a halogen element has a minimum oxygen concentration of 5 XIO"cm-" or less in a ■-type semiconductor, and its thickness is 0.3-3.0μ typically 1.5μ
was formed.
その第1の代表例は光照射が基板側からの場合であるた
め、P型(SixC,、0< x < 1 )半導体(
約200人)−I型アモルファスシリコン半導体(約1
.5μ)−N型の微結晶 (約500人)を有する半導
体よりなる1つのPIN接合を有する非単結晶半導体(
3)を全面にわたって均一の膜厚で形成させた。The first typical example is when light is irradiated from the substrate side, so it is a P-type (SixC, 0<x<1) semiconductor (
Approximately 200 people) - Type I amorphous silicon semiconductor (approximately 1
.. 5μ) - a non-single-crystalline semiconductor (with one PIN junction) consisting of a semiconductor with N-type microcrystals (approximately 500 microcrystals)
3) was formed to have a uniform thickness over the entire surface.
第2の代表例はP型半導体−■型アモルファス半導体を
有する1つのPI接合を有する非単結晶半導体(3)を
全面にわたって形成させる。In the second representative example, a non-single crystal semiconductor (3) having one PI junction having a P-type semiconductor and a ■-type amorphous semiconductor is formed over the entire surface.
さらに本発明方法における400 nm以下、の波長の
紫外光を発光するエキシマレーザ光アニールの概要を示
す。Furthermore, an outline of excimer laser light annealing that emits ultraviolet light with a wavelength of 400 nm or less in the method of the present invention will be shown.
被照射半導体は第1図(A)に示す。PIN接合を構成
するN型半導体を形成する前(PI接合を形成後即ち第
2の代表例)または後(PIN接合を形成した後即ち第
1の代表例)の半導体を光アニール工程における対象物
として用いた。The semiconductor to be irradiated is shown in FIG. 1(A). A semiconductor before (after forming a PI junction, i.e., second representative example) or after forming an N-type semiconductor constituting a PIN junction (i.e., after forming a PIN junction, i.e., first representative example) is used as an object in a photo-annealing process. It was used as
この対象物を真空中または水素雰囲気中に保存し、ここ
に合成石英窓を通して外部よりパルス光を照射した。This object was stored in a vacuum or in a hydrogen atmosphere, and pulsed light was irradiated from the outside through a synthetic quartz window.
光源の照射光面積は120mm”としたエキシマパルス
レーザ光を用いた。特にこの巾は素子を構成する領域中
と同一とし、同一個所への照射は1回または10回以下
の繰り返しパルス光照射の操作としてその照射部を移動
し、素子を構成する領域のすべてを光アニールさせた。Excimer pulse laser light was used with the irradiation area of the light source being 120 mm. In particular, this width was the same as the area constituting the element, and the same area was irradiated once or repeatedly pulsed light was irradiated less than 10 times. As an operation, the irradiation part was moved to optically anneal all the regions that constitute the element.
ここではケスナック製エキシマレーザ発振器を用いた。Here, an excimer laser oscillator manufactured by Kesnack was used.
このレーザ光はレンズで集光せしめ、矩形を有し10m
m X 12mmの面積のパルス光(繰り返し周波数3
0Hz〜300Hz)を用いた。この照射幅は第1図の
素子領域(11) 、 (31)の幅と一致せしめた。This laser beam is focused by a lens, has a rectangular shape, and has a length of 10m.
Pulsed light with an area of m x 12 mm (repetition frequency 3
0Hz to 300Hz) was used. This irradiation width was made to match the width of the element regions (11) and (31) in FIG.
この照射光(25)を被照射面に一定速度で移動する基
体に照射させた。This irradiation light (25) was irradiated onto a substrate moving at a constant speed on the irradiation surface.
か(すると、非単結晶半導体中で1層の裏面電極側の一
部の厚さの0.1〜0.4μmの深さの領域の結晶化を
させることができた。この結晶化の事実は、この工程の
後レーザラマン分光測定を行うことにより判明した。加
えて、この本発明方法のアニールはパルス幅が10〜5
0n秒と短い光パルスアニールのため、結晶化の際、既
に含有している水素またはハロゲン元素を外部に脱気す
ることがほとんどない。加えて結晶性または秩序性を光
アニールにより促進するため、光劣化特性が小さくなり
、加えてPI間の1層中の空乏層の巾をアモルファス構
造のPIN接合における0、3μより1〜3μと伸ばす
ことができるという二重の特長を有していた。このため
1層の最適厚さをアモルファス半導体のみを1層で用°
いたときの0.5μmより結品性を有する半導体との複
合構造のため、0.5〜2.0μmにまで厚くさせるこ
とができ、短波長光はアモルファスシリコン半導体領域
(35−1) 、 (35’ −1)で吸収せしめ、ま
た長波長光は多結晶シリコン半導体領域(35−2)
、 (35’−2)で吸収させることにより広い波長に
わたって光電変換をさせることが可能となった。その結
果、光電変換装置としての電流を増加させ得る。(As a result, it was possible to crystallize a region with a depth of 0.1 to 0.4 μm in a part of the back electrode side of one layer in the non-single-crystal semiconductor.The fact of this crystallization was found by performing laser Raman spectroscopy after this step.In addition, the annealing of the method of the present invention has a pulse width of 10 to 5.
Because the light pulse annealing is as short as 0 nanoseconds, there is almost no possibility of degassing the hydrogen or halogen elements already contained during crystallization. In addition, since crystallinity or orderliness is promoted by photoannealing, photodegradation characteristics are reduced, and in addition, the width of the depletion layer in one layer between PIs is 1 to 3μ, compared to 0.3μ in an amorphous PIN junction. It had the double feature of being able to be stretched. For this reason, the optimum thickness of one layer is determined by using only amorphous semiconductor in one layer.
Because it has a composite structure with a semiconductor that has crystallization properties, it can be made thicker to 0.5 to 2.0 μm, and short wavelength light can be used in the amorphous silicon semiconductor region (35-1). 35'-1), and long wavelength light is absorbed by the polycrystalline silicon semiconductor region (35-2).
, (35'-2) makes it possible to perform photoelectric conversion over a wide range of wavelengths. As a result, the current as a photoelectric conversion device can be increased.
このレーザ光アニールは、第1図(C)において素子を
構成する(31)、(11)の領域である(35−2)
。This laser beam annealing is performed on the regions (35-2) (31) and (11) that constitute the device in FIG. 1(C).
.
(35’−2)に限られる。そして連結部(4)を構成
する領域は高抵抗型の半導体、特にアモルファス半導体
であり、(20)の下側の半導体(34)により電極(
39) 、 (39°)間のリークがないようにせしめ
た。(35'-2). The region constituting the connecting portion (4) is a high-resistance semiconductor, especially an amorphous semiconductor, and the semiconductor (34) below the (20) is connected to the electrode (
39) and (39°) to ensure that there is no leakage.
さらにこのレーザアニールは、素子の巾方向の両端部(
図面の前後方向の端部)より1〜2Il111内側とし
、両端部には至らせないようにした。結果として、アモ
ルファス半導体が素子を構成する領域(31) 、 (
11)が多結晶化した領域(35−2) 、 (35’
−2)の外周辺のすべてに残存させている。換言すれ
ば、素子を構成する領域の外周辺部は高抵抗度のアモル
ファス半導体で取り囲む構造とし、かくすることにより
、半導体(35−2) 、 (35’−2)の周辺部で
の上下電極間のリーク、即ち等価回路的にいうならば直
列抵抗の低下を防ぐことができた。Furthermore, this laser annealing is applied to both ends of the device in the width direction (
It was placed 1 to 2Il111 inward from the end in the front-rear direction of the drawing, and did not reach both ends. As a result, the region (31) where the amorphous semiconductor constitutes the element, (
11) is polycrystalline (35-2), (35'
-2) remains all around the outside. In other words, the outer periphery of the region constituting the element is surrounded by a high-resistance amorphous semiconductor, so that the upper and lower electrodes at the periphery of the semiconductors (35-2) and (35'-2) It was possible to prevent leakage between the two, that is, a decrease in series resistance in terms of an equivalent circuit.
さらに本発明における第1の例においては、このレーザ
アニールの後、第1図(B)に示されるごとく、第1の
開溝(13)の左方向側(第1の素子側)にわたって第
2の開溝(14)を第2のLSI程により形成させた。Furthermore, in the first example of the present invention, after this laser annealing, as shown in FIG. The open groove (14) was formed by the second LSI process.
この図面では第1および第2の開溝(13) 、 (1
4)の中心間を100μずらしている。In this drawing, the first and second open grooves (13), (1
4) are shifted by 100μ between the centers.
かくして第2の開溝(14)は第1の電極の側面(8)
を露出させた。The second open groove (14) thus forms a side surface (8) of the first electrode.
exposed.
また第2の例においては、PI接合が形成されているの
みのため、その上にN型半導体をプラズマCVD法によ
り形成し、PIN接合の半導体を形成させた。ひき続き
、前記した如く、開溝(14)を形成した。In the second example, since only a PI junction was formed, an N-type semiconductor was formed thereon by plasma CVD to form a PIN junction semiconductor. Subsequently, the open grooves (14) were formed as described above.
第1図において、さらにこの上面に第1図(C)に示さ
れるごとく、表面の第2の導電膜(5)を形成した。In FIG. 1, a second surface conductive film (5) was further formed on this upper surface as shown in FIG. 1(C).
さらにこの後、第3のLSにより切断分離をして複数の
第2の電極(39) 、 (39’)の形成用に第3の
開溝(20)を形成してアイソレイションした。Furthermore, after this, isolation was performed by cutting and separating using a third LS to form third open grooves (20) for forming a plurality of second electrodes (39) and (39').
この第2の導電膜(5)は金属と透光性導電酸化膜(C
TF)との多層膜を用いた。その厚さはそれぞれ300
〜1500人に形成させた。This second conductive film (5) consists of a metal and a transparent conductive oxide film (C
A multilayer film with TF) was used. The thickness of each is 300
~1500 people formed it.
このCTFとしてクロム−珪素化合物等の非酸化物導電
膜よりなる透光性導電膜を用いてもよい。As this CTF, a light-transmitting conductive film made of a non-oxide conductive film such as a chromium-silicon compound may be used.
これらは電子ビーム蒸着法またはスパッタ法、フォトC
VD法、フォト・プラズマCVD法を含むCVD゛ 法
を用い、半導体層を劣化させないため、250℃以下の
温度で形成させた。These are electron beam evaporation method, sputtering method, photo C
A CVD method including a VD method and a photo-plasma CVD method was used to form the semiconductor layer at a temperature of 250° C. or lower in order to prevent deterioration of the semiconductor layer.
か(して第1図(C)に示されるごと(、複数の素子(
31)、 (11)を連結部(4)で直列接続する光電
変換装置を作ることができた。(as shown in FIG. 1(C)), a plurality of elements (
31) and (11) were connected in series at the connecting part (4).
第1図(D)はさらに本発明を光電変換装置として完成
させんとしたものである。即ちパッシベイション膜とし
てプラズマ気相法またはフォト・プラズマ気相法により
窒化珪素膜(21)を500〜2000人の厚さに均一
に形成させ、各素子間のリーク電流の湿気等の吸着によ
る発生をさらに防いだ。FIG. 1(D) shows an attempt to further complete the present invention as a photoelectric conversion device. That is, as a passivation film, a silicon nitride film (21) is uniformly formed to a thickness of 500 to 2,000 layers by a plasma vapor phase method or a photo plasma vapor phase method, and the leakage current between each element is caused by adsorption of moisture, etc. This further prevented the outbreak.
第1図(D)におけるA−A’の縦断面図でのエネルギ
バンドダイヤグラムを第2図に示す。図面は光照射(1
0)面側をP型半導体(6)を有し、アモルファス半導
体(35−1)、多結晶半導体(35−2)を有する。FIG. 2 shows an energy band diagram in a longitudinal cross-sectional view taken along line AA' in FIG. 1(D). The drawing is irradiated with light (1
0) has a P-type semiconductor (6) on the surface side, and has an amorphous semiconductor (35-1) and a polycrystalline semiconductor (35-2).
このため、I型半導体はアモルファス半導体(7−1)
と多結晶半導体(マー2)とを有し、さらにそのうしろ
にN型半導体(8)を構成している。多結晶半導体(7
−2)の厚さは0.1〜0.4μであり、長波長光の吸
収に有効であった。Therefore, type I semiconductor is an amorphous semiconductor (7-1)
and a polycrystalline semiconductor (mer 2), and further constitutes an N-type semiconductor (8) behind it. Polycrystalline semiconductor (7
-2) had a thickness of 0.1 to 0.4μ and was effective in absorbing long wavelength light.
このN型半導体は光アニールの後にアモルファスまたは
微結晶構造で形成してもよい。かくすると工程数が増え
る。しかし光アニールによりこのN型半導体とI型半導
体中に局部的に拡散してしまうことを防ぐことができ歩
留まりが向上する。This N-type semiconductor may be formed into an amorphous or microcrystalline structure after photoannealing. This increases the number of steps. However, optical annealing can prevent local diffusion into the N-type semiconductor and I-type semiconductor, improving yield.
さらに外部引出し端子(24) 、 (24”)を周辺
部に設けた。Furthermore, external lead-out terminals (24) and (24'') were provided at the periphery.
斯(して照射光(10)に対し、この実施例のごとき基
板(10cmX10cm)において、各素子を巾101
III11×9211Imの短冊上に設け、さらに連結
部の巾150μm外部引出し電極部の巾4.311II
11、周辺部4mmによって、実質的に88mm X
92mm内に9段を有せしめた。In this way, for the irradiation light (10), on the substrate (10 cm x 10 cm) as in this example, each element was
III 11 x 9211Im strip, and the width of the connection part is 150μm, and the width of the external extraction electrode part is 4.311II
11. With 4mm peripheral area, it is practically 88mm
Nine stages were provided within 92 mm.
その結果、セグメントが12.2%(1,05cm”)
の変換効率を有する場合、パネルにて10.4%を9段
直列連結抵抗により有せしめることができた。As a result, the segment is 12.2% (1,05cm”)
When the conversion efficiency was 10.4%, the panel could have a conversion efficiency of 10.4% using 9 stages of series-connected resistors.
「効果」
本発明は■型半導体を形成した後の工程であるNまたは
P型半導体層の形成の前または後にレーザアニールを行
い、長波長光の集収効率を向上せしめ、ひいては変換効
率の向上をさせた。さらにその際、連結部、周辺部は初
期と同じアモルファス構造を保持せしめたため、ここで
の半導体の結晶化に伴う低抵抗化、さらに結果としての
リーク電流の増大を防ぐことができた。"Effects" The present invention performs laser annealing before or after forming an N- or P-type semiconductor layer, which is a step after forming a ■-type semiconductor, to improve the collection efficiency of long-wavelength light and, in turn, to improve the conversion efficiency. I let it happen. Furthermore, at this time, the connecting portion and the peripheral portion were allowed to maintain the same amorphous structure as in the initial stage, thereby making it possible to reduce the resistance caused by the crystallization of the semiconductor here and also to prevent the resulting increase in leakage current.
またこの入射光とは反対側の内部の半導体のみを多結晶
化することにより、そこでの高い電流密度を有しつつも
これまでアモルファス光電変換装置の特長である集積化
のしやすさに対しまった(その特徴を失わずに成就でき
た。In addition, by polycrystalizing only the internal semiconductor on the side opposite to this incident light, it is possible to achieve a high current density there, but it is not easy to integrate, which is a feature of amorphous photoelectric conversion devices. (It was achieved without losing its characteristics.
第1図は本発明の光電変換装置の製造工程を示す縦断面
図である。
第2図は本発明のA−A’ の縦断面出に対応したエネ
ルギバンド幅を示す。
1・・・・・透光性基板
2・・・・・透光性導電膜
3・・・・・非単結晶半導体
31.11 ・・・光電変換素子
4・・・・・連結部
35−1.35’−トアモルファス半導体35−2.3
5’−2・多結晶半導体
25・・・・・エキシマレーザ光
10・・・・・照射光
6・・・・・P型半導体
7−1 ・・・・アモルファスI型半導体7−2 ・
・・・多結晶I型半導体
7・・・・・I型半導体
8・・・・・N型半導体
5・・・・・裏面電極よう導体FIG. 1 is a longitudinal sectional view showing the manufacturing process of the photoelectric conversion device of the present invention. FIG. 2 shows the energy band width corresponding to the longitudinal section taken along the line AA' of the present invention. 1...Transparent substrate 2...Transparent conductive film 3...Non-single crystal semiconductor 31.11...Photoelectric conversion element 4...Connection part 35- 1.35'-tor amorphous semiconductor 35-2.3
5'-2 Polycrystalline semiconductor 25... Excimer laser light 10... Irradiation light 6... P-type semiconductor 7-1... Amorphous I-type semiconductor 7-2.
... Polycrystalline I-type semiconductor 7 ... I-type semiconductor 8 ... N-type semiconductor 5 ... Back electrode conductor
Claims (1)
上に密接してPIN接合を有する水素またはハロゲン元
素が添加された非単結晶半導体と、該半導体上に第2の
電極とを有する光電変換素子を複数個直列に連結部にて
連結して設けた半導体装置において、前記光電変換素子
を構成する領域の裏面側の半導体の結晶化は連結部を構
成する領域の裏面側の前記半導体に比べて助長して設け
られたことを特徴とする半導体装置。 2、特許請求の範囲第1項において、水素またはハロゲ
ン元素を有するPIN接合を有する非単結晶半導体の光
電変換素子を構成する領域のI型半導体は、水素または
ハロゲン元素が添加された多結晶構成を有する低抵抗型
半導体を光照射面と反対側の裏面側に設け、さらにかか
る裏面における連結部を構成する領域のI型半導体はア
モルファス構造を有する高抵抗型半導体よりなることを
特徴とする半導体装置。 3、特許請求の範囲第1項において、光電変換素子を構
成する領域の表面側の半導体はアモルファス構造を有す
ることを特徴とする半導体装置。[Claims] 1. A first electrode on a substrate having an insulating surface, a non-single crystal semiconductor doped with hydrogen or a halogen element having a PIN junction in close contact with the electrode, and a non-single crystal semiconductor on the semiconductor. In a semiconductor device in which a plurality of photoelectric conversion elements having a second electrode and a second electrode are connected in series at a connecting part, crystallization of the semiconductor on the back side of the region constituting the photoelectric conversion element constitutes the connecting part. 1. A semiconductor device, characterized in that the semiconductor device is provided with a larger area than the semiconductor on the back side of the region. 2. In claim 1, the I-type semiconductor in the region constituting the photoelectric conversion element of a non-single-crystal semiconductor having a PIN junction containing hydrogen or a halogen element has a polycrystalline structure doped with hydrogen or a halogen element. A semiconductor characterized in that a low-resistance type semiconductor having a structure is provided on the back side opposite to the light irradiation surface, and an I-type semiconductor in a region constituting a connecting portion on the back side is made of a high-resistance type semiconductor having an amorphous structure. Device. 3. A semiconductor device according to claim 1, wherein the semiconductor on the surface side of the region constituting the photoelectric conversion element has an amorphous structure.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP61281045A JPS63133578A (en) | 1986-11-25 | 1986-11-25 | Semiconductor device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP61281045A JPS63133578A (en) | 1986-11-25 | 1986-11-25 | Semiconductor device |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS63133578A true JPS63133578A (en) | 1988-06-06 |
Family
ID=17633530
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP61281045A Pending JPS63133578A (en) | 1986-11-25 | 1986-11-25 | Semiconductor device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS63133578A (en) |
Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS6196773A (en) * | 1984-10-17 | 1986-05-15 | Agency Of Ind Science & Technol | Manufacture of semiconductor device |
JPS61231772A (en) * | 1985-04-05 | 1986-10-16 | Semiconductor Energy Lab Co Ltd | Manufacture of semiconductor device |
-
1986
- 1986-11-25 JP JP61281045A patent/JPS63133578A/en active Pending
Patent Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS6196773A (en) * | 1984-10-17 | 1986-05-15 | Agency Of Ind Science & Technol | Manufacture of semiconductor device |
JPS61231772A (en) * | 1985-04-05 | 1986-10-16 | Semiconductor Energy Lab Co Ltd | Manufacture of semiconductor device |
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