JPS63132454A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To make easily contact holes minute and flat, by growing single crystal Si only on amorphous Si in the contact hole by solid phase epitaxy, eliminating selectively excess amorphous silicon, and burying it in single crystal Si. CONSTITUTION:After a gate electrode 20, a gate oxide film 21, an N<+> type diffusion layer 22, an element isolation region 23, etc., are formed on a P-type Si substrate 100, an interlayer insulating film 25 is formed. After the film 25 is made flat, contact holes 27 which connect the layer 22 and the layer 26 are formed in the following manner; after amorphous Si 29 is deposited on the whole surface of holes on which the film 25 and the Si surface are exposed, a heat treatment at 600 deg.C is performed in an N2 atmosphere, and single crystal Si is grown up to the upper surface of the hole 27 by solid phase epitaxy. Next, excess amorphous Si is selectively eliminated by etching.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a method for manufacturing a semiconductor device, and in particular, to a method for manufacturing a semiconductor device, and in particular to a method for manufacturing a semiconductor device.
The present invention relates to a method for manufacturing a semiconductor device having a connection region (contact hole, through hole, etc.) which is a component of multilayer wiring for LSI suitable for high performance.

[Conventional technology]

LSI has achieved high integration at a rate of four times every three years, centered on fine processing technology. Furthermore, in order to achieve large-scale high integration, high-density wiring technology is required to miniaturize and multilayer multilayer wiring. The main technologies for realizing the above-mentioned high-density wiring technology include (1) planarization of the wiring structure, (2) reduction of the connection area (contact hole, through hole), and (2) application of migration-resistant and corrosion-resistant wiring materials. The present invention aims to provide a technique effective for the above-mentioned (1) and (2). FIG. 2 illustrates the problems inherent in conventional multilayer wiring, exemplified by, for example, MoS transistors.

Wiring layers 1-a, 1-b and interlayer insulating films 2-a, 2-b
are each sputtering method.

CV D (Chsmical Vapor Depo
It is formed by the ``situation'' method. All of these thin film deposition methods reflect the shape of the underlying substrate. For example, the wiring layer 1-a, 1-b, the layer interlayer 1Ili1' layer 2-a, 2-b (7) shape tear on the selective oxide film 3, gate electrode 4, or contact hole 5, through hole 6. In places where steps overlap, height differences are accumulated as they are (for example, ■ in the figure). This causes problems such as poor microfabrication and poor wiring reliability. The problem with the former is that the photoresist l-film thickness for the processing mask is Sj
Since it differs at each location within the wafer, the exposure and development characteristics in the lithography process become film thickness dependent, resulting in a decrease in one-dimensional performance. Alternatively, during dry etching, the thickness of the wiring layer 1 at the shoulders and gaps of the stepped portion is effectively thicker than that at the flat portion, so that etching remains are likely to occur, causing wiring short circuits. The latter decrease in reliability is due to the fact that in the wiring layer 1, the thickness of the deposited film at the bottom of the step becomes extremely thin, resulting in disconnection of the wiring, and in the absolute layer 2, the quality of the deposited film at the shoulder and bottom of the step, This is because the reduction in film thickness causes short circuits between wiring layers. As devices become smaller and more highly integrated, the above problems become more prominent.

This is because parasitic effects such as wiring resistance and capacitance become a problem. That is, although the planar dimension is reduced to 1/k by the scaling law (proportional reduction agent), it is difficult to reduce the vertical structure such as the thickness of wiring and interlayer insulating film. Vertical structure is also 1
This is because if the wiring resistance and wiring delay are reduced to /J%, the wiring resistance and wiring delay will double, causing deterioration of the characteristics and reliability of the LSI. As described above, since it is impossible to reduce the vertical dimension of the wiring layer, the unevenness of the device surface inevitably becomes severe. That is, since the aspect ratio (for example, the aspect ratio of the recess is expressed as a height of 7 widths) increases, the problem shown in FIG. 2 becomes more and more noticeable. For this reason, various methods of reducing the step difference, that is, flattening methods, are used depending on the required steps. Categorized by process: wiring layer.

Interlayer insulation layer, connection hole (contact hole, through hole)
It is broadly divided into formation. Examples of planarization of the wiring layer include an anodic oxidation method and a lift-off method. For the interlayer insulating film layer, PSG (Phospho 5ilicateG
lass), BPSG (Boro Phospo
5iOz using a coating film of 5iLinate Glass), an etch-back method using the coating film and etching, or a bias sputtering method.
There are a film planarization method, a planarization method using an organic insulating film, etc.

Regarding connection holes, their formation is one of the major factors that restricts the increase in layout density, and there is a tendency to further reduce the size of the connection holes in the future. As miniaturization progresses, a decrease in wiring coverage (step coverage) in contact holes has become a problem. That is, in the commonly used AQ sputtering method, the side walls of the connection hole are adhered to each other by A,
This is a phenomenon in which the AQ film at the bottom becomes extremely thin due to the shadow of the two particles. Conventionally, in order to prevent this, a method has been used in which the shape of the hole is tapered to give it an inclination. However, it is disadvantageous to the reduction of the connection hole due to miniaturization, and a vertical shape is essential.

For this reason, step coverage of wiring layers is becoming increasingly difficult. Furthermore, in order to flatten an uneven underlying surface, there is a general tendency to increase the thickness of the interlayer insulating film;
With the addition of miniaturization, the aspect ratio of connection holes tends to increase significantly. To solve this problem, various methods have been used to form connection holes. Among these, a method of embedding a metal material or the like into a connection hole with a larger aspect ratio has been attempted. By adopting this method, it is possible to improve the step coverage of fine contact holes or to flatten the contact holes. For example, a first-order example is known. Figure 3 (
A) is a method of filling the contact hole with poly-Si or the like using an etch-back method. Poly 5ill is deposited on the contact hole 10 and the interlayer insulating film 2 by the CVD method or the like. Then resist 1
After spin coating an organic material such as No. 2 on the uneven surface to make the surface appear flat, the entire surface is etched (etched back) under the same etching speed conditions for poly 5ill and resist 12. ), poly 5ill is buried only in the contact hole 1o. FIG. 4 shows a method in which the contact hole is filled with Si by a selective epitaxial growth method. A connection hole 10 is formed as shown in (a), and S
i H4t 5iHz 100 using C1z as source gas
At around 0° C., Si is selectively grown in a vapor phase only in the connection hole 10. However, the method shown in Fig. 3 has a complicated process, the range of the same etching speed condition is narrow, and non-uniform etching is likely to occur, and as shown in Fig. 3(d), the buried height of the contact hole is It tends to become unbalanced. For this reason, the processing accuracy of the wiring layer in the next step is reduced. The fourth method (@) must be compatible with the LSI process, and because it grows Si at high temperatures, it has an adverse effect on shallow underlying junctions.

Others: AQ bias sputtering method, tungsten selection C
There are VD methods and metal CVD methods, but each has problems in reliability, film thickness, uniformity, and film quality.

[Problem that the invention seeks to solve]

The above conventional technology does not consider the uniformity of the buried layer of the contact hole, the compatibility with the process (heat treatment temperature), or the ease of the process, and the flatness of the wiring structure to achieve high-density wiring is not considered. ification.

There was a problem in reducing the connection area.

The purpose of the present invention is to achieve high-density wiring for LSI,
It is an object of the present invention to provide a method for manufacturing a semiconductor device having a connection region that eliminates the problems of the prior art described above.

(Means for solving problems) The above purpose is to deposit amorphous [Si] on a Si substrate.

Then, heating is performed in a furnace to form single crystal Si. This is achieved by selectively filling the connection region with single crystal Si using a so-called in-phase epitaxial growth method.

[Effect]

In the present invention, amorphous Si is deposited on the contact hole surface where the interlayer insulating film and the Si surface are exposed, and is heated in a furnace at 500 to 600°C, so that only the amorphous Si in the contact hole becomes solid. Single crystal Si is grown by epitaxial growth, excess amorphous Si is selectively removed, and the inside of the contact hole is filled with single crystal Si.
The feature is that it is embedded with i. This allows for a buried layer with good uniformity, consistency with the process, and easy miniaturization and flattening of connection holes.

〔Example〕

Hereinafter, the present invention will be explained in detail using examples.

FIG. 1 shows an example in which the present invention is applied to a typical N-type MO8h transistor. In the figure (a), a (100) P-type Si substrate 100 has a gate electrode 20 having a two-layer structure of PolySi and tungsten silicide. Gate oxide film 2
1. Consisting of source and drain N+ type scattering layers 22 and 23
2 is an oxide film for element isolation, and 24 is a diffusion layer for a channel stopper.

These diffusion layers, gate electrodes, and element isolations were formed by diffusion, CVD, and photolithography techniques in a normal LSI manufacturing process. After that, the wiring process begins. First, an interlayer insulating film 25 is formed.

In the interlayer insulation film 25, S i (OCzH3) was used as the source. 5iOz by low pressure CVD and BPSG (Boro Phospo 5ilica) for planarization.
It is a glass film.

BPSG film is SiH40oz +PHs +BzHe
The interlayer insulating film 25 was deposited using a gas system and reflowed to planarize it. Thereafter, a connection hole 27 (contact hole) connecting the source/drain 22 of the N0 type diffusion layer and the wiring layer 26 is formed by normal photolithography. Next, single-crystal Si is formed in the connection hole 27, the details of which are described in the first section.
It is shown in (b) in the figure. The figure shows connection hole 27 for simplicity.
Only a portion is shown. First, the single crystal surface 28, which will become a seed region for crystal growth, is cleaned. The cleaning method was heat treatment in an ultra-high vacuum. In the same vacuum, amorphous 5i29 was deposited on the entire surface by electron beam evaporation, and low-temperature heat treatment (350° C.) was performed to control the amorphous nature of the deposited Si. After that, heat treatment was performed at 600℃ in N2 atmosphere to form a single crystal 5i3.
Grow 0. That is, the growth of a single crystal to form single crystal Si by in-phase epitaxial growth is
However, the growth of single crystal Si can be easily stopped at the upper surface of the connection hole 27 by controlling the heat treatment time. Thereafter, it is lightly etched with an HF-based etching solution to remove excess amorphous Si. Amorphous Si and single crystal Si can be selectively etched easily with an HF-based etching solution. In order to make ohmic contact with the wiring layer 26, the single-crystal Si in the contact hole 27 is deposited with amorphous Si and then ion-implanted with phosphorus at 600° C. uniformly in the film thickness direction. The single crystal Si is grown by heat treatment and is formed into an N-type.Since the contact hole 27 is filled with the single crystal 5i30 by the method described above, the wiring layer 26 to be formed next is There is no need to consider step coverage for the contact hole 27, and the contact hole 27 is flattened on the same surface as the interlayer insulating film 25. Furthermore, the thickness of the interlayer insulating film 25 is uniform, and the contact hole 27 As long as the depth of the single crystal S
It is easy to control the growth of i, and the contact hole is uniformly planarized over the entire surface.

Thereafter, the aluminum wiring layer 26 is
was formed by a sputtering method, and the pattern accuracy was checked by ordinary photolithography.

Further, an interlayer insulating film 31 between the wiring layers was formed, connection holes between the wiring layers were formed by photolithography, and a wiring layer 32 was further formed.

According to the first embodiment of the present invention, single-crystal Si can be filled into the connection hole at a low temperature without adversely affecting the underlying shallow bonding layer. Moreover, since the contact hole is filled with single-crystal Si, there is no need to consider the step coverage of the wiring layer, making it easy to reduce the size of the contact hole. Furthermore, since the connection hole and the interlayer insulating film are flattened on the same surface, photolithography of the wiring layer in the next step is facilitated.

〔Effect of the invention〕

According to the present invention, since it is possible to deposit amorphous Si and fill the contact hole with single crystal Si at a low temperature by furnace heating, that is, by solid phase epitaxial growth, it is possible to improve the compatibility with the process, especially with respect to heat treatment. In other words, the negative effect on the formation of shallow junctions is reduced. Further, since a uniform buried layer in the connection hole can be easily obtained, the pattern accuracy of the wiring layer in the next step is improved. Further, complicated steps such as constant speed etching are not required, simplifying the process.

By obtaining the above effects, the connection area can be easily reduced, and high-density wiring for LSI can be achieved.

[Brief explanation of the drawing]

FIG. 1 shows an N-type MOS for explaining one embodiment of the present invention.
A cross-sectional view of a transistor, FIG. 2 shows a MoS transistor 100...Si substrate, 20...gate electrode, 21...gate oxide film, 2
2... Source/drain, 23... Selective oxide film, 2
5... Interlayer insulating film, 26... Wiring layer. 27... Connection hole, 29... Amorphous S1.30... Single crystal x a

Claims (1)

[Claims] 1. Elements such as transistors with N-type and P-type impurity layers formed in a semiconductor substrate are formed, and a plurality of wiring layers on the semiconductor substrate and a plurality of interconnection layers electrically connected to the element region of the semiconductor substrate are formed. In a method for manufacturing a semiconductor device comprising a connection hole and an interlayer insulating layer in which the connection hole is formed and electrically insulates the element region of the semiconductor substrate, the wiring layer, and the wiring layer, the connection hole is formed simply by solid phase growth. A method for manufacturing a semiconductor device characterized by selective embedding with crystalline silicon.