JPS63132446A - Manufacture of semiconductor - Google Patents

Manufacture of semiconductor

Info

Publication number
JPS63132446A
JPS63132446A JP25898086A JP25898086A JPS63132446A JP S63132446 A JPS63132446 A JP S63132446A JP 25898086 A JP25898086 A JP 25898086A JP 25898086 A JP25898086 A JP 25898086A JP S63132446 A JPS63132446 A JP S63132446A
Authority
JP
Japan
Prior art keywords
oxide film
mask
semiconductor substrate
groove
etching
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP25898086A
Other languages
Japanese (ja)
Other versions
JPH0587142B2 (en
Inventor
Tatsuya Ishii
達也 石井
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP25898086A priority Critical patent/JPS63132446A/en
Priority to DE19873736531 priority patent/DE3736531A1/en
Priority to US07/113,744 priority patent/US4772569A/en
Publication of JPS63132446A publication Critical patent/JPS63132446A/en
Publication of JPH0587142B2 publication Critical patent/JPH0587142B2/ja
Granted legal-status Critical Current

Links

Landscapes

  • Local Oxidation Of Silicon (AREA)
  • Drying Of Semiconductors (AREA)
  • Element Separation (AREA)

Abstract

PURPOSE:To improve a patterning precision by a method wherein, after a groove is dug on a semiconductor substrate, oxide masks for the surface other than the grooved region and a selective oxide film to be used for isolation on the sidewall surface of the groove are simultaneously patterned. CONSTITUTION:An oxide mask 2 is formed on the whole surface of a semiconductor substrate 1 and thereafter, an Si oxide film 5 is formed and this is subjected to deep groove etching. Then, after an Si nitride film 2 is formed on the whole surface, an Si oxide film 7 is formed on the whole surface and this is etched. Subsequently, the oxide mask 2 is removed to perform an entire surface etching, the whole surface of the Si oxide film 3 is etched and the oxide mask 2 only on the bottom surface of a groove is removed. Subsequently, the Si nitride film 2 is patterned simultaneously with the removal via a photoengraving process, wherein a multilayer resist is used, and an isolation of the surface other the grooved region on the substrate and an isolation oxide film on the sidewall surface of the groove are formed.

Description

【発明の詳細な説明】 (産業上の利用分野〕 この発明は、半導体基板に溝堀り領域を備えた3次元半
導体装置、特に、その素子量分#I膜の製造方法に関す
るものである。
DETAILED DESCRIPTION OF THE INVENTION (Industrial Application Field) The present invention relates to a three-dimensional semiconductor device having a grooved region in a semiconductor substrate, and particularly to a method for manufacturing a #I film corresponding to the number of elements thereof.

(従来の技術〕 ′!t! 9図ないし第16図に、半導体基板に溝堀り
の領域を備えた3次元半導体装置における従来のt導体
基板トの溝堀り領域以外の表面、及び溝の側壁面、底面
の素子間分離酸化膜の形成方法の一例の各工程シーケン
スを示す要部破断断面図である。
(Prior art) '!t! Figures 9 to 16 show the surface of a conventional t-conductor substrate other than the grooved area in a three-dimensional semiconductor device having a grooved area on the semiconductor substrate, and the groove. FIG. 3 is a fragmentary cross-sectional view of a main part showing a process sequence of an example of a method for forming an inter-element isolation oxide film on a side wall surface and a bottom surface of the semiconductor device.

(構成要素) 第9図において、1は弔結晶シリコン等の゛i′、導体
基板、2は、シリコン窒化11!2等の酸化マスク祠料
、3は、シリコン窒化膜2川のシリコン酸化膜等の′F
敷き材料、次工程の第10図における4は、シリコン酸
化膜等の素子間分離酸化膜、つぎに第1!〜15図にお
ける5は、シリコン基板lの溝堀りエツチングの際に用
いられるシリコン酸化膜等のエッチグングマスク材料、
第13]メ1における6は、酸化マスク材料2をパター
ニングする際に用いるレジスト等のエツチングマスク材
$4、次工程第14図における7は、゛ト導体」^べ1
に掘られた溝の底面を分離酸化する際の酸化マスク材料
2のパターニングに用いられるシリコン酸化膜等のエツ
チングマスク材料である。
(Components) In Fig. 9, 1 is a conductive substrate made of crystalline silicon, 2 is an oxide mask such as silicon nitride 11!2, 3 is a silicon oxide film of silicon nitride film 2, etc. 'F of etc.
4 in FIG. 10 of the next process is an inter-element isolation oxide film such as a silicon oxide film, and then the 1st! 5 in Fig. 15 is an etching mask material such as a silicon oxide film used in trench etching of the silicon substrate l;
13] 6 in the first step is an etching mask material such as a resist used when patterning the oxide mask material 2, and 7 in the next step in FIG. 14 is a conductor.
This is an etching mask material such as a silicon oxide film used for patterning the oxidation mask material 2 when separating and oxidizing the bottom surface of a groove dug in the trench.

(従来の製造方法) 次に、従来の製造方法について説明する。(Conventional manufacturing method) Next, a conventional manufacturing method will be explained.

第8図は、後述するこの発明による最終二[程における
要部断面図で、最終[l的は、この図に示すように゛l
′−導体J^板1上の溝堀り領域以外の表面ならびに溝
の側壁面及び底面に素子間分離酸化膜4を形成すること
にある。
FIG. 8 is a cross-sectional view of the main part in the final second step according to the present invention, which will be described later.
The object is to form an inter-element isolation oxide film 4 on the surface of the conductor J^ board 1 other than the grooved area, and on the sidewalls and bottom surfaces of the groove.

まず、第9図にンバずように、酸化マスク材料2を半導
体基板1」二の全表面に成1反した後、半導体基板1上
の溝堀り領域以外の素子間分離領域を、写真製版工程を
経て酸化マスク2を、パターニングし、4に示すように
分離酸化した状態が第10図である。次に、半導体基板
1の溝堀りエツチングの際に用いるエツチング材料5を
成膜し、写真製版工程を経てパターニングした後、溝堀
りエツチングした状態が第11図、続いて半導体」^叛
1である単結晶シリコンを熱酸化した後、全人面に酸化
マスク2となるシリコン窒化膜を成膜した状態が第12
図、続いて、この酸化マスク2となるシリコン多層レジ
ストを用いたが真製版工程を経てパターニングした状態
か第13図で、この図では、まだ第1層[」のレジスト
6が除去されていない状態を示している。すなわち、こ
こでは、゛h導体基板1表面に掘られた溝の側壁分離さ
れる領域のみの酸化マスク2を除去している。
First, as shown in FIG. 9, after applying a layer of oxide mask material 2 to the entire surface of the semiconductor substrate 1'', the isolation regions other than the grooved regions on the semiconductor substrate 1 are formed by photolithography. FIG. 10 shows the state in which the oxidation mask 2 is patterned through the process and separated and oxidized as shown in 4. Next, an etching material 5 to be used in trench etching of the semiconductor substrate 1 is formed, and after patterning through a photolithography process, the state of the trench trench etching is shown in Figure 11. After thermally oxidizing the single-crystal silicon, a silicon nitride film, which becomes the oxidation mask 2, is formed on the entire human face.
Next, the silicon multilayer resist that becomes the oxidation mask 2 was used, but it was patterned through a true plate making process. Indicates the condition. That is, here, the oxidation mask 2 is removed only in the region where the sidewalls of the grooves dug in the surface of the conductor substrate 1 are to be separated.

次にレジスト6を除去し、全面にシリコン酸化1漠7を
f&、yAシた状態が第14図、続いて、このシリコン
酸化11Q 7を反応性イオンエッチ等の異方性エツチ
ングによりエツチングした状態が第15図であり、溝の
側壁面のみのシリコン酸化膜7が−F面方向からのII
s! J’Jか厚いため、エツチングされずに枠となっ
て残存している。続いて、酸化マスク2の全面エツチン
グ、シリコン酸化1tQ 7の全面エツチングを経た状
態が第16図で、ここでは、溝の底面の酸化マスク2の
みを除去している。すなわち、半導体基板上1の溝掘領
域以外の表面は、溝堀りエツチングのマスク材料である
シリコン酸化膜5、溝の側壁面は異方性エツチングによ
り形成されたシリコン酸化膜7の枠によってマスクされ
、溝の底面の酸化マスク2のみが除去されている。ここ
までの工程で、溝の側壁面の酸化マスクがパターニング
され、続いて溝の底面の酸化マスク2が除去されたわけ
である。次に分離酸化した状態が第8図で、これで素f
間分層の工程は完rする。
Next, the resist 6 is removed, and silicon oxide 11Q 7 is etched on the entire surface, as shown in Figure 14. This silicon oxide 11Q 7 is then etched by anisotropic etching such as reactive ion etching. is shown in FIG. 15, and the silicon oxide film 7 only on the side wall surface of the trench is viewed from the -F plane direction II.
s! Because J'J is thick, it is not etched and remains as a frame. Subsequently, FIG. 16 shows the state after the entire surface etching of the oxide mask 2 and the entire surface etching of the silicon oxide 1tQ7, in which only the oxide mask 2 at the bottom of the groove is removed. That is, the surface of the semiconductor substrate 1 other than the grooved region is masked by a silicon oxide film 5 which is a mask material for trench etching, and the side wall surface of the trench is masked by a frame of a silicon oxide film 7 formed by anisotropic etching. Only the oxide mask 2 at the bottom of the groove is removed. In the steps up to this point, the oxide mask on the sidewalls of the trench was patterned, and then the oxide mask 2 on the bottom of the trench was removed. Next, the separated and oxidized state is shown in Figure 8.
The interlayer process is completed.

以上の工程を筒tp−に要約すると、当初、半導体基板
1の溝堀り領域以外の表面の分a酸化膜4を形成し、続
いて溝を掘った後、全人面を酸化マスク2で覆い、溝の
側壁面の酸化マスクをパターニング、続いて溝の底面の
酸化マスク2を除去し、最後に溝の側壁面を底面との分
離領域を同時に酸化する工程シーケンスであると要約す
ることができる。
To summarize the above steps in a cylindrical manner, first, an oxide film 4 is formed on the surface of the semiconductor substrate 1 other than the grooved area, and then, after digging a groove, the entire surface is covered with an oxide mask 2. The process sequence can be summarized as follows: covering, patterning the oxide mask on the sidewalls of the trench, then removing the oxide mask 2 on the bottom of the trench, and finally oxidizing the region separating the sidewalls of the trench from the bottom at the same time. can.

(発明か解決しようとする問題点) しかしながら、以1−のような従来の製造方法にあって
は、半導体基板I Fの溝堀り領域以外の表面の分離酸
化と、溝の側壁面の分1l11酸化とを独存した工程で
行なうため、それぞれのパターニングマスクが必要とな
り、両者のセルフアライメントがとわない。また、パタ
ーンレイアウト上、マスクアライメントのマージンを取
らなければならず、さらに、溝堀り工程でマスクずれか
生じ易く、溝堀り領域以外の表面の分S酸化膜領域と溝
堀りf域とかrrなることがあれば、半導体基板1の斜
めエツチングが生じ第15図に示したシリコン酸化膜7
の枠が残(fせずに、溝の側壁面の酸化マスク2か除去
されるii)能性がある等の問題点があった。
(Problem to be Solved by the Invention) However, in the conventional manufacturing method as described in 1- below, isolation oxidation of the surface of the semiconductor substrate IF other than the grooved region and separation of the sidewall surface of the groove are required. Since 1l11 oxidation and oxidation are performed in separate steps, respective patterning masks are required, and self-alignment of both is difficult. In addition, a margin for mask alignment must be taken in terms of pattern layout, and furthermore, mask misalignment is likely to occur during the trenching process, and the S oxide film region and the trench f region on the surface other than the trenching region. If rr occurs, diagonal etching of the semiconductor substrate 1 will occur and the silicon oxide film 7 shown in FIG.
There were problems such as the possibility that the oxidized mask 2 on the side wall surface of the trench could be removed without leaving a frame (f).

この発明は、L記のような従来例の製造方法の問題を解
消するためになされたもので、半導体基板4ユの溝堀り
領域以外の表面の分離酸化領域と、溝の側壁面の分離酸
化領域のセルフアライメントがとれ、かつ半導体基板上
の溝堀り領域以外の表面の分離酸化膜領域と、溝堀り領
域との重なりによるTMの側壁面における分離酸化の際
の酸化マスクのパターニング不良を防止できる゛ト導体
製造方法の提供を目的としている。
This invention was made in order to solve the problems of the conventional manufacturing method as described in L.The present invention was made in order to solve the problems of the conventional manufacturing method as described in L. Poor patterning of the oxide mask during isolation oxidation on the sidewall surface of the TM due to self-alignment of the oxidized region and overlap between the isolation oxide film region on the surface other than the grooved region on the semiconductor substrate and the grooved region. The purpose of the present invention is to provide a method for manufacturing a conductor that can prevent this.

〔問題点を解決するための手段〕[Means for solving problems]

このため、この発明に係る゛h導体製造方法においては
、半導体JJi&、)―に溝を掘った後、半導体基板ト
の溝堀り領域以外の表面の分離酸化膜ならびに溝の側壁
面の分B酸化膜、双方の酸化マスクを1桟のパターニン
グマスクを用いて、同時にパターニングする−「程方法
を採用することにより、11η記[1的を達成しようと
するものである。
For this reason, in the conductor manufacturing method according to the present invention, after trenches are dug in the semiconductor JJi The oxide film and both oxide masks are patterned simultaneously using a single patterning mask.By adopting the method, we aim to achieve goal 11.

〔作用〕[Effect]

以上のような製造方法により、゛V導体1.(板」−の
溝掘り領域以外の表面ならびに満の(lu11壁面の酸
化マスクを同時にパターニングするようにしたため、パ
ターンレイアウト上のマスクアライメントのマージンを
とる必要がなくなり、′i導体装置の小形化、微細化が
容易になる。
By the above manufacturing method, "V conductor 1. Since the oxidation mask on the surface other than the grooved area of the (plate) and the full (lu11 wall surface) is patterned at the same time, it is no longer necessary to take a margin for mask alignment on the pattern layout, which reduces the size of the i-conductor device. Miniaturization becomes easier.

また、半導体基板に溝を掘った後、基板表面の分離酸化
11Qを形成するようにしたため、溝堀り領域と基板表
面との分離領域の市なりによる基板の斜めエッチを生ず
ることがなくなり、満の側壁面の酸化マスクのパターニ
ング不良か防止される。
In addition, since the isolation oxide 11Q is formed on the substrate surface after trenching the semiconductor substrate, diagonal etching of the substrate due to the separation region between the trenching region and the substrate surface will not occur, and the substrate will not be completely etched. This prevents defective patterning of the oxidation mask on the sidewall surface.

さらに、゛r−惇体基体基板溝堀り領域以外の表面の分
離酸化ならびにγlηの側壁面の分離酸化の酸化マスク
を1枚のパターニングマスクを用いてパターニングする
ことにより、従来方法より製造工程か短縮される。
Furthermore, by patterning the oxidation mask for the isolation oxidation of the surface other than the grooved area of the ゛r-body substrate substrate and the isolation oxidation of the sidewall surface of γlη using a single patterning mask, the manufacturing process is simpler than the conventional method. be shortened.

(実施例) 以−トに、この発明を実施例に基づいて説明する。(Example) The present invention will now be explained based on examples.

第1図ないし、第8図は、この発明を用いたt導体製造
方法の芥4二稈シーケンスの一実施例を示−4−要部破
断南面図で、1〜7は、前記従来半導体製造方法の説明
図第9〜16図に示した構成要素と全く同一相″′!l
のものである。
1 to 8 show an embodiment of the t-conductor manufacturing method using the present invention in a two-culm sequence. Explanatory diagram of the method Exactly the same phase as the components shown in Figures 9 to 16''!l
belongs to.

(製造方法) 次に、この発明による製造方法を説明する。前記従来例
と同様、最終l]的は、第81Aに示1−ように半導体
基板表面に素f間分曙酸化膜を形成することにある。ま
ず、第1図に示すごとく、半導体基板1上の全表面に、
酸化マスク2を成I模した後、溝堀りエツチングのエツ
チングマスク材料に用いられるシリコン酸化195を成
膜、続いてシリコン酸化膜5を、写真製版工程を経てパ
ターニングし、半導体基板1を溝堀りエツチングした状
態か第2図である。ここまでの工程は、半導体基板18
トの溝堀り領域の形成に加えて、溝堀り領域以外の表面
を酸化マスク2が覆い、そのトに溝堀りエツチングのエ
ツチングマスク材料となったシリコン酸化1漠5が覆っ
た状態である。
(Manufacturing method) Next, the manufacturing method according to the present invention will be explained. As in the conventional example, the final goal is to form an oxidized film on the surface of the semiconductor substrate between elements f, as shown in No. 81A. First, as shown in FIG. 1, on the entire surface of the semiconductor substrate 1,
After forming the oxide mask 2, a silicon oxide film 195 used as an etching mask material for groove etching is formed, and then a silicon oxide film 5 is patterned through a photolithography process, and the semiconductor substrate 1 is grooved. Figure 2 shows the etched state. The steps up to this point are the semiconductor substrate 18
In addition to forming the grooved area on the top, an oxide mask 2 covers the surface other than the grooved area, and the silicon oxide layer 5, which is the etching mask material for the grooved etching, is covered. be.

次に、半導体基板1の準結晶シリコンを熱酸化し、全面
にシリコン窒化膜2を成膜した後、さらに全面にシリコ
ン酸化膜7を成+tq L、た状態が第3図、続いて、
このシリコン酸化ttQ 7を反応性イオンエツチング
等の異方性エツチングを用いてエツチングした状態が第
4図であり、溝の側壁面のみのシリコン酸化膜が上面方
向からの膜厚が厚いため、エツチングされずに枠となっ
て残存している。続いて酸化マスク2の除去して全面エ
ツチング、シリコン酸化膜3の全面エツチングを行なっ
た状態が第5図で、ここでは、溝の底面の酸化マスク2
のみを除去している。
Next, the quasi-crystalline silicon of the semiconductor substrate 1 is thermally oxidized to form a silicon nitride film 2 on the entire surface, and then a silicon oxide film 7 is further formed on the entire surface as shown in FIG.
Figure 4 shows a state in which this silicon oxide ttQ7 is etched using anisotropic etching such as reactive ion etching.The silicon oxide film on only the side wall surface of the trench is thick from the top surface direction, so the etching is difficult. It remains as a frame without being removed. FIG. 5 shows the state in which the oxide mask 2 is removed and the entire surface is etched, and the silicon oxide film 3 is etched over the entire surface.
only are removed.

すなわち、゛i導体)1ζ板l上の溝堀り領域以外の表
面は、溝堀りエツチングのマスク材料であるシリコン酸
化膜5、溝の側壁面は、異方性エツチングにより形成さ
れたシリコン酸化膜7の枠によってマスクされ、溝の底
面の酸化マスク2のみか除去されている。この工程は、
以上のように、+iif記従来例と全く同一である。次
に、分m酸化した状態か第6図であり、ここで溝の底面
の分離酸化膜か形成さねたわけである。
In other words, the surface of the (i-conductor) 1ζ plate l other than the grooved area is covered with a silicon oxide film 5, which is a mask material for groove etching, and the sidewalls of the groove are covered with a silicon oxide film formed by anisotropic etching. Masked by the frame of the membrane 7, only the oxide mask 2 at the bottom of the groove is removed. This process is
As described above, this is completely the same as the conventional example described in +iif. Next, the oxidized state is shown in FIG. 6, where the isolation oxide film at the bottom of the trench was not formed.

続いて、゛ト導体基板i 、1の溝堀り領域以外の表面
の分+11!酸化、ならびに溝の側壁面の分離酸化の酸
化マスクとなるシリコン窒化+142を多層レジストを
用いた写真製版工程を経て、同時にパターニングした状
態か第7図であり、ここでは、多層レジストの第1層1
1のレジスト6がまだ除去されていない状態である。次
に、このレジスト6を除去し、分離酸化した状態か第8
図である。これで、基叛トの溝掘り領域以外の分離なら
びに満の側壁面の分離酸化膜か形成されたわけで、すべ
ての分離丁桿は完rする。
Next, the surface area other than the grooved area of ゛conductor substrate i, 1 +11! Figure 7 shows the state in which silicon nitride +142, which serves as an oxidation mask for oxidation and isolation oxidation of the sidewalls of the trench, is simultaneously patterned through a photolithography process using a multilayer resist. 1
The resist 6 of No. 1 has not yet been removed. Next, this resist 6 is removed, and the separated and oxidized state is removed.
It is a diagram. With this, the isolation other than the grooved area of the base plate and the isolation oxide film on the side wall surfaces have been formed, and all the isolation plates are completed.

なお、」−記実施例の説明においては、第8図に示した
素子間分離酸化膜の製造方法について述へたが、この発
明は、その他の溝堀り領域以外の表向、及び溝の側壁面
に選択酸化!IQを用いた場合の素f−間分離全般の製
造Jf法にも通用できることはもちろんである。
In the description of the embodiment described in "-", the method for manufacturing the element isolation oxide film shown in FIG. Selective oxidation on the side wall! Of course, this method can also be applied to the Jf method for producing general f-element separation using IQ.

(発明の効果) 以l−1説明し・たように、この発明の製造方法によれ
ば、半導体基板上に満を掘った後、溝堀り領域以外の表
面ならびに溝の側壁面の分離に用いる選択酸化膜の酸化
マスクを、同時にパターニングすることにより、従来の
製造方法より写1“(製版工程及び分離酸化工程が少な
くなり、また、パターニング粒度が向上しt導体装置の
小形化、微細化に寄与し得る。
(Effects of the Invention) As explained in 1-1 below, according to the manufacturing method of the present invention, after a semiconductor substrate is fully excavated, the surface other than the grooved area and the side wall surface of the groove are separated. By simultaneously patterning the oxidation mask of the selective oxide film used, the number of plate-making steps and separation oxidation steps is reduced compared to the conventional manufacturing method, and the patterning grain size is improved, making it possible to miniaturize and miniaturize the T-conductor device. can contribute to

【図面の簡単な説明】[Brief explanation of the drawing]

第1図ないし第8図は、この発明に係る一実施例の半導
体製造方法の外工程シーケンスを示す要部破断断面図で
ある。第9図ないし第16図は、従来の製造力法の一例
の各工程シーケンスを示″4−要部破断断面図である。 1・・・・・パr−導体」^板 2・・・・・・酸化マスク 3・・・・・・酸化マスク下敷 4・・・・・・分m酸化+19 5.6.7・・・・・・エツチングマスクイ(理人大岩
増雄 @        * 機            概 飄「 w&       法 〜↑ 味       慨 載          較 手続補正書(自発) 1、事件の表示   特願昭 61−258980号2
、発明ノ名称:y、導体製造方法 3、補正をする者 (連絡先03(213) 342+特許部)(、′1・
′、7 ゝ\−−′ 方式 %式%) 5、補正の対象 (1)明細−Fの特許請求の範囲および発明の詳細な説
明の欄。 (2)図面第4図および第14図。 6、補正の内容 (1)特許請求の範囲を別紙のとおり訂正する。 (2)明細書の第4頁第17行の「シリコン酸化[7(
7)J ヲrシリコンe化111i3.5.7(7)J
 ト訂正する。 (3)明細書の第6頁第3行の「両者のセルフアライメ
ント」をr両者のセルフアライメント」と訂正する。 (4)明細書の第6頁第16行の「セルフアライメント
」を「セルフアライメント」と訂正する。 (5)明lBMの第9頁第18行乃至第19行の「酸化
マスク2の除去して全面エツチング」をr酸化マスク2
の全面エツチング」と訂正する。 (6)明細書の第9頁第19行の「シリコン酸化JIQ
 3の」を「シリコン酸化膜3,5.7の」と訂正する
。 (7)明細δの第10頁第18行の「こわで、」を「こ
こで、Jと訂正する。 (8)明細書の第10頁第19行の「溝掘り領域以外の
分離」を「満掘り領域以外の分I!!酸化I模」と訂正
する。 (9)明細−Fの第10頁第20行の「分離酸化膜が形
成さねたわけで」をr分Il!酸化膜が同時に形成され
たわけで」と訂正する。 (10)明細書の第1O頁第20行の「すべての」を「
これですべての1と訂正する。 (11)明細書の第11頁第4行の「この発明は、」を
rこの発明は第7図の構造のみならず、」と訂正する。 (12)明細書の第11頁第6行の「製造方法にも通用
」をr製造方法に適用Jと訂正1−る。 (13)明細書の第11頁第13行乃至第14行の「写
真製版工程及び分離酸化工程が少なくなり、」をr写真
製版工程が少なくなり、Jと訂正する。 (14)図面第4図、第14図を別紙のとおり訂正する
。 7、添付書類のIJ録 (1)補正後の特許請求の範囲を記載した書面1通 (2)補正後の図面第4図、第14図  1通特許請求
の範囲 (1)半導体基板に溝掘り領域を備えた3次元半導体装
置において、前記゛ト導体基板上の溝掘り領域以外の表
面ならびに溝の側壁面の素子量分I!!酸化1摸を1パ
ターンニングマスクを用いて形成することを特徴とする
半導体製造方法。 (2)前記半導体基板上の溝掘り領域以外の表面ならび
に溝の側壁面の素子間分間に、選択酸化膜を用いること
を特徴とする特許請求の範囲第1項記載の半導体製造方
法。 (3)前記半導体基板に掘られたえΔ且円証Ω皇及びに
゛ 、リ LL の′面のt  ヒ1′1を、多層レジ
ストを用いてパターニングすることを特徴とする特許請
求の範囲第1項または第2項記載の半導体製造方法。 第4図
1 to 8 are fragmentary cross-sectional views of essential parts showing an external process sequence of a semiconductor manufacturing method according to an embodiment of the present invention. FIGS. 9 to 16 are sectional views showing each process sequence of an example of the conventional manufacturing method. ... Oxidation mask 3 ... Oxidation mask underlay 4 ... Minute m oxidation +19 5.6.7 ... Etching mask (Masuo Rijin Oiwa @ * Machine General) "W & Law~↑ Comparison procedure amendment (voluntary) 1. Indication of the case Patent application No. 61-258980 2
, Title of invention: y, Conductor manufacturing method 3, Person making the amendment (Contact number 03 (213) 342 + Patent Department) (,'1・
', 7 ゝ\--' Formula % Formula %) 5. Subject of amendment (1) Scope of Claims and Detailed Description of the Invention in Specification-F. (2) Drawings 4 and 14. 6. Contents of amendment (1) The scope of claims is amended as shown in the attached sheet. (2) “Silicon oxidation [7(
7) J wor silicone 111i3.5.7 (7) J
Correct it. (3) In the third line of page 6 of the specification, "self-alignment of both" is corrected to "self-alignment of both." (4) "Self-alignment" on page 6, line 16 of the specification is corrected to "self-alignment." (5) ``Remove oxide mask 2 and perform etching on the entire surface'' on page 9, lines 18 to 19 of Akira IBM.
"Full-face etching," he corrected. (6) “Silicon Oxide JIQ” on page 9, line 19 of the specification
"3" is corrected to "silicon oxide film 3,5.7". (7) "Kowade," on page 10, line 18 of specification δ is corrected to "Here, J." (8) "Separation other than trenching area" on page 10, line 19 of specification I corrected it to "Other than the fully dug area I!! Oxidation I model". (9) "Because the isolation oxide film was not formed" on page 10, line 20 of Specification-F, r minute Il! This means that the oxide film was formed at the same time.'' (10) “All” in page 10, line 20 of the specification is replaced with “
Correct all 1's with this. (11) In the fourth line of page 11 of the specification, ``This invention covers not only the structure shown in FIG. (12) "Applicable to the manufacturing method" on page 11, line 6 of the specification applies to the r manufacturing method, and correction 1-1. (13) On page 11, lines 13 to 14 of the specification, ``The number of photolithography steps and separation oxidation steps will be reduced'' will be corrected to ``R, the number of photolithography steps will be reduced,'' and J. (14) Figures 4 and 14 of the drawings will be corrected as shown in the attached sheet. 7. IJ record of attached documents (1) One document stating the scope of claims after amendment (2) Drawings after amendment Figures 4 and 14 One copy of claims (1) Groove in semiconductor substrate In a three-dimensional semiconductor device having a trenched region, the amount of elements on the surface of the conductor substrate other than the trenched region and the side wall surface of the trench is I! ! A semiconductor manufacturing method characterized in that one oxide layer is formed using one patterning mask. (2) A method of manufacturing a semiconductor according to claim 1, characterized in that a selective oxide film is used on the surface of the semiconductor substrate other than the grooved region and between the elements on the sidewall surface of the groove. (3) The scope of the claim characterized in that the t 1'1 of the planes of the holes Δ, Ω, and LL dug in the semiconductor substrate are patterned using a multilayer resist. The semiconductor manufacturing method according to item 1 or 2. Figure 4

Claims (3)

【特許請求の範囲】[Claims] (1)半導体基板に溝堀り領域を備えた3次元半導体装
置において、前記半導体基板上の溝堀り領域以外の表面
ならびに溝の側壁面の素子間分離酸化膜を1パターンニ
ングマスクを用いて形成することを特徴とする半導体製
造方法。
(1) In a three-dimensional semiconductor device having a grooved region on a semiconductor substrate, a patterning mask is used to form an inter-element isolation oxide film on the surface of the semiconductor substrate other than the trenched region and on the sidewalls of the trench. A semiconductor manufacturing method characterized by forming a semiconductor.
(2)前記半導体基板上の溝堀り領域以外の表面ならび
に溝の側壁面の素子間分離に、選択酸化膜を用いること
を特徴とする特許請求の範囲第1項記載の半導体製造方
法。
(2) A method of manufacturing a semiconductor according to claim 1, characterized in that a selective oxide film is used for isolation between elements on a surface other than the grooved region on the semiconductor substrate and on sidewall surfaces of the groove.
(3)前記半導体基板に掘られた溝の側壁面の選択酸化
膜のマスクを、多層レジストを用いてパターニングする
ことを特徴とする特許請求の範囲第1項または第2項記
載の半導体製造方法。
(3) A semiconductor manufacturing method according to claim 1 or 2, characterized in that a mask of a selective oxide film on a side wall surface of a trench dug in the semiconductor substrate is patterned using a multilayer resist. .
JP25898086A 1986-10-30 1986-10-30 Manufacture of semiconductor Granted JPS63132446A (en)

Priority Applications (3)

Application Number Priority Date Filing Date Title
JP25898086A JPS63132446A (en) 1986-10-30 1986-10-30 Manufacture of semiconductor
DE19873736531 DE3736531A1 (en) 1986-10-30 1987-10-28 METHOD FOR PRODUCING A SEMICONDUCTOR DEVICE
US07/113,744 US4772569A (en) 1986-10-30 1987-10-28 Method for forming oxide isolation films on french sidewalls

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP25898086A JPS63132446A (en) 1986-10-30 1986-10-30 Manufacture of semiconductor

Publications (2)

Publication Number Publication Date
JPS63132446A true JPS63132446A (en) 1988-06-04
JPH0587142B2 JPH0587142B2 (en) 1993-12-15

Family

ID=17327685

Family Applications (1)

Application Number Title Priority Date Filing Date
JP25898086A Granted JPS63132446A (en) 1986-10-30 1986-10-30 Manufacture of semiconductor

Country Status (1)

Country Link
JP (1) JPS63132446A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP1744211A1 (en) * 2005-07-14 2007-01-17 ASML Netherlands BV Substrate, lithographic multiple exposure method, machine readable medium

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP1744211A1 (en) * 2005-07-14 2007-01-17 ASML Netherlands BV Substrate, lithographic multiple exposure method, machine readable medium

Also Published As

Publication number Publication date
JPH0587142B2 (en) 1993-12-15

Similar Documents

Publication Publication Date Title
JPH11345875A (en) Semiconductor device and manufacture thereof and photo mask used for the semiconductor device
JPS63132446A (en) Manufacture of semiconductor
JP2771057B2 (en) Method for manufacturing semiconductor device
JP3209209B2 (en) Method for manufacturing semiconductor device having capacitance contact hole
JPH07235594A (en) Manufacture of semiconductor device
JPH0587141B2 (en)
JPH0845942A (en) Metal wiring formation of semiconductor element
JP2727587B2 (en) Multilayer wiring method
TW594448B (en) Overlay mark and method for making the same
JP2669160B2 (en) Method for manufacturing semiconductor device
JPH036058A (en) Semiconductor device
JPH079933B2 (en) Method for manufacturing semiconductor device
JPH0387030A (en) Multilayer interconnection
JPH0661354A (en) Manufacture of semiconductor device
JP2836587B2 (en) Method for manufacturing semiconductor device
JPH04299838A (en) Manufacture of semiconductor device
JPS63229747A (en) Manufacture of semiconductor device
JPH07142776A (en) Pattern formation
JPH0349212A (en) Formation of alignment mark for exposure pattern of semiconductor device
JPH0636134B2 (en) Thin film transistor matrix and method of forming the same
JPH01204441A (en) Manufacture of semiconductor device
JPH03175645A (en) Manufacture of semiconductor device
JPS6321847A (en) Forming method for element separating region for semiconductor integrated circuit
JPS62242335A (en) Formation of element isolating region of semiconductor integrated circuit
JPH01171226A (en) Flattened etching

Legal Events

Date Code Title Description
S111 Request for change of ownership or part of ownership

Free format text: JAPANESE INTERMEDIATE CODE: R313111

R360 Written notification for declining of transfer of rights

Free format text: JAPANESE INTERMEDIATE CODE: R360

R360 Written notification for declining of transfer of rights

Free format text: JAPANESE INTERMEDIATE CODE: R360

R371 Transfer withdrawn

Free format text: JAPANESE INTERMEDIATE CODE: R371

S111 Request for change of ownership or part of ownership

Free format text: JAPANESE INTERMEDIATE CODE: R313111

R350 Written notification of registration of transfer

Free format text: JAPANESE INTERMEDIATE CODE: R350

EXPY Cancellation because of completion of term