JPS6313170A - Digital recording and reproducing system - Google Patents

Abstract

PURPOSE:To simplify the device constitution and to improve the system by establishing the synchronization of a large block synchronizing signal after a synchronizing signal added before a data signal is established so as to attain stable synchronization and reproduction. CONSTITUTION:A separator circuit 33 compares synchronizing signal patterns from a reproduced signal in a recording medium being decoded into the original digital signal by a code conversion circuit 31 according to the timing being extracted and recovered by a clock recovery circuit 32 to recover the synchronizing signal Sync thereby establishing the synchronization of a small block. On the other hand, the synchronizing signal extracted by the circuit 33 is fed to a control signal gate circuit 39, the synchronization is established according to the signal Sync, and a synchronizing separator circuit 40 separates the synchronizing signal Sync according to the recovered clock from a control signal CB in the small block extracted from the output of the circuit 31 through the timing control by the recovered clock and a control signal recovery circuit 41 recovers a control information signal from the signal CB according to the signal Sync. Thus, the synchronization is established by one synchronizing system and the signal Sync basically at the reproduction and stable reproduction is obtained.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a digital recording reproducing apparatus useful for digitizing audio signals and the like, recording them on a recording medium, and reproducing them.

2. Description of the Related Art Conventionally, when so-called audio signals such as voices and musical tones are digitized and recorded on a recording medium, the following procedure is generally used. That is, one sample of the audio signal is treated as a one-word data signal, and one-word parity signals P and Q, each consisting of Σ:MOD2 operation T:matrix, are added to several words of data signals DI, . . . , Dn.

After interleaving these and taking measures against burst errors, a first synchronization signal S corresponding to one word and an error check signal ECC are added to form a small block as shown in FIG. In other words, it forms the first block. Furthermore, a plurality of the above-mentioned first
The blocks are integrated and a second synchronization signal S and a control signal CBC are added thereto to form a second block, and this is used as a unit to create an MF suitable for recording.
The data is recorded on a disk recording medium after being subjected to code conversion such as M. The control signal CBo includes the number of multiplexed channels, address information used to search for data signals, and the like.

The signal recorded on the disk recording medium in the format shown in FIG. 1 is reproduced and restored by, for example, a reproducing apparatus having the configuration shown in FIG. 2. That is, the code converter 1 restores the MFM signal to its original digital signal form, and the clock reproducing circuit 2 regenerates the clock of the reproduced signal, that is, the bit synchronization signal. Synchronous separation circuit 3
reproduces the second synchronization signal S given to the second block from the reproduced signal in accordance with the reproduced clock, thereby establishing synchronization of the C-th block. Further, the synchronization separation circuit 4 selects the first synchronization signal S from the reproduced signal according to the second synchronization signal S and the reproduced clock C.
is playing. This establishes the synchronization of the first block nC lock. Thus, the memory 5 sequentially writes the data signal and parity signal in the reproduced signal to predetermined addresses in accordance with the first and second synchronization signals, and also writes the error check signal ECC separated by the error check circuit 6 to each word. Each is given.

In this memory 5, the data signal and the parity signal are dinterleaved and output. Error correction circuit 7
is to manually input the above output signal and perform error correction on the data signals DI, ~, D based on the parity signals P and Q.
The corrected output is converted into an analog signal by a D/A converter 8. Further, the control signal reproducing circuit 9 is connected to the first and second
The control signal CBC is separated and reproduced from the output signal from the memory 5 according to the synchronization signal. This control signal CBo
Accordingly, the demultiplexer 10 operates and outputs the analog-converted data signal to a predetermined channel.

In this way, the signal recorded on the disk recording medium is reproduced and restored.

By the way, in order to perform the above signal reproduction correctly, reproduction of the first and second synchronization signals is an important issue. For example, if the synchronization signal position deviates from the normal position, each data word will be significantly distorted, resulting in significant deterioration of signal quality.

Therefore, conventionally, the second synchronization signal is used to establish synchronization of the second block, and then the first synchronization signal is used to establish synchronization of the first block. Control was complicated because two synchronization signals were required. Moreover, the number of bits in the second block corresponding to the second synchronization signal is quite large, and therefore it is necessary to increase the number of bits in the synchronization signal to improve accuracy. Therefore, the hardware configuration of the synchronous separation circuit 3 has become considerably complicated. Furthermore, there is the problem that the number of samples of a data signal reproduced from a disk recording medium in a certain period of time must be equal to the number of samples of a signal converted into an analog signal. This certain period of time is generally determined with the second block as one unit. At this time, it is necessary to reproduce signals including synchronization signals, check signals, etc., so if the number of samples per block is n and the second block is formed from r first blocks, then the data The number of words is (n
+3) It also reaches Xr. On the other hand, the number of sample data in these words is n(r-1). It is necessary to temporally match these data numbers. However, the above-mentioned ratio is generally not an integer, which makes the clock of the control system considerably slow, and it is necessary to set the frequency of the master clock sufficiently high. This also resulted in major system limitations.

The present invention divides the second synchronization signal and control signal of a large block composed of a plurality of small blocks, and provides the position of the control signal of the small block, that is, immediately after the first synchronization signal forming the small block. When reproducing the inserted and digitally recorded signal, the synchronization signal of ff12 is established after the synchronization of the first synchronization signal is established.

DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the apparatus of the present invention will be described below with reference to the drawings.

FIG. 3 shows the basic data format in the present invention, in which a parity signal P is added to a plurality of word data signals.
, Q are added one word each, and an error check signal E is added.
One word of CC is added, and a group of information bits corresponding to one word further forms a first block. Then, a plurality of the first blocks are put together to form a second block. In this case, the control signal CB is inserted into the information bit group along with ynC for inserting the synchronization signal S for establishing synchronization of the first block. When the control signal CB is separated and extracted from each first block over the entire second block and summarized, as shown in the figure, the second synchronization signal Syc control information signal CBc and error check for these signals are generated. This is to form an error check signal CEc for use.

In other words, the control signal C3 of the program consisting of the synchronization signal 81 control information signals CBC and C and the error check signal CEc is divided according to the number of first blocks constituting the second block, for example, divided into equal parts. are inserted into predetermined positions of each information bit group of the first block to form a data format.

In this case, the information bit group of the first block is determined at the beginning of the first block in consideration of establishing block synchronization and the like. That is, as shown in Fig. 3, one word nC is constructed by inserting the control signal CB following the synchronization signal S, followed by multiple words of data signals, parity signals P and Q, and error checking for each word. Since the data format is added with the signal ECC, word synchronization becomes periodic, which is convenient in terms of hardware configuration.

FIG. 4 is a schematic configuration diagram of a digital recording and reproducing apparatus that digitizes an audio signal according to the above data format, records it on a disk recording medium, and reproduces and restores the same, where A indicates a recording section and B indicates a reproducing section. ing. Hereinafter, the present invention will be explained in detail according to the configuration and operation of this device.

The n-channel audio input signal is sent to multiplexer 1.
1 and is time-division multiplexed and input. The A/D converter 12 converts the input signals into digital data signals of, for example, 16 bits per sample at a predetermined sampling period.

The above-mentioned 16-bit data discard is supplied to the parity addition circuit 13 as one word, and the above-mentioned MOD2
The parity signals P and Q resulting from the calculation are added to the memory 14.
are written sequentially. The data signal and parity signal P are stored in this memory 14.

Interleave processing is performed on Q. On the other hand, the control signal generation circuit 15 generates a control information signal CBo, such as the number of channels of the input signal and address information for the data signal, such as information necessary for locating the beginning of the song when the data signal indicates music, to the data signal. It is occurring in response.

A check signal generation circuit 16 inputting this control information signal CBo generates an error check signal CEc for the same signal C, and supplies the error of B to an adder 17 to add it to the control information signal C. Further, the main circuit 13 for generating a synchronizing signal for control signals generates a second synchronizing signal S for the control signal CB.
The adder 19 selects and extracts these as appropriate and places each signal at a predetermined position. Therefore, the output signal sequence of the adder 19 is a control C signal CBcl consisting of a synchronization signal S or a control information signal CBo, etc.: a plurality of word ≠-ta signals and parity signals P and Q. The signal error check circuit 20 generates an error check signal ECC for the signal series, and the adder 21 adds it to the signal series. The signal synchronization signal generation circuit 22 generates a synchronization signal S at intervals corresponding to the period of the first block.
The adder 23 inserts the ynC synchronization signal S at the beginning of the signal series, that is, at the beginning of the first block of ynC to complete the signal format as shown in FIG.

The code conversion circuit 24 converts the signal into a signal waveform suitable for recording on a disk recording medium by, for example, performing MFM conversion on the signal, and outputs this to the recording device. Thus, by digitizing the n-channel analog signal. Recording is performed on the disk recording device.

Now, the signal recorded as described above is reproduced and restored as follows. The reproduced signal from the disc recording medium is restored to the original digital signal form by the code conversion circuit 31. At the same time, the clock reproducing circuit 32 extracts signal timing from the reproduced signal and reproduces the clock timing of the signal. According to this clock timing, the separation circuit 33 reproduces and restores the synchronization signal S from the reproduced signal, for example, by comparing the synchronization signal patterns.
C There is. The ynC synchronization of the first block is established by this synchronization signal S, and the reproduced data signal and parity signals P and Q are sequentially written into the memory 34. At this time, the error check circuit 35 separates and extracts the error check signal ECC from the reproduced and restored signal, performs an error check, and supplies it to the memory 34 to be used as the data signal and parity signals P and Q. are given to each. The memory 34 performs dinterleaving on the written data signal and parity signals P and Q, and sequentially reads them out and outputs them to the error correction circuit 36. The error correction circuit 36 performs error correction of the data signal based on the parity signals P and Q. The D/A converter 37 restores the error-corrected data signal to an analog signal, and the demultiplexer 38 distributes and outputs the analog signal to predetermined channels in accordance with control information to be described later.

On the other hand, the synchronization signal extracted by the synchronization separation circuit 33 is supplied to a control signal gate circuit 39. This gate circuit 39 establishes synchronization with the synchronization signal S according to the synchronization signal S, and is timing-controlled by the reproduction clock to obtain information on a predetermined position in the first block from the reproduction restoration signal (output signal of the code conversion circuit 31), that is, a control signal. CB is selectively extracted. Synchronous separation circuit 4
0 separates and reproduces the second synchronization signal S from the selectively extracted control signal Cs according to the reproduction clock.

The control signal reproducing circuit C41 reproduces the control information signal CBC from the control signal CB in accordance with the second synchronization signal S of the control signal CB. The demultiplexer 38 performs a channel separation operation according to the number of signal channels indicated in the control information signal CBo and its synchronization information. still,
When the error check circuit 42 detects an error in the control information signal CBC from the error check signal C, the control signal reproducing circuit 41 stops the reproducing operation and reproduces the control information signal CBo obtained from the next second block. It is configured to perform playback operations on.

The functions of this method in the above-mentioned apparatus configured and operated in this way are enormous as follows. That is, when reproducing a signal from a disk recording medium,
Basically, it is only necessary to establish synchronization using one synchronization system, that is, the synchronization signal S, which is extremely stable and less likely to lose synchronization compared to the conventional system. Moreover, since the first block and the second block are not independently synchronized using the second synchronization signal,
The control system is easy, and the hardware configuration can be simplified. Furthermore, since the memory 34 and the error correction circuit 36 can be controlled block by block and periodically, simple and stable operation can be expected. Furthermore, regarding the master clock, there is no need to take any measures for the control signal block, so the number of reproduced samples and the number of output samples can be easily matched, and there is no need to increase the frequency of the master clock. This is very advantageous when converting the device into an LSI, and can reduce the cost of the device.

On the other hand, identification of the control information signal CBC essentially requires two synchronization signals S and S, but the above ynQ
The synchronization signal S can be regarded as a form of the control signal CI3, and no special pattern measures are required. Moreover, the control signal CB generally does not change instantaneously;
For example, it can be considered that there is no change during one revolution of disk reproduction. Therefore, even if synchronization with the control signal CB occurs, if synchronization is established at an appropriate timing, the original state will be restored, and no inconvenience will occur. Therefore, the configuration of the control signal reproducing system can be significantly simplified. Furthermore, even if the control information at that moment is lost due to loss of synchronization, it can be immediately supplemented at the next timing, so virtually no problem occurs. Moreover, since the control signals are not absolutely essential to the data signals, they can be simplified as appropriate depending on the use.

By the way, in the above explanation, the control signal CB (synchronization signal S
Control information signal C1 machine check signal yc
BC, CEC) is simply divided and these are sequentially inserted into predetermined bit positions of one block, but the following may also be used. For example, if the information sequence of the first block is taken as one unit and is arranged two-dimensionally to form the second block, then the data signal position, the parity signals P and Q, and the error check signal ECC are located at the fifth block. They are selected based on a certain relationship as shown in the figure. At this time, the synchronization signal S position, nC position, and control signal CB position are also arranged in an orderly manner at predetermined positions. Therefore, when considering such a signal arrangement, the e pattern information of the second synchronization signal S for second block synchronization is distributed and inserted into each first block over the second block, as shown in FIG. However, the control information signal CBo can also be inserted in a distributed manner in the same manner. Therefore, the synchronization signal Sy0 and the control information CB
When reproducing the synchronizing signal S component and the control information signal CB at a predetermined timing from each first block nC whose synchronization has been established by the synchronizing signal S. The components may be specifically separated and extracted and, for example, sequentially written into a memory. By combining these over the second block, the second synchronization signal S
pattern, and also the control information C signal CBC. If this type of method is adopted, the number of bits of the synchronization signal S can be increased, and even if a burst error occurs, the error can be dispersed and simple error correction can be performed, so it is very effective. It is possible to establish stable synchronization, that is, to establish synchronization of the second block. Furthermore, even if an error check signal is added, it can be inserted for each block (word), so reliability can be improved.

Further, as shown in FIG. 6, a second synchronization signal Sy.

If you do not need a very large number of bits for
The components of the second synchronization signal S may be distributed and inserted only into a predetermined number of 11C blocks, and the components of the control information signal CBo may be distributed and inserted into the remaining blocks. In this way, a large number of bits can be allocated to the control information signal CBG, making it possible to stably record and reproduce a variety of control information.

By the way, in the above example, it was explained that the error check signal ECC included in the first block acts only on the data signal and the parity signals P and Q, but the error check signal ECC including the control signal CB You may also give In this case, it is sufficient to attach an error pointer to each predetermined portion of the control block, and use the error pointer to identify whether or not an error has occurred. That is, when the synchronization signal S for control is reproduced, the synchronization signal S
All you have to do is determine whether C is normal or accidental.

FIG. 7 is a diagram showing an example of the configuration of a reproducing apparatus used for digital recording and reproducing using the error pointer. The synchronization signal S in the signal reproduced from the disk recording medium is separated and extracted by the synchronization separation circuit 51 according to its clock timing nC, and is used for establishing synchronization of the first block. The memory 52 in which the data signal, nC, parity signal, and Q in the reproduced and restored signal are written in accordance with the synchronization signal S functions similarly to the memory 34 of the previous embodiment (shown in FIG. 4). The control signal gate circuit 53 also controls the synchronization signal S.
The control signal CB is separated and extracted according to the clock timing and the control signal C.
B is supplied to the shift register 54 and also supplied to the error check circuit 55. This error check circuit 55 performs an error check on the control information signal CBc based on the error check signal CEc in the control signal Cs. If there is no error in the control information signal CBc, the error check circuit 55 issues a latch signal via the gate circuit 56, and the data stored in the shift register 54 (
The control information signal CBc) is latched in the latch circuit 57. In this manner, the various control information signals described above are read out from this latch circuit 57.

On the other hand, the synchronization separation circuit 58 extracts the second synchronization signal S1 component from the separated and extracted control information CB according to the clock timing. The shift register 59 installed for synchronization protection has a register configuration having the same period as the synchronization signal S, and is normally reset by the output of the synchronization separation circuit 58. That is, the shift register 59 includes a gate circuit 61 whose gate is controlled by a counter circuit 60, which will be described later, and a wind gate circuit 6 using the output of the shift register 59.
2 to the synchronous separation circuit 5 through the OR circuit 63.
It is reset by the output of 8 to establish synchronization. However, now, the counter circuit 6o counts the number of errors at the error points detected by the error check circuit 64, and when the counted value reaches a predetermined value, the counter circuit 60 issues a gate control signal. The gate circuit 61 is closed. As a result, the reset signal is no longer applied to the shift register 59, and the shift register 59 directly outputs the previously stored signal, that is, the signal with the previous phase, as a reproduction synchronization signal.

Now, the counter circuit 65 counts the number of errors in the error pointer during the period excluding the synchronization signal S and part C. When the error check circuit 55 detects an error in the control information signal CBE even though the count value by the counter circuit 65 is "zero", this means that the synchronization for the control signal is lost. ing. When this state occurs, the gate circuit 66 which receives the outputs of the counter circuit 65 and the error check circuit 55 opens the gate circuit 67 for resetting the shift register 59,
The shift register 59 is reset to C with the next synchronization signal S to restore synchronization. Further, the counter circuit 68 calculates the number of reset signals that are not captured by the wind gate circuit 68, and when a predetermined value is reached, the gate circuit 67 is opened, assuming that the synchronization has been lost. By opening this gate circuit 67, the shift register 59 is reset and automatic restoration of synchronization is performed. Then, the shift register 59 synchronously reproduces the
When the error check circuit 55 determines that there is no error in the control information signal CB, the gate circuit 56 is opened with an appropriate phase pulse, and the correct control concession signal CBC is latched into the latch circuit 57.

Thus, if the synchronous regeneration circuit with the above configuration is provided, the control signal C
Even if the synchronization is lost when reproducing B, the synchronization will be restored when the next second block is reproduced. Then, the reproduction control signal C8 when the synchronization is lost is not outputted, and only the control signal CB, in which synchronization is correctly established and no error has occurred, is reproduced and outputted. This is because when a signal is reproduced from a disk recording medium, the control signal does not vary much with respect to a series of information groups, and moreover, it can be considered that the information is exactly the same in one rotation of the disk recording medium. Therefore, if the mm control information is reproduced accurately, the information can be used as is to some extent, making the above reproduction method very effective.

By the way, if the synchronization for control is sufficiently stable or if there is no problem even if the synchronization is slightly out of synchronization, the error pointer may be simply checked as shown in FIG. That is, the error pointer is shifted to the shift register 71.
When the control information input to the shift register 72 is latched into the latch circuit 73, the latch command signal and each bit output of the shift register 71 are latched by gate control by the gate circuits 74a, 74b, -T4n. The circuit 73 is configured to apply a latch signal to each bit. At the same time, gate circuits 74a, 74b, ~7
4n outputs to flip-flops 75a, 75b, ~7
5n and set in order from the latch output. And these flip-flops 75a, 75b
, ~75n gate circuits 74a, 74b~
74n, and the flip-flops 75a,
75b and 75n are configured to be reset at predetermined intervals. In this way, the control signal CB components can be extracted sequentially from the bit position where it is determined that no error occurs by the error pointer without performing the above-mentioned error check of the control signal, so for example, a predetermined number of second blocks can be reproduced. This makes it possible to accurately identify the control information CB. Note that the parity signal for error correction is the control signal CB.
If the error pointer is included, the error pointer may be used to correct one or more errors in the control block according to various correction methods.

In addition, in the apparatus of the present invention, specifically, for example, the following constant settings may be performed. For example, assume that the audio signal sample frequency is 50.4 KHz, the number of bits per sample is 16 bits, and the number of input channels is 4 channels. In this case, assuming that the first block has 16 bits per word, there are 8 words of data signals, 2 words of parity signals P and Q, 1 word of error check signal ECC, and synchronization signal S.
and nC control signal CB together form one word, forming the signal sequence of the first block. However, the synchronization signals S, S
Allocating 15 bits each to yna
yc, the control signal is a 1-bit column in the vertical direction of the second block. Now, the second block length is conveniently set to 1/300 seconds for NTSC or PAL television signals. If you set it as having one period, it will be 8.
This results in 4 bits of space. Therefore, even if the synchronization signal and the error check signal are inserted one word at a time into the above space, the control signal CB can be inserted into the remaining 52 bits. Therefore, even if the number of channels and the song start address for the music signal are included as the control signal CB, it can be realized with sufficient margin.

FIG. 9 shows the clock system of the control system when the present invention is executed under the above conditions. In this case, word synchronization, the first block frequency, the second block frequency, etc. can be obtained by generating a 4.8 MHz master clock and counting down as appropriate.

In other words, the clock signal control system can be realized very easily, and there is no need to set the frequency of the master clock so high. Therefore, it is very easy to implement the device.

As explained above, according to the present invention, it is possible to perform stable synchronized reproduction at all times to effectively reproduce data signals, and also to simplify the clock control system and the like, thereby greatly simplifying the device configuration. It is possible to exhibit various special advantages and effects, and to improve the system configuration. Furthermore, in the present invention, the second synchronization signal and control signal of the large block are divided and inserted and recorded immediately after the first synchronization signal of the small block.
Word synchronization is periodic, which simplifies the hardware configuration and provides stable synchronization.

Incidentally, the present invention is not limited to the above-described embodiments either. For example, the basic configurations of the first block and the second block can be modified in various ways according to specifications without departing from the gist thereof. Furthermore, the configuration of the recording/reproducing apparatus employing the present invention, the configuration of the synchronous reproducing circuit, etc. are not limited. In short, the device of the present invention can be modified in various ways without departing from the gist thereof, and can be applied to various recording and reproducing devices.

[BRIEF DESCRIPTION OF THE DRAWINGS] Fig. 1 is a diagram showing a data format for recording and reproducing in a conventional device, Fig. 2 is a configuration diagram of a conventional reproducing device, and Fig. 3 is a diagram showing signal data according to an embodiment of the present invention. 4 is a schematic configuration diagram of a signal recording and reproducing apparatus constructed by applying the present invention, FIGS. 5 and 6 are diagrams showing other data formats of the signal, and FIG. 7 is a diagram showing the format. A configuration diagram of a control signal regeneration circuit for synchronized reproduction with respect to the control signal C8, FIG. 8 is a diagram showing another configuration example of the control signal regeneration circuit,
FIG. 9 is a schematic diagram showing the clock system. 13 ... Parry addition circuit 14 ... Memory 15 ... Control signal generation circuit 16 ... Check signal generation circuit 18 ... Control signal synchronization generation circuit 20 ... Signal error check generation circuit 22・
- Signal synchronization generation circuit 32 ... Clock regeneration circuit 33 ... Synchronization separation circuit 34 ... Memory 35 ... Error check circuit 36 ... Error correction circuit 39 ... Control signal gate circuit 40 ...・Synchronization separation circuit 41 ... Control signal regeneration circuit 42 ... Error check circuit 54 ... Shift register 57 ... Latch circuit 59 ... Shift register 60 ... Counter circuit 65 ... Counter circuit application Person's representative Patent attorney Noriyuki Chika (and 1 other person) 14 Figure Syr+c Cac Figure 5 yc Sync Cac

Claims (1)

[Claims] A first synchronization signal and a control signal following this synchronization signal are added before a data signal to form a small block, and a second synchronization of a large block composed of a plurality of small blocks is performed. When reproducing a digitally recorded signal by dividing the signal and the control signal and inserting the same into the position of the control signal of the small block in place of the control signal of the small block, after establishing the synchronization of the first synchronization signal, A digital recording and reproducing device that establishes synchronization of two synchronization signals.