JPS6313154B2 - - Google Patents

Info

Publication number
JPS6313154B2
JPS6313154B2 JP58080216A JP8021683A JPS6313154B2 JP S6313154 B2 JPS6313154 B2 JP S6313154B2 JP 58080216 A JP58080216 A JP 58080216A JP 8021683 A JP8021683 A JP 8021683A JP S6313154 B2 JPS6313154 B2 JP S6313154B2
Authority
JP
Japan
Prior art keywords
tester
test
logic
circuit
phase
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP58080216A
Other languages
English (en)
Japanese (ja)
Other versions
JPS58225365A (ja
Inventor
Puri Puremu
Kei Puri Yogi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
International Business Machines Corp
Original Assignee
International Business Machines Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by International Business Machines Corp filed Critical International Business Machines Corp
Publication of JPS58225365A publication Critical patent/JPS58225365A/ja
Publication of JPS6313154B2 publication Critical patent/JPS6313154B2/ja
Granted legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/319—Tester hardware, i.e. output processing circuits
    • G01R31/3193—Tester hardware, i.e. output processing circuits with comparison between actual response and known fault free response
    • G01R31/31937—Timing aspects, e.g. measuring propagation delay

Landscapes

  • Engineering & Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Tests Of Electronic Circuits (AREA)
  • Test And Diagnosis Of Digital Computers (AREA)
JP58080216A 1982-06-18 1983-05-10 論理回路の試験方法 Granted JPS58225365A (ja)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US06/389,820 US4477902A (en) 1982-06-18 1982-06-18 Testing method for assuring AC performance of high performance random logic designs using low speed tester
US389820 2003-03-17

Publications (2)

Publication Number Publication Date
JPS58225365A JPS58225365A (ja) 1983-12-27
JPS6313154B2 true JPS6313154B2 (US07714131-20100511-C00024.png) 1988-03-24

Family

ID=23539853

Family Applications (1)

Application Number Title Priority Date Filing Date
JP58080216A Granted JPS58225365A (ja) 1982-06-18 1983-05-10 論理回路の試験方法

Country Status (4)

Country Link
US (1) US4477902A (US07714131-20100511-C00024.png)
EP (1) EP0097781B1 (US07714131-20100511-C00024.png)
JP (1) JPS58225365A (US07714131-20100511-C00024.png)
DE (1) DE3365089D1 (US07714131-20100511-C00024.png)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6393941U (US07714131-20100511-C00024.png) * 1986-12-10 1988-06-17

Families Citing this family (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4575674A (en) * 1983-07-01 1986-03-11 Motorola, Inc. Macrocell array having real time diagnostics
US4564943A (en) * 1983-07-05 1986-01-14 International Business Machines System path stressing
EP0146645B1 (de) * 1983-12-08 1987-09-16 Ibm Deutschland Gmbh Prüf- und Diagnoseeinrichtung für Digitalrechner
JPH0772744B2 (ja) * 1984-09-04 1995-08-02 株式会社日立製作所 半導体集積回路装置
US4962474A (en) * 1987-11-17 1990-10-09 International Business Machines Corporation LSSD edge detection logic for asynchronous data interface
US5097468A (en) * 1988-05-03 1992-03-17 Digital Equipment Corporation Testing asynchronous processes
US5039939A (en) * 1988-12-29 1991-08-13 International Business Machines Corporation Calculating AC chip performance using the LSSD scan path
US5018144A (en) * 1989-04-28 1991-05-21 International Business Machines Corporation Logic performance verification and transition fault detection
EP0555267A4 (en) * 1990-09-24 1994-05-18 Transwitch Corp Sonet signal generating apparatus and method
US5414714A (en) * 1992-03-26 1995-05-09 Motorola, Inc. Method and apparatus for scan testing an array in a data processing system
US5606567A (en) * 1994-10-21 1997-02-25 Lucent Technologies Inc. Delay testing of high-performance digital components by a slow-speed tester
SE505091C2 (sv) 1995-10-03 1997-06-23 Ericsson Telefon Ab L M Redundansstruktur vid digital väljare
US5768159A (en) * 1996-05-02 1998-06-16 Northern Telecom Limited Method of simulating AC timing characteristics of integrated circuits
KR100735920B1 (ko) * 2005-12-28 2007-07-06 삼성전자주식회사 디바이스 테스트 장치 및 방법과, 그 인터페이스 장치
US20080082880A1 (en) * 2006-09-06 2008-04-03 Hsin-Po Wang Method of testing high-speed ic with low-speed ic tester
US11842782B2 (en) * 2021-09-30 2023-12-12 EMC IP Holding Company LLC Phased parameterized combinatoric testing for a data storage system

Family Cites Families (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3107329A (en) * 1960-08-29 1963-10-15 Bell Telephone Labor Inc Method and apparatus for measuring time delay in transmission paths
US3333187A (en) * 1964-03-25 1967-07-25 Sperry Rand Corp Pulse duration measuring device using series connected pulse width classifier stages
FR2104641B1 (US07714131-20100511-C00024.png) * 1970-03-03 1973-08-10 Commissariat Energie Atomique
US3675127A (en) * 1970-12-28 1972-07-04 Bell Telephone Labor Inc Gated-clock time measurement apparatus including granularity error elimination
US3761695A (en) * 1972-10-16 1973-09-25 Ibm Method of level sensitive testing a functional logic system
US3783254A (en) * 1972-10-16 1974-01-01 Ibm Level sensitive logic system
GB1389894A (en) * 1972-10-28 1975-04-09 Ferranti Ltd Apparatus for the measurement of short time intervals
CA1065060A (en) * 1976-04-01 1979-10-23 David L. Freeman Cross-correlator circuit
US4063080A (en) * 1976-06-30 1977-12-13 International Business Machines Corporation Method of propagation delay testing a level sensitive array logic system
DE2842750A1 (de) * 1978-09-30 1980-04-10 Ibm Deutschland Verfahren und anordnung zur pruefung von durch monolithisch integrierten halbleiterschaltungen dargestellten sequentiellen schaltungen
US4293919A (en) * 1979-08-13 1981-10-06 International Business Machines Corporation Level sensitive scan design (LSSD) system
US4285059A (en) * 1979-12-10 1981-08-18 The United States Of America As Represented By The Secretary Of The Army Circuit for test of ultra high speed digital arithmetic units

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6393941U (US07714131-20100511-C00024.png) * 1986-12-10 1988-06-17

Also Published As

Publication number Publication date
EP0097781B1 (en) 1986-08-06
JPS58225365A (ja) 1983-12-27
US4477902A (en) 1984-10-16
EP0097781A1 (en) 1984-01-11
DE3365089D1 (en) 1986-09-11

Similar Documents

Publication Publication Date Title
US5606567A (en) Delay testing of high-performance digital components by a slow-speed tester
KR100335683B1 (ko) 속도 관련 결함을 테스트하기 위해 멀티플렉서 스캔플립플롭을 이용하는 방법 및 장치
JPS6313154B2 (US07714131-20100511-C00024.png)
US5349587A (en) Multiple clock rate test apparatus for testing digital systems
US6510534B1 (en) Method and apparatus for testing high performance circuits
US3784907A (en) Method of propagation delay testing a functional logic system
EP0394611B1 (en) Logic performance verification and transition fault detection
US6032278A (en) Method and apparatus for performing scan testing
KR940020127A (ko) 반도체 집적회로 및 그 테스트방법
US7228476B2 (en) System and method for testing integrated circuits at operational speed using high-frequency clock converter
US8375265B1 (en) Delay fault testing using distributed clock dividers
US5473618A (en) Semiconductor integrated circuit having a built-in test circuit
EP0702241B1 (en) Structural and performance scan test
US7421634B2 (en) Sequential scan based techniques to test interface between modules designed to operate at different frequencies
US6976199B2 (en) AC LSSD/LBIST test coverage enhancement
JPH0440113A (ja) フリップフロップ回路及び半導体集積回路
KR100305678B1 (ko) 반도체장치의테스터
US5754063A (en) Method and apparatus to measure internal node timing
JP3328160B2 (ja) 論理集積回路のテスト装置
EP3859361A1 (en) An electronic circuit and corresponding method of testing electronic circuits
US11768239B1 (en) Method and apparatus for timing-annotated scan-chain testing using parallel testbench
JP4644966B2 (ja) 半導体試験方法
Alluri et al. Small Delay Tracing Defect Testing
JPH1152015A (ja) 高速半導体集積回路装置のテスト回路
WO2006138583A2 (en) Sequential scan test of interface between ic modules that operate at different frequencies