JPS63131434U - - Google Patents

Info

Publication number
JPS63131434U
JPS63131434U JP2210587U JP2210587U JPS63131434U JP S63131434 U JPS63131434 U JP S63131434U JP 2210587 U JP2210587 U JP 2210587U JP 2210587 U JP2210587 U JP 2210587U JP S63131434 U JPS63131434 U JP S63131434U
Authority
JP
Japan
Prior art keywords
data
received
processor unit
limit value
receiving device
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2210587U
Other languages
Japanese (ja)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP2210587U priority Critical patent/JPS63131434U/ja
Publication of JPS63131434U publication Critical patent/JPS63131434U/ja
Pending legal-status Critical Current

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Landscapes

  • Dc Digital Transmission (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)

Description

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本考案の一実施例を示すブロツク図、
第2図はユニバーサル非同期送受信器の動作を説
明するためのタイムチヤート、第3図はプロセツ
サユニツトの処理プログラムの一例を示すフロー
チヤートである。 1……ユニバーサル非同期送受信器、3……プ
ロセツサユニツト。
FIG. 1 is a block diagram showing an embodiment of the present invention.
FIG. 2 is a time chart for explaining the operation of the universal asynchronous transceiver, and FIG. 3 is a flow chart showing an example of a processing program of the processor unit. 1...Universal asynchronous transceiver, 3...Processor unit.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] 受信パルスを直列データとして調歩同期方式に
より並列データに変換しプロセツサユニツトに送
出するユニバーサル非同期送受信器を備えたパル
ス信号受信装置においてプロセツサユニツトは、
一定周期でユニバーサル非同期送受信器による受
信データの有無を調べ、当該受信データから受信
パルスの幅が所定の上限値および下限値の間にあ
ると判断されることを条件として、それに続くデ
ータの受信処理を実行することを特徴とするパル
ス信号受信装置。
In a pulse signal receiving device equipped with a universal asynchronous transceiver that converts received pulses into serial data into parallel data using an asynchronous method and sends it to a processor unit, the processor unit
The presence or absence of received data by the universal asynchronous transceiver is checked at regular intervals, and the subsequent data reception processing is performed on the condition that the width of the received pulse is determined to be between a predetermined upper limit value and lower limit value based on the received data. A pulse signal receiving device characterized by performing the following.
JP2210587U 1987-02-19 1987-02-19 Pending JPS63131434U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2210587U JPS63131434U (en) 1987-02-19 1987-02-19

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2210587U JPS63131434U (en) 1987-02-19 1987-02-19

Publications (1)

Publication Number Publication Date
JPS63131434U true JPS63131434U (en) 1988-08-29

Family

ID=30819172

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2210587U Pending JPS63131434U (en) 1987-02-19 1987-02-19

Country Status (1)

Country Link
JP (1) JPS63131434U (en)

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