JPS63129326U - - Google Patents

Description

[Brief explanation of the drawing]

Fig. 1 is a circuit block diagram of a preset receiver according to an embodiment of the present invention, Fig. 2 is a timing chart explaining the preset tuning operation of the preset receiver of Fig. 1, and Fig. 3 is a circuit diagram of the preset receiver of Fig. 1. FIG. 2 is a timing chart explaining the preset operation of the machine. 1... Local oscillation circuit (PLL), 2... Programmable frequency divider, 3... Frequency division ratio setting means, 4...
Preset memory, OS1... one-shot multivibrator (timer means), AN ₁ , AN
₂ ...AND gate (detection means).

Claims (1)

[Scope of utility model registration request] The local oscillator circuit is constituted by a PLL, and includes a frequency division ratio setting means for setting a frequency division ratio to a programmable frequency divider constituting the PLL, a preset key, and a preset key provided corresponding to the preset key for setting reception frequency information of a broadcasting station. In a preset receiver equipped with a preset memory for storing, a timer means that is activated for a certain period of time from the operation of the preset key;
When the operation of the preset key is released, a detection means for detecting a coincidence between the operating state and the non-operation state of the timer means, and a first output of the detection means sets the receiving frequency information of the preset memory to the frequency division ratio setting. 1. A preset receiver, characterized in that the preset receiver is configured to supply a write signal to the preset memory at a second output.