JPS63127352A - Common bus transfer control system - Google Patents

Abstract

PURPOSE:To contrive to attain high speed data transfer processing by comparing an address stored in an address buffer with an address of a request data and transferring its data to a data transfer request input/output controller so as to update an operation history in case of dissidence. CONSTITUTION:A channel controller 3 compares 9 an address stored in an address buffer 7 with a memory address of a request data with respect to a data transfer request from an input/output controller 6. As a result, the operation history of an area of a data buffer 8 corresponding to the address being the result of comparison coincidence is updated into the newest information, the data is read and transferred to the input/output device 6 requesting the transfer via a common bus 5. In case of comparison dissidence, the controller 3 applies request of use of a memory bus 4 to the CPU 1 and monopolizes, the memory bus 4 to access the memory 2. Then the memory address is written in the area of the buffer 7 corresponding to the area written in the buffer 8 to update the operation history for an operation history control section 10 corresponding to the area into the newest using history.

Description

[Detailed Description of the Invention] [Summary] A channel control device is provided with a data buffer that stores a plurality of data read from a memory, and in response to a data transfer request from an input/output control device, when the data exists in the data buffer, transfers the data from the data buffer to the input/output control device via the common bus without accessing the memory, reducing the number of memory accesses, speeding up common bus transfer, and making effective use of the memory bus. The aim is to

[Industrial application field]

The present invention provides a system in which a central processing unit, a memory, and a channel control device are connected via a memory bus, and the channel control device and a plurality of input/output control devices are connected via a common bus. The present invention relates to a common bus transfer control method for transferring data to an input/output control device that requests data transfer via a bus.

In various data processing systems, a central processing unit, memory, and channel control device are connected via a memory bus, and a plurality of input/output control devices are connected to the channel control device via a common bus. It has a configuration in which various input/output devices such as magnetic disk drives, printers, and display devices are connected to the input/output control unit, and the central processing unit accesses the memory via the memory bus to process data. For example, the channel control device performs advance reading, stores the data read from memory in a buffer, and performs input/output control. In response to a data transfer request from the III device, the data is transferred via the common bus. In this case, it is desired to effectively utilize the memory bus to improve the processing capacity of the central processing unit.

[Conventional technology]

For example, as shown in FIG. 4, a conventional data processing system includes a central processing unit (CC) 21 and a memory (MM).
22 and a channel control device (CHC) 23 are connected via a memory bus 24, and a plurality of input/output control devices (IOC) 26 are connected via a common bus 25 to the channel control device 23.
is connected, and the channel control device 23 is provided with a buffer (BF) 27 for one data. Further, various input/output devices (not shown) such as a magnetic disk device, a printer, and a display device are connected to the input/output control device 26.

The channel control device 23 acquires the right to use the memory bus 24, accesses the memory 22, temporarily stores the read data in the buffer 27, and releases the exclusive memory bus 24. Then, data is transferred from the buffer 27 to the data transfer request input/output control device 26 via the common bus 25.

In order to improve processing performance, if the central processing unit 21 is a 32-bit processor, the memory bus 24 connected to the memory 22 will have a width of 32 bits. In addition, the input/output control unit 26 does not require as much processing power as the central processing unit 21, so if a 16-bit processor is used,
The common bus 25 has a width of 16 bits, and the 32-bit data read from the memory 22 is transferred to the buffer 27.
The upper 16 bits or lower 16 bits of the 32-bit data are selected in response to a data transfer request from the input/output control unit 26 and sent from the buffer 27 to the common bus 25.

In addition, the channel control device 23 has a function of pre-reading instructions, and reads in advance the instruction stored at the address next to the address of the memory 22 where the instruction requested by the human output control device 26 is stored, and stores it in the buffer. By storing it in memory, the channel control device 23 and the input/output control device 2
This speeds up the data transfer between 6 and 6.

[Problem that the invention seeks to solve]

When data transfer requests from a single input/output control device 26 are continuously applied to the channel control device 23, the data generally exist at consecutive addresses in many cases. For example, 3 read from memory 22
Part of the 2-bit data is stored in the buffer 27, the upper 16 bits are sent to the common bus 25 by the first data transfer request, and the lower 16 bits are sent to the common bus 25 by the second data transfer request. In many cases, you can get away with it. In such a case, only one memory access is required for two data transfer requests from the input/output key control device.

On the other hand, when multiple input/output control devices make data transfer requests alternately, the data requested by each device almost never exists in consecutive addresses, and therefore the memory 22 is accessed for each data transfer request. and read out 32
The bit data is transferred to the buffer 27 via the memory bus 24.
The upper 16 bits or the lower 16 bits are sent to the common bus 25 in accordance with a data transfer request. In this way, since the channel control device 23 monopolizes the memory bus 24 for each data transfer request, the time that the central processing unit 21 monopolizes the memory bus 24 becomes shorter, which may reduce processing performance. These problems also occur when the channel control device 23 performs advance reading of instructions.

An object of the present invention is to shorten the time that a channel control device occupies a memory bus, improve the processing capacity of a central processing unit, and improve the transfer speed of the common bus 25.

[Means for solving problems]

The common bus transfer control method of the present invention is to deal with data transfer requests from a plurality of input/output control devices by providing a data buffer that can store a plurality of data in a channel control device. explain.

A processor (CC) 1, a memory (MM) 2, and a channel control device (CHC) 3 are connected via a memory bus 4, and the channel control device 3 is an input/output control device (IOC).
The channel control unit W3 is connected to a plurality of channels via a common bus 5 having a bus width narrower than the bus width of the memory bus 4, for example 32 bits, for example 16 bits. In this method, an input/output control device 6 is connected to the channel control device 3, and data read from the memory 2 is transferred from the channel control device 3 to the input/output control device 6 via the common bus 5. An address buffer (ADB) 7 and a data buffer (DB) 8 each having a plurality of areas for storing access addresses and read data in correspondence with each other, a comparison unit 9 that performs address comparison, and a usage history of the data buffer 8 are recorded. A usage history control unit IO is provided.

The channel control device 3 compares the address of the request data from the input/output control device 6 with the address stored in the address buffer 7 using the comparison section 9, and if the comparison matches,
The usage history corresponding to the comparison matching address is updated to the latest usage, and data from the corresponding area of the data buffer 8 is transferred to the data transfer request input/output control device via the common bus 5. If the comparison does not match, read the data from the memory 2 according to the address of the data transfer request, write the data to, for example, the oldest used area of the data buffer 8 indicated by the usage history control unit 10, and transfer the data to the common bus. 5, the data transfer request is transferred to the input/output control device, and the usage history of the usage history control unit 10, which was the oldest usage, is updated to the latest usage.

[Effect]

Data read from the memory 2 in response to a data transfer request from the input/output control device 6 and its address are stored in a data buffer 8 and an address buffer 7 in the channel control device 3 in correspondence with each other. Further, the usage history control unit 10 stores the usage history of the area of the data buffer 8 corresponding to the address buffer 7, and when data is read from the memory 2, it is read out according to the usage history of the area of the data buffer 8. It is used to write data, for example, to control the data to be written in the oldest used area. Then, that area is updated to the most recently used area, the most recently used area is updated to the second most recently used area, and so on.

In response to a data transfer request from the input/output control device 6, the comparator 9 compares the address with the address stored in the address buffer 7, and if they match, the requested data is transferred to the data buffer 8. Therefore, without accessing the memory 2, the corresponding usage history is updated to the latest usage, and the data is immediately read from the data buffer 8 and sent to the common bus 5.

If the address comparison results in a mismatch, the requested data does not exist in the data buffer 8, so the memory 2 is accessed and the data is read out. This data is written to the data buffer 8 under the control of the usage history control unit 10,
The corresponding address is written to address buffer 7. Also, the usage history of the area of the data buffer 8 is updated. For example, items with the oldest usage history are discarded in order,
The read data is written into that area.

〔Example〕

Embodiments of the present invention will be described in detail below with reference to the drawings.

FIG. 1 is a block diagram of an embodiment of the present invention, where l is a central processing unit (CC), 2 is a memory (MM), 3 is a channel control unit (CHC), 4 is a memory bus, 5 is a common bus, 6 is an input/output control device (10C), 7 is an address buffer (ADB), 8 is a data buffer (DB),
9 is a comparison section, and 10 is a usage history control section.

The memory bus 4 that connects the central processing unit 1, memory 2, and channel control device 3 has a width of 32 bits, for example.
The common bus 5 connecting the channel control device 3 and the plurality of human output control devices 6 has a width of, for example, 16 bits. Each input/output control device 6 includes a magnetic disk device (not shown),
Various input/output devices such as printers and display devices are connected.

Is there an area in the channel control device 3 to store an address for accessing the memory 2 in response to a request from the input/output control device 6 in correspondence with data read from that address?
An address buffer 7 and a data buffer 8 each having one number are provided, and the address in this address buffer 7 and
A comparison section 9 that compares the address requested by the input/output control device 6, and a usage history control section 10 that stores the usage history of each area of the data buffer 8 and controls the data buffer 8 according to the record are provided.

In response to a data transfer request from the input/output control device 6, the channel control device 3 compares the address stored in the address buffer 7 with the memory address of the requested data in the comparator 9. If the comparison fails, it indicates that the requested data is stored in the data buffer 8. Therefore, the usage history of the area of the data buffer 8 corresponding to the address that matched the comparison is updated to the latest usage, and the data is read and stored. The data is transferred to the data transfer request input/output control device 6 via the common bus 5. Therefore, without accessing memory 2,
Since the data read from the data buffer 8 can be transferred, the memory bus 4 does not need to be used.

If the comparison does not match, this indicates that the requested data is not stored in the data buffer 8, so the channel control device 3 requests the central processing unit 1 to use the memory bus 4 and uses the memory bus 4 exclusively. to access memory 2. The data thus read is stored in the usage history control unit 1.
The data is written to, for example, the oldest used area of the data buffer 8 indicated by 0, and the data is transferred to the data transfer request input/output control device 6 via the common lot 5. Then, the memory address is written to the area of the address buffer 7 corresponding to the area written to the data buffer 8, and the usage history control unit 1
Update the usage history corresponding to area 0 to the latest usage.

FIG. 2 is an explanatory diagram of the operation of the embodiment of the present invention, in which the memory 2
A total of 32 bits of data, consisting of the upper 16 bits of data Dia and the lower 16 bits of data Dib, is stored in the address Ai (+=1.2, 3, . . . ) of the area # of the address buffer 7. 1. #2.・
...#m has addresses A I and A 4. A
2. ...Ak 4.1h, data corresponding to the address Dla, Dlb, ...Dka, Dkb
is stored in the data buffer 8, a data transfer request is applied from the input/output control device 6 to the channel control device 3, and the address of the requested data is as shown by the solid line frame.
Alb (Alb indicates that the lower 16 bits of data Dlb of the data at memory address A1 is requested;
When b (or a) of b (or Ala) indicates the lower (or higher) of the 32-bit data, the comparator 9 compares the address At with the exception of the lowest bit bit b. The address stored in address buffer 7 is compared.

In this case, since it matches the address A1 stored in the #1 area of the address buffer 7, the comparator 9 updates the usage history corresponding to the #l area of this address buffer 7 to the latest usage, and stores the address in the #1 area. #1 of the corresponding data buffer 8
The lower 16 bits of data Dlb indicated by the least significant bit b of the address are read from the area and transferred to the data transfer request input/output controller 6 via the common bus 5 as shown by the solid line. Therefore, without using memory bus 4,
Data can be immediately transferred to the input/output control device 6 that has received a data transfer request.

Further, when a data transfer request is applied to the channel control device 3 from another input/output control device 6 and the address of the requested data is A3a as shown by the dotted line frame, the comparator 9 transfers this request as in the case described above. A3 of the addresses A3a and the address stored in the address buffer 7 are compared. In this case, if a matching address is not stored, the memory bus 4 is occupied and the memory 2
The data D3a and D3b are read from the address A3 of the address A3, and the data D3a and D3b are written to the oldest used area of the data buffer 8 by the usage history control unit 10.
Corresponding to a of 3a, the upper 16 bits of data D3a are transferred to the data transfer request input/output control device 6 via the common bus 5, as shown by the dotted line.

In this case, assuming that the oldest used area is #2, the currently read data D3a and D3b are written to the area where data D4a and D4b were stored, and the #2 area of address buffer 7 is written to the area where data D4a and D4b were stored. Address A3 is written. Also, the oldest usage history in area #2 of the usage history control unit 10 is updated to the latest usage history.

In this way, after the human output control device 6 requests the data D3a of the upper 16 bits, and then another input/output control device requests other data, the previous input/output control device 6 again requests the data at consecutive addresses. As, lower 16 bit data D3b
In this case, since the lower 16 bits of data D3b are stored in the data buffer 8, the data D3b is immediately sent via the common bus 5 without accessing the memory 2. can be transferred.

FIG. 3 is an explanatory diagram of the operation of the usage history control unit. When the buffer areas are #1 to #5, it is composed of five stages of shift registers L1 to L5 corresponding to each area, and the usage history is “1”. ”
It is expressed by the shift position of , and the first stage "l" is the latest used (1)
, the "1" in the fifth row is the oldest used (5).

(a) is an example of an initial state, in which data is sequentially written from buffer area #1 to buffer area #5.

That is, "l" is sequentially shifted to the shift register corresponding to the used buffer area, and as a usage history, buffer area #1 becomes the oldest used (5) and buffer area #5 becomes the latest used (1). Indicates when

(In the state of al, the oldest used area (5) is used, but if another area, for example buffer area #3, is used, shift "1" indicating use to #3) In addition to adding it to the register, "1" is shifted to the third stage L3 of the shift register corresponding to #3, so the shift range of each shift register is 1 bit shifted up to the third stage L3 where this "1" exists. As a result, the state shown in (b) is reached, the usage history of #1 and #2 remains unchanged, #3 is updated from (3) to the latest usage (1), and #4 and #5 are The usage history is updated from (2) to (3) and from (1) to (2).

In state (b), if the oldest used buffer area #1 (5) is used, or if a new address is added to the buffer, "l" is placed in the fifth stage of the shift register corresponding to #l.
” exists, the shift range is up to the 5th gear, and (
Shifted by 1 bit from the state in b), (C)
The state shown in is reached. Therefore, buffer area #1 is the most recently used (1), and buffer area #2 is the oldest used (5).

Buffer usage history control can be realized by other means, but in this embodiment, the usage history of the buffer area can be recorded by shift control of the shift register corresponding to the buffer area, Latest use (1
) and oldest used (5) can be easily determined based on the "1" position of the shift register, making it possible to record usage history and speed up buffer control.

Further, the widths of the memory lotus 4 and the common bus 5 are not limited to those of the above-described embodiments, and various combinations can be adopted depending on the system.

〔Effect of the invention〕

As explained above, in the present invention, the channel control device 3 and the plurality of input/output control devices 6 are connected via the common bus 5, and the data transfer request from the input/output control device 6 or the channel control device 3 is When the input/output control device 6 has a function of pre-reading the requested instruction from the memory 2, the address stored in the address buffer 7 and the address of the requested data are compared in the comparison section 9, and if they match, the , updates the usage history of the corresponding usage history control unit 10, and transfers the data stored in the data buffer 8 to the data transfer request input/output control device 6 via the common bus 5. If the comparison does not match, the memory 2 is accessed to read the data, the data is stored in the data buffer 8, the address is stored in the address buffer 7, and the data is sent to the data transfer request input/output control device 6. common bus 5
is used to update the usage history in the usage history control unit 10, and when there are alternate data transfer requests from multiple input/output control devices, the data stored in the data buffer 8 Since there are relatively many requests for this, the channel control device 3 uses the memory bus 4 less frequently, which has the advantage of improving the processing speed of the central processing unit 1. Further, when the requested data exists in the data buffer 8, there is an advantage that the data transfer processing speed is increased.

[Brief explanation of the drawing]

Fig. 1 is a block diagram of the embodiment of the present invention, Fig. 2 is an explanatory diagram of the operation of the embodiment of the present invention, Fig. 3 is an explanatory diagram of the operation of the usage history control section, and Fig. 4 is an explanatory diagram of the conventional example. It is. ■ is the central processing unit (CC), 2 is the memory (MM), 3
is a channel control unit (CHC), 4 is a memory bus, 5 is a
is a common bus, 6 is an input/output controller (IOC), 7 is an address buffer (ADB), and 8 is a data buffer (
DB), 9 is a comparison section, and 10 is a usage history control section.

Claims (1)

[Claims] A processor (1), a memory (2), and a channel control device (
3) are connected via a memory bus (4), a plurality of input/output control devices (6) are connected to the channel control device (3) via a common bus (5), and a plurality of input/output control devices (6) are connected to the channel control device (3) via a common bus (5). In the common bus transfer control method of transferring data from the channel control device (3) to the input/output control device (6) via the common bus (5), the channel control device (3) , an address buffer (7) and a data buffer (8) that store the access address of the memory (2) and read data in correspondence, respectively.
), a comparison unit (9) that performs address comparison, and a usage history control unit (
10), and the channel control device (3) is connected to the input/output control device (6).
) and the address stored in the address buffer (7).
), and if the comparison matches, the usage history of the usage history control unit (10) corresponding to the comparison matching address is updated, and the data in the data buffer (8) is transferred via the common bus (5). and transfers the data transfer request to the input/output control unit (6), and if the comparison does not match, reads the data from the memory (2) according to the address of the data transfer request, and transfers the data to the usage history control unit (10). writes the data into the data buffer (8) under the control of the data transfer request input/output control device (6) via the common bus (5), and records the usage history of the usage history control unit (10). A common bus transfer control method characterized by updating.