JPS63125444U - - Google Patents
Info
- Publication number
- JPS63125444U JPS63125444U JP1987015249U JP1524987U JPS63125444U JP S63125444 U JPS63125444 U JP S63125444U JP 1987015249 U JP1987015249 U JP 1987015249U JP 1524987 U JP1524987 U JP 1524987U JP S63125444 U JPS63125444 U JP S63125444U
- Authority
- JP
- Japan
- Prior art keywords
- clock
- input signal
- counter
- point
- multiphase
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000001514 detection method Methods 0.000 claims description 3
- 230000010355 oscillation Effects 0.000 claims 1
- 230000001360 synchronised effect Effects 0.000 claims 1
- 238000010586 diagram Methods 0.000 description 2
- 238000007493 shaping process Methods 0.000 description 1
Landscapes
- Pulse Circuits (AREA)
- Manipulation Of Pulses (AREA)
- Synchronisation In Digital Transmission Systems (AREA)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1987015249U JPH0631795Y2 (ja) | 1987-02-03 | 1987-02-03 | デイジタル信号同期回路 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1987015249U JPH0631795Y2 (ja) | 1987-02-03 | 1987-02-03 | デイジタル信号同期回路 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS63125444U true JPS63125444U (OSRAM) | 1988-08-16 |
| JPH0631795Y2 JPH0631795Y2 (ja) | 1994-08-22 |
Family
ID=30806007
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1987015249U Expired - Lifetime JPH0631795Y2 (ja) | 1987-02-03 | 1987-02-03 | デイジタル信号同期回路 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0631795Y2 (OSRAM) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2011199792A (ja) * | 2010-03-24 | 2011-10-06 | Meidensha Corp | Ｄｐｌｌ回路 |
-
1987
- 1987-02-03 JP JP1987015249U patent/JPH0631795Y2/ja not_active Expired - Lifetime
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2011199792A (ja) * | 2010-03-24 | 2011-10-06 | Meidensha Corp | Ｄｐｌｌ回路 |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0631795Y2 (ja) | 1994-08-22 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| JPH0467372B2 (OSRAM) | ||
| JPS63125444U (OSRAM) | ||
| JPS6036922Y2 (ja) | 垂直同期信号検出回路 | |
| JP2600668B2 (ja) | クロツク再生回路 | |
| JPS6412691A (en) | Video signal sampling circuit | |
| JPH0170483U (OSRAM) | ||
| JPS6281177A (ja) | 同期制御回路 | |
| JP2508863B2 (ja) | ペデスタルクランプ回路 | |
| JPH01103975U (OSRAM) | ||
| JP3398393B2 (ja) | Ｐｌｌ回路および信号処理装置 | |
| JPH0734540Y2 (ja) | 発振停止回路付デジタル・オ−ディオ・インタ−フェ−ス回路 | |
| JPS62186533U (OSRAM) | ||
| JPH0632165B2 (ja) | ピツチコントロ−ル装置 | |
| JPS6421586U (OSRAM) | ||
| JPS6150346U (OSRAM) | ||
| JPS63196124U (OSRAM) | ||
| JPS61195644U (OSRAM) | ||
| JPH0412763U (OSRAM) | ||
| JPH0290586U (OSRAM) | ||
| JPS6221663U (OSRAM) | ||
| JPH0348982U (OSRAM) | ||
| JPH03117945U (OSRAM) | ||
| JPH05300470A (ja) | クロック信号生成回路 | |
| JPS63125471U (OSRAM) | ||
| JPS62125029U (OSRAM) |