JPS63124560A - Semiconductor device - Google Patents

Abstract

PURPOSE:To prevent deterioration in characteristics, by providing a oneconductivity type high concentration impurity layer in an epitaxial layer beneath a gate electrode so that the upper end part is positioned in the vicinity of a drain region and the lower end part is connected to a one-conductivity type semiconductor substrate, absorbing a current at the substrate, which is generated in the vicinity of the drain due to impact ions, and making the current to flow to the substrate side. CONSTITUTION:A P<+> type layer 104 is provided in a P-type epitaxial layer 102 beneath a gate electrode 109A so that the upper end part is positioned in the vicinity of an N-type drain region 115 and the lower end part is connected to a P<+> type semiconductor substrate 101. Therefore, a current in a substrate, which is generated in the vicinity of the drain due to impact ions, is absorbed in the P<+> type layer 104 and taken into the low resistance region of the substrate. The increase in potential in the vicinity of a source is suppressed. Thus the gate current of a transistor is suppressed, and the deterioration in characteristics of the transistor can be prevented.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor device, and particularly to an MO3 type semiconductor device.

[Conventional technology]

Conventionally, MOS semiconductor devices have been designed with shorter channels and higher density. However, as the channel becomes shorter, the electric field between the source and drain becomes stronger, and a substrate current is generated due to the impact ionization phenomenon caused by the collision of electrons near the drain, which further increases the potential near the source. is amplified and a large amount of current flows.

On the other hand, at this time, the gate current also flows, and electrons are captured in the gate insulating film, causing a change in the threshold voltage of the MOS semiconductor device, changing the conductivity of the MOS semiconductor device, making the operation unstable, and reducing the operation speed. This will cause it to deteriorate.

Furthermore, in recent years, CMO8 semiconductor devices have been used in a wide range of fields due to their reduced power consumption and wide operating range.

However, since two different transistors, a P-channel type and an N-channel type, are provided in one substrate, it is known that the interaction between these two transistors causes a unique problem called the so-called latch-up phenomenon. It is being

To cope with these problems, a transistor having a structure shown in FIG. 4 is known.

In FIG. 4, an N-type well 106 and a P-type well 120 are formed in a P-type semiconductor substrate 101A.
A P-channel transistor and an N-channel transistor separated by a field insulating film 107 are formed in each well.

Then, a gate electrode 112 on the N-channel side and a gate electrode 109 on the P-channel side are formed on the gate insulating wA 108, and sources and drains are formed in the wells on both sides thereof. A P-type source region 110 and a P-type drain region 111 on the P-channel side are formed as diffusion layers.

On the other hand, the drain on the N channel side is the N++ source region 11
It has a double structure of an N+ type drain region 114 and an N type drain region 115, which have a high concentration similar to No. 3. The N+ type drain region 114 is formed at a certain distance from the gate electrode 112.

In a CMOS semiconductor device with such a structure, since a part of the drain of the N-channel transistor is formed of an N-type diffusion layer, the electric field strength near the drain is relaxed, and the injected into the gate insulating film is Deterioration is suppressed because fewer electrons are used. Since the P-type well 120 having a higher impurity concentration than the substrate is formed, it is possible to increase the substrate current until the potential near the source is raised.

[Problem that the invention seeks to solve]

However, in the conventional CMOS semiconductor device mentioned above,
By increasing the concentration of the P-type well 120, it is possible to further prevent deterioration of the characteristics, but increasing the well concentration causes a change in the extension of the depletion layer from the diffusion layer near the drain. , it becomes impossible to weaken the electric field strength. Further, since the well concentration is high, the capacitance of the source/drain diffusion layer becomes large, and furthermore, the mobility of the N-channel transistor is reduced, and the conductivity is deteriorated, which hinders high-speed operation.

In addition, increasing the concentration of the P-type well 120 is well known as an effect of suppressing the latch-up phenomenon described above, but simply increasing the concentration of the P-type well 120 does not have a sufficient effect. Since the location of the junction with the grounded P-type well potential must be appropriately selected, the degree of freedom in wiring design is hindered, and there is also the problem that higher density is hindered.

An object of the present invention is to provide a semiconductor device that eliminates the above-mentioned problems and prevents characteristic deterioration.

[Means for solving problems]

The semiconductor device of the present invention includes a low concentration epitaxial layer of one conductivity type provided on a semiconductor substrate of high concentration of - conductivity type, a source region and a drain region of opposite conductivity type formed on the surface of this epitaxial layer, and the source region of the opposite conductivity type formed on the surface of the epitaxial layer. a gate electrode formed between the region and the drain region via a gate oxide film;
A high concentration impurity layer of one conductivity type is formed in the epitaxial layer under the gate electrode, and has an upper end located near the drain region and a lower end connected to the surface of the semiconductor substrate.

〔Example〕

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a sectional view of one embodiment of the present invention, and the present invention is shown in FIG.
In Figure 1, which shows a case where it is applied to a MOS semiconductor device, a P type epitaxial layer 102 is provided on a P+ type semiconductor substrate 101, and a layer for element isolation is provided on this P type epitaxial layer N102. A field insulating film 107 is formed, and an N-type well 106 and a P+-type channel stopper 10 are formed in the P-type epitaxial layer 102.
3.105 is formed. A P-type source region 110 . is formed in this N-type well 106 . A P-channel transistor is provided that includes a P-type drain region 111 and a gate electrode 109 formed with a gate insulating film 108 interposed therebetween.

On the other hand, the N channel transistor includes an N+ type source region 113 formed in the P type epitaxial layer 102, an N
The gate electrode 10 is formed through the type drain region 115, the N+ type drain region 114, and the gate insulating film 108.
It consists of 9A. The drain structure of this N-channel transistor is the one commonly used in the past.
The N type drain region 115 is intended to alleviate the concentration of electric field near the drain, and is intended to reduce the resistance of the N+ type drain region 114 and the drain diffusion layer as much as possible.

In particular, the P type epitaxial layer 102 under the gate electrode 109A has an upper end located near the N type drain region 115 and a lower end located in the P" type semiconductor substrate 102.
A P+ type layer 104 is provided which connects to 1.

In this embodiment configured in this way, the substrate current due to impact ionization occurring near the drain is absorbed by this P+ type layer 104 and drawn into the low resistance region of the substrate, and the current near the source is Increase in potential is suppressed. Therefore, the gate current of the transistor is suppressed, and deterioration of the characteristics of the transistor can be prevented.

Since this P+ type layer 104 is not in contact with the drain and does not reach the interface of the gate insulating film 108, the electrical capacity of the drain diffusion layer becomes small, and the impurity concentration at the interface is lower than that of the epitaxial layer. Since the conductivity of the transistor is low, high-speed operation can be expected.

Further, P1 type channel stoppers 103 and 105 are formed across the interface of the field insulating film 107 and the P+ type semiconductor substrate 101. At this time, the field insulating film 10
7 forms an oxidation-resistant film in the active region of the transistor, oxidizes the epitaxial layer, and embeds it in the substrate.

Since it is formed by a so-called selective oxidation method, the gate insulation 11
It is necessary to have a structure in which the interface of the field insulating film 107 is buried from the interface between the 5T 108 and the P-type epitaxial layer 102, and the diffusion layer is formed shallowly, and the depth of the field insulating film 107 under the interface is Min is P1 type layer 10
It will be at the top of 4.

Providing the P1 type channel stoppers 103 and 105 below the field insulating film 107 has the effect of suppressing the latch-up phenomenon by absorbing the flow of floating charges and taking them to the substrate. In addition, since the P+ type channel stoppers 103 and 105 are selectively formed, contact with the diffusion layers forming the source/drain regions can be suppressed as much as possible, which reduces electrical capacitance and enables high-speed operation. It becomes possible. When the channel is further shortened and the deterioration effect increases, this P+ type channel stopper 1
By adjusting the position and concentration of 03.105, latch-up can be further suppressed.

In the above example, it was shown that the effects of CMO3 semiconductor devices are diverse, but single channel MO3 semiconductor devices have various effects.
It goes without saying that the present invention has a major effect on semiconductor devices as well, and this effect can be particularly effectively exhibited in N-channel MOS transistors.

Next, the manufacturing method of the above embodiment will be explained with reference to FIGS. 2(a) to 2(e).

First, as shown in FIG. 2(a), a P-type epitaxial layer 102 is formed on a P+-type silicon substrate 101. Next, in order to form a P1-type layer, the surface of the P-type epitaxial layer 102 is selectively formed. A pattern is formed using an oxide film or photoresist, and high-energy ion implantation is performed to form P1 type layers 103A, 104A, and 105A at relatively deep positions. N-type impurity ions are implanted into a region where a type well is to be formed to form an N-type layer 106A.

Next, as shown in FIG. 2(b), heat treatment is performed to form P+ type layers 103A and 104A.

P+ type layer 104 and P+ type channel stopper 1 connected to the surface of P+ type semiconductor substrate 101 by diffusing 105A.
03°, 105 is formed. However, the upper ends of these P+ type layers must be formed at a certain distance from the surface of the P type epitaxial layer 102. On the other hand, the N-type layer 106A forms the N-type well 106 by heat treatment, but this must be formed so as to reach the surface of the P-type epitaxial layer 102. However, the bottom of the N-type well 106 does not necessarily have to reach the P+-type semiconductor substrate 101.

Next, as shown in FIG. 2(c), an oxidation-resistant film is selectively formed on the surface of the P-type epitaxial layer 102, and the field insulating film 109 is formed by oxidizing the epitaxial layer using this film as a mask. The active region and the field insulating film region are separated. At this time, P+ type channel stopper 10
3. The upper end of the film 105 is formed so as to be in contact with the bottom of the field insulating film 107. Thereafter, a gate insulating film 108 is formed in the active region, and gate electrodes 109 and 109A are formed, for example, by doping polycrystalline silicon with impurities. and,
Using photoresist 211 as a mask, N-type impurities are introduced into a predetermined drain region by, for example, ion implantation, and an appropriate heat treatment is performed to form N-type drain region 115.

Next, as shown in FIG. 2(d), Photoregis)-21
At 1A, a part of the gate electrode 109A and the N-type drain region 1
15, covering a part of the gate electrode side and the P channel side,
For example, an N type impurity 3 such as arsenic is ion-implanted at a high concentration to form a low resistance N+ type drain region 114.

Next, as shown in FIG. 2(e), using a photoresist as a mask in the same way as the N-channel side, a P-type impurity such as boron is ion-implanted into the P-channel side to form a P-channel transistor. A type source region 110 and a P type drain region 111 are formed. Next, a glabellar insulating film 216 is formed, a contact hole is formed at a predetermined position, and a metal wiring 217 is formed to complete the CMO8 semiconductor device component. .

In the manufacturing method shown in FIGS. 2(a) to 2(e), the P+ type layer 104 is formed by ion implantation, but it can also be formed by another manufacturing method. This will be explained below according to FIG.

First, as shown in FIG. 3(a), a P-type epitaxial layer 102 is formed on a P+-type semiconductor substrate 101 in the same manner as shown in FIG.
ff1121 is provided at a predetermined position where 5A is to be formed.

Next, as shown in FIG. 3(b), a P1 type epitaxial layer 303 is formed on the entire surface including 71$121.

Next, as shown in FIG. 3(c), the P+ type epitaxial layer 303 is etched away from the surface to form P+ type layers 130A and 104A in 1121.

105A is formed.

Next, as shown in FIG. 3(d>), when the P-type epitaxial layer 102 is further grown, the buried layer formed in the previous step grows, forming a slightly larger buried P+ type layer 103.
A, 104A, and 105A. After that, using the oxide film 204 and photoresist 1~ as a mask on the surface, the N-type layer 106Af
! - Formed by ion implantation to form an N well. Thereafter, a CMO3 semiconductor device is completed by the steps shown in FIGS. 2(b) to 2(e).

〔Effect of the invention〕

As explained above, the present invention provides a high concentration impurity layer of one conductivity type in the epitaxial layer under the gate electrode, the upper end of which is located near the drain region, and the lower end of which is connected to the semiconductor substrate of one conductivity type. Impacts that occurred nearby
By absorbing the substrate current caused by ionization and flowing it to the substrate side, it prevents electrons from being captured in the gate insulating film, and also has the effect of suppressing the latch-up phenomenon that is unique to CMO3 semiconductor devices. be. In addition, the electrical capacitance of the diffusion layer forming the source and drain can be reduced, and high-speed operation can be achieved without impairing the conductivity of the transistor.

[Brief explanation of the drawing]

FIG. 1 is a sectional view of an embodiment of the present invention, and FIGS. 2(a) to (
e) and FIGS. 3(a) to 3(d) are cross-sectional views of a semiconductor chip shown in order of steps to explain the manufacturing method of an embodiment of the structure of the present invention, and FIG. 4 is an example of a conventional semiconductor device. FIG. 101...N++ semiconductor substrate, 102...N type epitaxial layer, 103.105...P1 type channel stopper, 104...P+ type layer, 106...N type well, 107...Field insulation Film, 108... Gate insulating film, 109, 109A... Gate electrode, 110
...P type source region, 111...P type drain region, 113...N++ source region, 114...N+ type tray region 115...N type drain region, 120
...P-type well, 121...groove, 204...oxide film, 211.211A...photoresist, 216...
・Interlayer insulating film: 217...metal wiring, 303...P
+ type epitaxial layer. rot: F"!+-foQ, fol? A: Keto Denryuman 1st ward 4th figure 2' ward A 2'th figure

Claims (1)

[Claims] A low concentration epitaxial layer of one conductivity type provided on a high concentration semiconductor substrate of one conductivity type, a source region and a drain region of opposite conductivity type formed on the surface of the epitaxial layer, and a region between the source region and the drain region. A gate electrode formed through a gate oxide film, and a conductive layer formed in the epitaxial layer below the gate electrode, whose upper end is located near the drain region and whose lower end is connected to the surface of the semiconductor substrate. 1. A semiconductor device comprising: a high-concentration impurity layer.