JPS6312390B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention provides MNOS (metal-nitride film-oxide)
The present invention relates to a method for manufacturing a semiconductor device having a semiconductor structure.

A MOS type semiconductor device having an MNOS structure with a dense nitride film (Si ₃ N ₄ film) is, for example, a MOS
It is often used in type semiconductor ROM devices.
It is well known that the MNOS structure is more resistant to contamination than the general MOS structure, and has higher circuit reliability.

Furthermore, in the manufacturing of integrated circuits, it is well known that the interface between the semiconductor substrate and the gate oxide film in the gate region is damaged during the vapor deposition process of electrode wiring metal, but generally, the interface between the semiconductor substrate and the gate _oxide film in the gate region is damaged. It is also well known that damage can be recovered by annealing.

In an integrated circuit having an MNOS structure covered with the Si ₃ N ₄ film, the Si ₃ N ₄ film also blocks the penetration of H ₂ , making it difficult to recover from damage to the MOS transistor.

However, since H ₂ enters through the contact hole without a Si ₃ N ₄ film, the MOS transistor near the contact hole recovers from damage, but the MOS transistor far away from the contact hole, for example in the ROM part, In an integrated circuit with an MNOS structure, which has no contact hole and is covered with a Si ₃ N ₄ film over a considerable area, the gate (MOS transistor) located at a distance of 0.1 to 0.2 mm or more from the contact hole is exposed to H ₂ . The damage cannot be completely removed only by annealing in a containing atmosphere.

There is a drawback that a difference occurs in the gate threshold voltage V _T and mutual conductance g _n between the peripheral part of the ROM near the contact hole and the central part of the ROM away from the contact hole, resulting in a reduction in the power supply voltage margin of the integrated circuit.

This invention was made to solve the above-mentioned conventional drawbacks, and it is a ROM of an integrated circuit with an MNOS structure.
The purpose of this invention is to provide a method for manufacturing a semiconductor device that can be widely used in MOS type integrated circuits, while also aiming to improve the characteristics of semiconductor devices.

Embodiments of the method for manufacturing a semiconductor device of the present invention will be described below with reference to the drawings. 1 to 8 are process explanatory diagrams of the first embodiment of the present invention, in which an N-type silicon substrate with an MNOS structure is used.
This is a cross-sectional view of the process of a channel ROM semiconductor device, and will be explained below in order of process.

Figure 1 shows an oxide film 2 on the surface of an N-type silicon substrate 1.
A P ^- well 3 is formed by applying a photoetching technique, an ion implantation technique, a thermal diffusion technique, etc., and then a P ⁺ channel stopper region 4 shown in FIG. 2 is formed.

Next, N ⁺ source/drain regions 5 and cross-under diffusion layers 6 of the MOS transistor shown in FIG. 3 are formed in the P ^- well 3. Next, it is shown in Figure 4.
The gate oxide film 7 of the MOS transistor is replaced with the oxide film 2
is removed to form about 800 Å.

Next, using CVD technology, a Si ₃ N ₄ film 8 shown in FIG.
Å form. A contact hole 9 is made in this by photo-etching technique, and the electrode wiring metal shown in Fig. 6 is formed by sputtering and vapor deposition.
A wiring pattern 10 is formed using a photo-etching technique.

At this time, the wiring pattern 10 is drawn so as to cover the gate region and as much of the diffused resistance region as possible. This is to prevent changes in diffusion resistance due to implantation of H ions. Further, in order to prevent changes in the diffusion resistance of the P ^- well 3 and the P ⁺ channel stopper region 4, an ion implantation mask such as a resist may be used after the wiring pattern 10 is formed by photolithography.

Next, as shown in Figure 7, H ions, e.g.
H ⁺ , H ⁺ ₂ and H ⁺ ₃ ions 11 are implanted. The injection conditions are 70 to 100 Kev and 4 to 10×10 ¹⁴ IONS/cm ² .

Next, as shown in Figure 8, annealing is performed at 400°C or higher, and H ions 1
2 is applied to the interface between the silicon substrate and the gate oxide film. The annealing atmosphere at this time is dangerous _H2
Avoid using only inert gas.

Although the embodiment of the N-channel ROM has been described above, it is obvious that the present invention can be similarly applied to other semiconductor devices, such as CMOS.

As explained above, in the first embodiment
In the manufacturing process of MNOS structure ROM semiconductor devices, H ions are implanted into the entire wafer and annealed after patterning the wiring metal.
It is possible to improve the V _T and g _n values of the MOS transistor in the ROM area covered with the Si ₃ N ₄ film, make the values uniform across the entire wafer, and improve the power supply voltage margin and quality.

In the first embodiment described above, the process of directly implanting H ions into the surface of the silicon substrate after forming the wiring pattern 10 was explained, but as shown in FIG. 9, a thermal oxide film 2 is formed on the surface of the N-type silicon substrate 1. photoetching technology, ion implantation technology, thermal diffusion technology,
By applying CVD technology, P ^- well 3, P ⁺ channel stopper region 4, N ⁺ source/drain region 5,
P ^- diffused resistance region 3a, P ⁺ diffused resistance region 5a, gate oxide film 7, Si ₃ N ₄ film 8, contact hole 9
Then, an electrode wiring metal is formed to a thickness of about 1 μm by sputtering and vapor deposition, and a wiring pattern 10 is formed by photoetching.

Next, as shown in FIG. 10, P ^- well 3,
To prevent changes in the diffusion resistance of the P ⁺ channel stopper region 4, photoresist is coated.
Further, the photoresist on the upper part of the ROM is removed using a photoetching technique to form an ion implantation mask 10a.

Next, H ion 11 is 70-100Kev, 4-10×
Perform ^10-14 IONS/ ^cm2 injection. Next, as shown in FIG. 11, the photoresist is removed and annealing is performed at 400° C. or higher in an atmosphere containing H ₂ .

As described above, according to the method of manufacturing a semiconductor device of the present invention, after forming a gate oxide film and a Si ₃ N ₄ film on a semiconductor substrate, forming an electrode wiring metal and forming a predetermined wiring pattern, , H ions are implanted so that they act on the interface between the semiconductor substrate and the gate oxide film, which has the advantage of improving the characteristics and stability of the ROM section of the MNOS structure integrated circuit. As a result, it can be widely used in MOS integrated circuits with built-in large-capacity ROM, such as microcomputer clock memories.

[Brief explanation of the drawing]

1 to 8 are process sectional views of one embodiment of the semiconductor device manufacturing method of the present invention, and FIGS. 9 to 11 are process sectional views of other embodiments of the semiconductor device manufacturing method of the present invention, respectively. It is a diagram. 1...N-type silicon substrate, 2...thermal oxide film, 3...
P ^- well, 3a...P ^- diffused resistance region, 4...P ⁺ channel stopper region, 5...N ⁺ source/drain region, 5a...P ⁺ diffused resistance region, 6...N ⁺ cross-under diffusion region, 7...gate Oxide film, 8...Si ₃ N ₄
Film, 9... Contact hole, 10... Wiring pattern, 10a... Ion plateation mask, 11
...H ion, 12...H ion implantation region.

Claims (1)

[Claims] 1 A channel stopper region and a source/MOS transistor region are formed in a well formed in a semiconductor substrate.
After forming the drain region, a step of forming a gate oxide film of this MOS transistor, a step of forming a Si ₃ N ₄ film on this gate oxide film, and a step of forming an electrode wiring metal on the gate oxide film to form a gate oxide film. and a step of injecting H ions into the vicinity of the interface between the gate oxide film and the semiconductor substrate using the wiring pattern as a mask. Production method.