JPS6312384B2 - - Google Patents

Info

Publication number
JPS6312384B2
JPS6312384B2 JP57108531A JP10853182A JPS6312384B2 JP S6312384 B2 JPS6312384 B2 JP S6312384B2 JP 57108531 A JP57108531 A JP 57108531A JP 10853182 A JP10853182 A JP 10853182A JP S6312384 B2 JPS6312384 B2 JP S6312384B2
Authority
JP
Japan
Prior art keywords
heat
thermally conductive
semiconductor
semiconductor substrate
semiconductor device
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP57108531A
Other languages
Japanese (ja)
Other versions
JPS59944A (en
Inventor
Masayoshi Sasaki
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
National Institute of Advanced Industrial Science and Technology AIST
Original Assignee
Agency of Industrial Science and Technology
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Agency of Industrial Science and Technology filed Critical Agency of Industrial Science and Technology
Priority to JP57108531A priority Critical patent/JPS59944A/en
Publication of JPS59944A publication Critical patent/JPS59944A/en
Publication of JPS6312384B2 publication Critical patent/JPS6312384B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/42—Fillings or auxiliary members in containers or encapsulations selected or arranged to facilitate heating or cooling
    • H01L23/433—Auxiliary members in containers characterised by their shape, e.g. pistons
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
    • H01L2224/48464—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area also being a ball bond, i.e. ball-to-ball
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/49105—Connecting at different heights
    • H01L2224/49107—Connecting at different heights on the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/12—Passive devices, e.g. 2 terminal devices
    • H01L2924/1204—Optical Diode
    • H01L2924/12041—LED
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/1515—Shape
    • H01L2924/15153—Shape the die mounting substrate comprising a recess for hosting the device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/15165—Monolayer substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/161—Cap
    • H01L2924/1615—Shape
    • H01L2924/16195—Flat cap [not enclosing an internal cavity]

Description

【発明の詳細な説明】 （発明の技術分野） この発明は、発熱をともなう半導体素子の放熱
を有効に除去することの出来る半導体装置に関す
る。DETAILED DESCRIPTION OF THE INVENTION (Technical Field of the Invention) The present invention relates to a semiconductor device that can effectively eliminate heat radiation from a semiconductor element that is accompanied by heat generation.

（背景技術とその問題点） 第１図は放熱対策を施こした従来の半導体装置
の断面構造図である。(Background Art and Problems Therewith) FIG. 1 is a cross-sectional structural diagram of a conventional semiconductor device in which heat dissipation measures are taken.

１は半導体素子がその内部に形成された半導体
基板、２はボンデイング用ワイア、３はパツケー
ジ、４は放熱用冷却フイン（放熱器）である。半
導体基板１の表面近くの素子活性領域で発生した
熱は、半導体基板１からパツケージ３を経て冷却
フイン４に導びかれ、そこで放熱する。熱の流れ
を模式的に矢印で示す。しかし、このような従来
の半導体装置では、素子の集積度が上昇し、発熱
量が増加すると放熱効率が悪化してしまうという
欠点があつた。 1 is a semiconductor substrate with a semiconductor element formed therein, 2 is a bonding wire, 3 is a package, and 4 is a cooling fin for heat radiation (radiator). Heat generated in the element active region near the surface of the semiconductor substrate 1 is led from the semiconductor substrate 1 through the package 3 to the cooling fins 4, where it is radiated. Heat flow is schematically shown by arrows. However, such conventional semiconductor devices have a drawback in that as the degree of integration of elements increases and the amount of heat generated increases, the heat dissipation efficiency deteriorates.

（発明の目的） この発明の目的は、発熱量が増加しても効率的
に放熱を行うことの出来る半導体装置を提供する
にある。(Object of the Invention) An object of the present invention is to provide a semiconductor device that can efficiently dissipate heat even if the amount of heat generated increases.

（発明の概要） この発明では、半導体素子が形成された半導体
基板の表面に密着して形成した熱伝導層と、この
熱伝導層と放熱器とを熱伝導可能に接続する熱伝
導ワイアとを有し、前記半導体基板を単独または
複数個積層するように構成して上記目的を達成し
た。(Summary of the Invention) The present invention includes a thermally conductive layer formed in close contact with the surface of a semiconductor substrate on which a semiconductor element is formed, and a thermally conductive wire that connects the thermally conductive layer and a radiator in a thermally conductive manner. The above object has been achieved by configuring the semiconductor substrate to have one semiconductor substrate or a plurality of semiconductor substrates stacked together.

以下この発明の実施例を図面に基づいて詳細に
説明する。 Embodiments of the present invention will be described in detail below with reference to the drawings.

（発明の実施例） 第２図はこの発明の一実施例を示す半導体装置
の断面図である。なお第１図に示したと同一部分
は同一符号を付して、説明を省略する。(Embodiment of the Invention) FIG. 2 is a sectional view of a semiconductor device showing an embodiment of the invention. Note that the same parts as shown in FIG. 1 are designated by the same reference numerals, and the description thereof will be omitted.

半導体基板１の表面に密着して金属などの熱の
良導体で熱伝導層５を形成する。またこの熱伝導
層５から熱を伝導によりパツケージ３に導びくた
めに熱伝導ワイア６が用いられる。 A thermally conductive layer 5 is formed of a good thermal conductor such as metal in close contact with the surface of the semiconductor substrate 1. Further, a heat conductive wire 6 is used to conduct heat from the heat conductive layer 5 to the package 3 by conduction.

図中に矢印で示したように、半導体基板１で発
生した熱は、従来の熱伝導経路の外に熱伝導層５
から熱伝導ワイア６を経て、パツケージへと逃げ
る経路が付加されることになる。従がつて熱はよ
り効率的に外部の冷却フイン４に導びかれる。 As indicated by the arrow in the figure, the heat generated in the semiconductor substrate 1 is transferred to a heat conductive layer 5 outside of the conventional heat conduction path.
This provides an additional path for the heat to escape from the heat through the heat conduction wire 6 to the package. Heat is therefore more efficiently guided to the external cooling fins 4.

熱伝導の効率の差は半導体基板１が、SOS
（Silicon on Sapphire）などのように絶縁体で構
成されている場合にはいつそう明確になる。即
ち、半導体基板１から直接パツケージへと逃げる
経路の放熱効率は半導体基板１の熱伝導率が小さ
いので非常に小さい。 The difference in heat conduction efficiency is that semiconductor substrate 1 is
This becomes clear when the material is composed of an insulator such as (Silicon on Sapphire). That is, the heat dissipation efficiency of the path escaping directly from the semiconductor substrate 1 to the package is extremely low because the thermal conductivity of the semiconductor substrate 1 is low.

それに対し、熱伝導層５から熱伝導ワイア６を
介してパツケージ３へと逃げる経路の放熱効率は
熱伝導率が大きいので非常に大きくなる。 On the other hand, the heat dissipation efficiency of the path from the thermally conductive layer 5 to the package 3 via the thermally conductive wire 6 is very high because the thermal conductivity is high.

なお、熱伝導層５の形成にあたつて、この厚み
を薄くしすぎると熱伝導率が小さくなつて、放熱
効率が悪くなり、厚すぎると生産性が悪くなるの
で制御には気を付けなくてもならない。好ましく
は0.5〜20μｍの範囲に選択するのが良い。熱伝導
層５とパツケージ３との接続に用いられる熱伝導
ワイア６の形成には、周知のワイアボンデイング
技術を用いれば良い。ワイア６の太さは十分に熱
伝導が可能な程度に出来るだけ太くしておく事が
望ましい。 Note that when forming the heat conductive layer 5, if the thickness is too thin, the thermal conductivity will be low and the heat dissipation efficiency will be poor, and if it is too thick, the productivity will be poor, so do not take care in controlling it. It must be done. Preferably, it is selected in the range of 0.5 to 20 μm. A well-known wire bonding technique may be used to form the thermally conductive wire 6 used to connect the thermally conductive layer 5 and the package 3. It is desirable that the wire 6 be as thick as possible to allow sufficient heat conduction.

第３図は、他の実施例を示した断面図で、第２
図に示した半導体基板１を複数個積層した構造と
なつている。７は半導体基板内に形成された半導
体素子領域、８は素子間を電気的に接続するアル
ミニウム等の配線層、９は積層した半導体基板１
の間に介在して互いを絶縁する絶縁層である。 FIG. 3 is a sectional view showing another embodiment;
It has a structure in which a plurality of semiconductor substrates 1 shown in the figure are stacked. 7 is a semiconductor element region formed in a semiconductor substrate; 8 is a wiring layer made of aluminum or the like that electrically connects elements; 9 is a stacked semiconductor substrate 1
This is an insulating layer interposed between them to insulate them from each other.

このような多層構造の半導体装置では、層間に
熱伝導層５を設けて放熱を行うことがより一層有
効である。多層構造の場合には、素子の集積密度
が高く、単位体積あたりの発熱が大きい反面、多
層間が熱伝導率の小さい絶縁層９で分離されてい
るためである。 In such a multilayered semiconductor device, it is even more effective to dissipate heat by providing a thermally conductive layer 5 between the layers. This is because in the case of a multilayer structure, the integration density of elements is high and heat generation per unit volume is large, but the multilayers are separated by an insulating layer 9 having low thermal conductivity.

（発明の効果） 以上実施例に基づいて詳細に説明したように、
この発明では、半導体基板表面に密着して形成し
た熱伝導層を用いて半導体素子の発生する熱を効
率よく放熱するようにしたので、熱発生の大きい
集積回路や個別半導体素子および半導体レーザ等
に利用して好適な半導体装置を実現することが出
来る。(Effect of the invention) As explained in detail based on the embodiments above,
In this invention, the heat generated by the semiconductor element is efficiently dissipated by using a thermally conductive layer formed in close contact with the surface of the semiconductor substrate. A suitable semiconductor device can be realized by utilizing this.

【図面の簡単な説明】[Brief explanation of the drawing]

第１図は従来の半導体装置の断面構造図、第２
図はこの発明の一実施例である半導体装置の断面
構造図、第３図は他の実施例の断面構造図であ
る。 １…半導体基板、３…パツケージ、４…冷却フ
イン、５…熱伝導層、６…熱伝導ワイア、７…半
導体素子領域、９…絶縁層。 Figure 1 is a cross-sectional structural diagram of a conventional semiconductor device;
The figure is a cross-sectional structural diagram of a semiconductor device which is one embodiment of the present invention, and FIG. 3 is a cross-sectional structural diagram of another embodiment. DESCRIPTION OF SYMBOLS 1... Semiconductor substrate, 3... Package, 4... Cooling fin, 5... Heat conductive layer, 6... Heat conductive wire, 7... Semiconductor element region, 9... Insulating layer.

Claims (1)

【特許請求の範囲】 １ 複数の半導体素子が形成され、積層された複
数の半導体基板と、 前記素子間を電気的に接続する配線と、 前記積層された基板間に介在する絶縁層とを有
する半導体装置において、 前記絶縁層内および前記積層された基板の最上
層に設けられ、お互いに熱伝導可能に接続された
熱伝導層と、 この熱伝導層と熱伝導可能に接続された放熱器
とを有することを特徴とする半導体装置。[Claims] 1. A semiconductor device comprising: a plurality of stacked semiconductor substrates on which a plurality of semiconductor elements are formed; wiring that electrically connects the elements; and an insulating layer interposed between the stacked substrates. In the semiconductor device, a thermally conductive layer provided in the insulating layer and on the top layer of the laminated substrates and connected to each other in a thermally conductive manner; and a heat sink connected to the thermally conductive layer in a thermally conductive manner. A semiconductor device characterized by having:
JP57108531A 1982-06-25 1982-06-25 Semiconductor device Granted JPS59944A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP57108531A JPS59944A (en) 1982-06-25 1982-06-25 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP57108531A JPS59944A (en) 1982-06-25 1982-06-25 Semiconductor device

Publications (2)

Publication Number Publication Date
JPS59944A JPS59944A (en) 1984-01-06
JPS6312384B2 true JPS6312384B2 (en) 1988-03-18

Family

ID=14487160

Family Applications (1)

Application Number Title Priority Date Filing Date
JP57108531A Granted JPS59944A (en) 1982-06-25 1982-06-25 Semiconductor device

Country Status (1)

Country Link
JP (1) JPS59944A (en)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
NL193609C (en) * 1981-12-30 2000-04-04 Bekaert Sa Nv Composite strand for processing as granulate in plastic products and method for manufacturing a plastic mixing granulate.
US4714953A (en) * 1986-05-12 1987-12-22 International Business Machines Corporation Welded wire cooling

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0134351Y2 (en) * 1980-11-14 1989-10-19

Also Published As

Publication number Publication date
JPS59944A (en) 1984-01-06

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