JPS59944A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPS59944A
JPS59944A JP57108531A JP10853182A JPS59944A JP S59944 A JPS59944 A JP S59944A JP 57108531 A JP57108531 A JP 57108531A JP 10853182 A JP10853182 A JP 10853182A JP S59944 A JPS59944 A JP S59944A
Authority
JP
Japan
Prior art keywords
heat
semiconductor substrate
semiconductor
conductive layer
semiconductor device
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP57108531A
Other languages
Japanese (ja)
Other versions
JPS6312384B2 (en
Inventor
Masayoshi Sasaki
佐々木　正義
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
National Institute of Advanced Industrial Science and Technology AIST
Original Assignee
Agency of Industrial Science and Technology
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Agency of Industrial Science and Technology filed Critical Agency of Industrial Science and Technology
Priority to JP57108531A priority Critical patent/JPS59944A/en
Publication of JPS59944A publication Critical patent/JPS59944A/en
Publication of JPS6312384B2 publication Critical patent/JPS6312384B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/42—Fillings or auxiliary members in containers or encapsulations selected or arranged to facilitate heating or cooling
    • H01L23/433—Auxiliary members in containers characterised by their shape, e.g. pistons
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
    • H01L2224/48464—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area also being a ball bond, i.e. ball-to-ball
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/49105—Connecting at different heights
    • H01L2224/49107—Connecting at different heights on the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/12—Passive devices, e.g. 2 terminal devices
    • H01L2924/1204—Optical Diode
    • H01L2924/12041—LED
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/1515—Shape
    • H01L2924/15153—Shape the die mounting substrate comprising a recess for hosting the device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/15165—Monolayer substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/161—Cap
    • H01L2924/1615—Shape
    • H01L2924/16195—Flat cap [not enclosing an internal cavity]

Landscapes

  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)

Abstract

PURPOSE:To efficiently dissipate heat even if the quantity of heat is increased by efficiently dissipating the heat generated from a semiconductor element by employing a heat conductive layer formed in contact with the surface of a semiconductor substrate. CONSTITUTION:A heat conductive layer 5 is formed of good heat conductor such as metal in contact with the surface of a semiconductor substrate 1. A heat conductive wire 6 is used to lead the heat from the layer 5 by means of conduction to a package 3. The heat generated at the substrate 1 is, as shown by an arrow, escaped to a route to the package 3 via the wire 6 from the layer 5 in addition to the conventional heat conduction route. Accordingly, the heat is led efficiently to an external cooling fin 4. The difference of the efficiency of heat conduction is made more clear when a semiconductor substrate 1 is composed of an insulator such as an SOS.

Description

【発明の詳細な説明】 （発明の技術分野） この発明は、発熱をともなう半導体素子の放熱を有効に
除去することの出来る半導体装置に関する。DETAILED DESCRIPTION OF THE INVENTION (Technical Field of the Invention) The present invention relates to a semiconductor device that can effectively eliminate heat radiation from a semiconductor element that is accompanied by heat generation.

（背景技術とその問題点） 第１図は放熱対策を施こした従来の半導体装νの断面構
造図である。(Background Art and Problems Therewith) FIG. 1 is a cross-sectional structural diagram of a conventional semiconductor device v with heat dissipation measures taken.

１は半導体素子がその内部に形成された半導体基板、２
はデンディング用ワイア、３はノ４ツケージ、４は放熱
用冷却フィン（放熱器）である。半導体基板１０表面近
くの素子活性領域で発生した熱は、半導体基板１からパ
ッケージ３を経て冷却フィン４に導びかれ、そこで放熱
する。熱の流れを模式的に矢印で示す。しかし、このよ
うな従来の半導体装置では、素子の集積度が上昇し、発
熱量が増加すると放熱効率が悪化してしまうという欠点
があった。1 is a semiconductor substrate in which a semiconductor element is formed; 2
3 is a wire for dending, 3 is a cage, and 4 is a cooling fin for heat radiation (radiator). Heat generated in the element active region near the surface of the semiconductor substrate 10 is guided from the semiconductor substrate 1 through the package 3 to the cooling fins 4, where it is radiated. Heat flow is schematically shown by arrows. However, such conventional semiconductor devices have the disadvantage that as the degree of integration of elements increases and the amount of heat generated increases, the heat dissipation efficiency deteriorates.

（発明の目的） この発明の目的は、発熱量が増加しても効率的に放熱を
行うことの出来る半導体装置を提供するにある。(Object of the Invention) An object of the present invention is to provide a semiconductor device that can efficiently dissipate heat even if the amount of heat generated increases.

（発明の概要） この発明では、半導体素子が形成された半導体複数個積
層するように構成して上記目的を達成し、Ｊｋ、。(Summary of the Invention) The present invention achieves the above object by stacking a plurality of semiconductors each having a semiconductor element formed thereon.

以下この発明の実施例を図面に基づいて詳細に説明する
。Embodiments of the present invention will be described in detail below with reference to the drawings.

（発明の実施例） 第２図はこの発明の一実施例を示す半導体装置の断面図
である。なお第１図に示したと同一部分は同一符号を付
して、説明を省略する。(Embodiment of the Invention) FIG. 2 is a sectional view of a semiconductor device showing an embodiment of the invention. Note that the same parts as shown in FIG. 1 are designated by the same reference numerals, and the description thereof will be omitted.

半導体基板１の表面に密着して金属などの熱の良導体で
熱伝導層５を形成する。またこの熱伝導層５から熱を伝
導により・母ツケージ３に導びくために熱伝導ワイア６
が用いられる。A thermally conductive layer 5 is formed of a good thermal conductor such as metal in close contact with the surface of the semiconductor substrate 1. In addition, a heat conductive wire 6 is used to conduct heat from the heat conductive layer 5 to the mother cage 3.
is used.

図中に矢印で示したように、半導体基板１で発生した熱
は、従来の熱伝導経路の外に熱伝導層５から熱伝導ワイ
ア６を経て、ノクツケージ３へと逃げる経路が付加され
ることになる。従がって熱はより効率的に外部の冷却フ
ィン４に導びかれる。As shown by the arrow in the figure, the heat generated in the semiconductor substrate 1 has an additional path to escape from the heat conduction layer 5 to the heat conduction wire 6 to the cage 3 in addition to the conventional heat conduction path. become. Therefore, heat is guided to the external cooling fins 4 more efficiently.

熱伝導の効率の差は半導体基板１が、５Ｏ８（５ｉｌｉ
ｃｏｎ　ｏｎ　５ａｐｐｈｉｒｅ　）などのように絶縁
体で構成されている場合にはいっそう明確になる。即ち
、半導体基板１から直接・母ツケージ３へと逃げる経路
の、放熱効率は半導体基板１の熱伝導率が小さいので非
常に小さい。The difference in heat conduction efficiency is that the semiconductor substrate 1 is 5O8 (5ili
This becomes even clearer when the structure is made of an insulator, such as a con on 5apphire. That is, the heat dissipation efficiency of the path escaping directly from the semiconductor substrate 1 to the mother cage 3 is extremely low because the thermal conductivity of the semiconductor substrate 1 is low.

それに対し、熱伝導層５から熱伝導ワイア６をを薄くし
すぎると熱伝導率が小さくなって、放熱、効率が悪くな
シ、厚すぎると生産性が悪くなるので制御には気を付け
なくてはならない。好ましくはり、５〜２０μｍの範囲
に選択するのが良い。熱伝導層５とパッケージ３との接
続に用いられる熱伝導ワイア６の形成には、周知のワイ
アボンディング技術を用いれば良い。ワイア６の太さは
十分に熱伝導が可能な程度に出来るだけ太くしておく事
が望ましい。On the other hand, if the thermal conductive wire 6 from the thermal conductive layer 5 is made too thin, the thermal conductivity will be low and the heat dissipation efficiency will be poor, and if it is too thick, the productivity will be poor, so do not pay attention to the control. must not. Preferably, the thickness is selected within the range of 5 to 20 μm. A well-known wire bonding technique may be used to form the thermally conductive wire 6 used to connect the thermally conductive layer 5 and the package 3. It is desirable that the wire 6 be as thick as possible to allow sufficient heat conduction.

第３図は、他の実施例を示した断面図で、第２図に示し
た半導体基板１を複数個積層した構造となっている。７
は半導体基板内に形成された半導体素子領域、８は素子
間を電気的に接続するアルミニウム等の配線層、９は積
層した半導体基板１の間に介在して互いを絶縁する絶縁
層である。FIG. 3 is a sectional view showing another embodiment, which has a structure in which a plurality of semiconductor substrates 1 shown in FIG. 2 are stacked. 7
Reference numeral 8 indicates a semiconductor element region formed in a semiconductor substrate, 8 a wiring layer made of aluminum or the like for electrically connecting elements, and 9 an insulating layer interposed between the stacked semiconductor substrates 1 to insulate them from each other.

このような多層構造の半導体装置では、眉間に熱伝導層
５を設けて放熱を行うことがよシ一層有効である。多層
構造の場合には、素子の集積密度が高く、単位体積あた
シの発熱が大きい反面、多層間が熱伝導率の小さい絶縁
層９で分離されているためである。In a semiconductor device having such a multilayer structure, it is even more effective to dissipate heat by providing a heat conductive layer 5 between the eyebrows. This is because, in the case of a multilayer structure, the integration density of elements is high and heat generation per unit volume is large, but the multilayers are separated by an insulating layer 9 having low thermal conductivity.

率よく放熱するようにしたので、熱発生の大きい集積回
路や個別半導体素子および半導体レーザ等に利用して好
適な半導体装置を実現することが出来る。Since heat is efficiently dissipated, a semiconductor device suitable for use in integrated circuits, individual semiconductor elements, semiconductor lasers, etc. that generate a large amount of heat can be realized.

【図面の簡単な説明】[Brief explanation of drawings]

第１図は従来の半導体装置の断面構造図、第２図はこの
発明の一実施例である半導体装置の断面構造図、第３図
は他の実施例の断面構造図である。 １・・・半導体基板、３・・・パッケージ、４・・・冷
却フィン、５・・・熱伝導層、６・・・熱伝導ワイア、
７・・・半導体素子領域、９・・・絶縁層。 特許出願人　工業技術院長　石　　坂　　誠　　−第２
図FIG. 1 is a sectional structural diagram of a conventional semiconductor device, FIG. 2 is a sectional structural diagram of a semiconductor device according to an embodiment of the present invention, and FIG. 3 is a sectional structural diagram of another embodiment. DESCRIPTION OF SYMBOLS 1... Semiconductor substrate, 3... Package, 4... Cooling fin, 5... Heat conductive layer, 6... Heat conductive wire,
7... Semiconductor element region, 9... Insulating layer. Patent applicant Makoto Ishizaka, Director of the Agency of Industrial Science and Technology - 2nd
figure

Claims (2)

【特許請求の範囲】[Claims] （１）半導体素子が形成された半導体基板の表面に密着
して形成した熱伝導層と、この熱伝導層と放熱器とを熱
伝導可能に接続する熱伝導ワイアとを有し、前記半導体
基板を単独または複数個積層してなる半導体装置。(1) A thermally conductive layer formed in close contact with the surface of a semiconductor substrate on which a semiconductor element is formed, and a thermally conductive wire that connects the thermally conductive layer and a radiator in a thermally conductive manner, and the semiconductor substrate Semiconductor device made by laminating one or more of these. （２）　　前記半導体基板の積層にあたシ絶縁層を介在
せしめた事を特徴とする特許請求の範囲第（１）項記載
の半導体装置。(2) The semiconductor device according to claim (1), characterized in that an insulating layer is interposed between the stacked semiconductor substrates.
JP57108531A 1982-06-25 1982-06-25 Semiconductor device Granted JPS59944A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP57108531A JPS59944A (en) 1982-06-25 1982-06-25 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP57108531A JPS59944A (en) 1982-06-25 1982-06-25 Semiconductor device

Publications (2)

Publication Number Publication Date
JPS59944A true JPS59944A (en) 1984-01-06
JPS6312384B2 JPS6312384B2 (en) 1988-03-18

Family

ID=14487160

Family Applications (1)

Application Number Title Priority Date Filing Date
JP57108531A Granted JPS59944A (en) 1982-06-25 1982-06-25 Semiconductor device

Country Status (1)

Country Link
JP (1) JPS59944A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4664971A (en) * 1981-12-30 1987-05-12 N.V. Bekaert S.A. Plastic article containing electrically conductive fibers
US4714953A (en) * 1986-05-12 1987-12-22 International Business Machines Corporation Welded wire cooling

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5784750U (en) * 1980-11-14 1982-05-25

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5784750U (en) * 1980-11-14 1982-05-25

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4664971A (en) * 1981-12-30 1987-05-12 N.V. Bekaert S.A. Plastic article containing electrically conductive fibers
US4714953A (en) * 1986-05-12 1987-12-22 International Business Machines Corporation Welded wire cooling

Also Published As

Publication number Publication date
JPS6312384B2 (en) 1988-03-18

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