JPS6312263B2 - - Google Patents

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Publication number
JPS6312263B2
JPS6312263B2 JP1627880A JP1627880A JPS6312263B2 JP S6312263 B2 JPS6312263 B2 JP S6312263B2 JP 1627880 A JP1627880 A JP 1627880A JP 1627880 A JP1627880 A JP 1627880A JP S6312263 B2 JPS6312263 B2 JP S6312263B2
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JP
Japan
Prior art keywords
voltage
capacitive element
circuit
measured
multiplier
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP1627880A
Other languages
Japanese (ja)
Other versions
JPS56112663A (en
Inventor
Seijiro Nosaka
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
KUWANO ELECTRIC INSTR
Original Assignee
KUWANO ELECTRIC INSTR
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Filing date
Publication date
Application filed by KUWANO ELECTRIC INSTR filed Critical KUWANO ELECTRIC INSTR
Priority to JP1627880A priority Critical patent/JPS56112663A/en
Publication of JPS56112663A publication Critical patent/JPS56112663A/en
Publication of JPS6312263B2 publication Critical patent/JPS6312263B2/ja
Granted legal-status Critical Current

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Classifications

    • GPHYSICS
    • G01MEASURING; TESTING
    • G01RMEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R27/00Arrangements for measuring resistance, reactance, impedance, or electric characteristics derived therefrom
    • G01R27/02Measuring real or complex resistance, reactance, impedance, or other two-pole characteristics derived therefrom, e.g. time constant
    • G01R27/26Measuring inductance or capacitance; Measuring quality factor, e.g. by using the resonance method; Measuring loss factor; Measuring dielectric constants ; Measuring impedance or related variables
    • G01R27/2688Measuring quality factor or dielectric loss, e.g. loss angle, or power factor
    • G01R27/2694Measuring dielectric loss, e.g. loss angle, loss factor or power factor

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Measurement Of Resistance Or Impedance (AREA)

Description

【発明の詳細な説明】 本発明は、容量素子の損失測定装置に関する。[Detailed description of the invention] The present invention relates to a capacitive element loss measuring device.

容量素子の損失測定装置として従来、第1図に
つき以下述べる構成のものが提案されている。
Conventionally, an apparatus for measuring loss of a capacitive element has been proposed with the configuration described below with reference to FIG.

即ち、 e0=E0sinωt …(1) で表わされる(但しE0は振幅、ωは角周波数、
tは時間)交流定電流e0の得られる交流定電圧源
1を有し、それに、静電容量CSと抵抗RSとの直
列等価回路で表わされる被測定容量素子2が、こ
れに i0=I0sinωt …(1)′ で表わされる定電流i0(但しI0は振幅)が流れて、
被測定容量素子2にて e1=i0Z=I0R0sinωt+I0/ωCSsin(ωt−π/2) =I0(RSsinωt−1/ωCScosωt) …(2) で表わされる被測定容量素子2の静電容量CSに逆
比例した交流電圧及び抵抗RSに比例した交流電
圧の和の交流電圧e1が得られる様に、定電流用抵
抗R0を介して接続されている。
That is, e 0 = E 0 sinωt …(1) (where E 0 is the amplitude, ω is the angular frequency,
It has an AC constant voltage source 1 that provides an AC constant current e 0 (t is time), and a capacitive element 2 to be measured represented by a series equivalent circuit of a capacitance C S and a resistance R S. 0 = I 0 sinωt …(1)′ A constant current i 0 (where I 0 is the amplitude) flows,
At capacitive element 2 to be measured, e 1 = i 0 Z = I 0 R 0 sinωt + I 0 /ωC S sin (ωt-π/2) = I 0 (R S sinωt-1/ωC S cosωt) ...(2) Through the constant current resistor R 0 so as to obtain an AC voltage e 1 which is the sum of the AC voltage inversely proportional to the capacitance C S of the capacitive element 2 to be measured and the AC voltage proportional to the resistance R S . It is connected.

又定電流用抵抗R0の両端に、移相回路5の入
力側が接続され、而してこの定電流用抵抗R0
両端にて得られる交流定電圧源1より得られる交
流定電圧e0に基く e0′=−i0R0=−I0R0sinωt …(1)″ で表わされる降下電圧e0′に基き、移相回路5の
出力側より、 e3=e0′ωC1R1=−I0R0ωC1R1sin(ωt+π/2)…(3
) で表わされる、降下交流電圧e0′に対して90゜の位
相差を有する交流電圧e3が得られる様になされて
いる。この場合移相回路5は、入力端子aと、接
地に接続されている入力端子aとは逆極性の入力
端子bと、入力端子aとは同極性の出力端子cと
を有する演算増幅器6と、一端が演算増幅器6の
入力端子aに、他端が極性反転回路INを介して
定電流用抵抗R0の接地側に接続されてなる容量
C1と、演算増幅器6の出力端子c及び入力端子
a間に接続せる抵抗R1とよりなる。
In addition, the input side of the phase shift circuit 5 is connected to both ends of the constant current resistor R 0 , and the AC constant voltage e 0 obtained from the AC constant voltage source 1 is obtained at both ends of the constant current resistor R 0 . Based on the drop voltage e 0 ′ expressed as e 0 ′=−i 0 R 0 =−I 0 R 0 sinωt …(1)″, from the output side of the phase shift circuit 5, e 3 = e 0 ′ωC 1 R 1 = −I 0 R 0 ωC 1 R 1 sin(ωt+π/2)…(3
), the AC voltage e 3 having a phase difference of 90° with respect to the falling AC voltage e 0 ' is obtained. In this case, the phase shift circuit 5 includes an operational amplifier 6 having an input terminal a, an input terminal b connected to ground and having the opposite polarity to the input terminal a, and an output terminal c having the same polarity as the input terminal a. , one end is connected to the input terminal a of the operational amplifier 6, and the other end is connected to the ground side of the constant current resistor R0 via the polarity inversion circuit IN.
C 1 and a resistor R 1 connected between the output terminal c and the input terminal a of the operational amplifier 6.

而して被測定容量素子2の両端より得られる交
流電圧e1が必要に応じて増幅器7を通じて乗算回
路8の一方の入力端子に供給され、一方乗算回路
8の他方の入力端子に移相回路5より得られる交
流電圧e3が必要に応じて増幅器9を通じて供給さ
れ、依つて乗算回路8より交流電圧e1及びe3に基
き E1=K1K3I0 2R0C1R1/2CS …(4) で表わされる、被測定容量素子2の静電容量CS
逆比例した直流電圧E1が得られるようになされ
ている。この場合乗算回路8は e4=K1e1・K3e3 =K1I0(RSsinωt−1/ωCScosωt)×{−K3I0R0ω
C1R1sin(ωt+π/2)} =−K1K3I0 2RSR0ωC1R1sin2ωt/2+K1K3I0 2R0C1R1
(1+cos2ωt)/2CS =K1K3I0 2R0C1R1/2CS−K1K3I0 2R0ωC1R1/2(RSsin
2ωt−1/ωCScos2ωt)…(5) で表わされる(但しK1及びK3は定数)、交流電圧
e1に基く電圧と交流電圧e3に基く電圧との積の出
力e4の得られる様に構成された乗算回路本体10
と、その出力側に接続された出力e4に基き(4)式で
表わされる直流電圧E1の得られる様に構成され
た低域波器11とよりなる。
The alternating current voltage e1 obtained from both ends of the capacitive element 2 to be measured is supplied to one input terminal of a multiplier circuit 8 via an amplifier 7 as necessary, and the other input terminal of the multiplier circuit 8 is supplied to a phase shift circuit. The alternating current voltage e 3 obtained from 5 is supplied through the amplifier 9 as necessary, and therefore, based on the alternating current voltages e 1 and e 3 from the multiplier circuit 8, E 1 =K 1 K 3 I 0 2 R 0 C 1 R 1 /2C S (4) A DC voltage E 1 that is inversely proportional to the capacitance C S of the capacitive element 2 to be measured is obtained. In this case, the multiplier circuit 8 is e 4 =K 1 e 1・K 3 e 3 =K 1 I 0 (R S sinωt−1/ωC S cosωt)×{−K 3 I 0 R 0 ω
C 1 R 1 sin(ωt+π/2)} =−K 1 K 3 I 0 2 R S R 0 ωC 1 R 1 sin2ωt/2+K 1 K 3 I 0 2 R 0 C 1 R 1
(1+cos2ωt)/2C S =K 1 K 3 I 0 2 R 0 C 1 R 1 /2C S −K 1 K 3 I 0 2 R 0 ωC 1 R 1 /2 (R S sin
2ωt−1/ωC S cos2ωt)…(5) (where K 1 and K 3 are constants), AC voltage
Multiplier circuit main body 10 configured to obtain output e 4 of the product of the voltage based on e 1 and the voltage based on AC voltage e 3
and a low frequency converter 11 configured to obtain a DC voltage E 1 expressed by equation (4) based on the output e 4 connected to its output side.

又被測定容量素子2の両端より得られる交流電
圧e1が必要に応じて上述せる増幅器7を通じて他
の乗算回路12の一方の入力端子に供給され、一
方乗算回路12の他方の入力端子に定電流用抵抗
R0の両端より得られる降下交流電圧e0′が必要に
応じて極性反転を伴う増幅器13を通じて供給さ
れ、依つて乗算回路12より交流電圧e0′及びe1
に基き、 E2=K0K1I0 2RSR0/2 …(6) で表わされる被測定容量素子2の抵抗RSに比例
した直流電圧E2が得られる様になされている。
この場合乗算回路12は e5=K0e0′・K1e1=K0I0R0sinωt・K1I0(RSsinωt−1
/ωCScosωt) =K0K1I0 2RSR0(1−cos2ωt)/2−K0K1I0 2R0sin2
ωt/2ωCS =K0K1I0 2RSR0/2−K0K1I0 2R0/2(RScos2ωt+1
/ωCSsin2ωt)…(7) で表わされる(但しK0及びK1は定数)、交流電圧
e0′に基く出力及び交流電圧e1に基く出力の積の
出力e5の得られる様に構成された乗算回路本体1
4と、その出力側に接続された出力e5に基き(6)式
で表わされる直流電圧E2の得られる様に構成さ
れた低域波器15とよりなる。
Further, the AC voltage e1 obtained from both ends of the capacitive element 2 to be measured is supplied to one input terminal of another multiplier circuit 12 through the above-mentioned amplifier 7 as necessary, and a constant voltage e1 is supplied to the other input terminal of the multiplier circuit 12. Current resistance
The dropped AC voltage e 0 ' obtained from both ends of R 0 is supplied through an amplifier 13 with polarity reversal as required, and the AC voltages e 0 ' and e 1 are supplied from the multiplier circuit 12.
Based on the equation, E 2 = K 0 K 1 I 0 2 R S R 0 /2 (6) It is designed to obtain a DC voltage E 2 proportional to the resistance R S of the capacitive element 2 under test. .
In this case, the multiplication circuit 12 is e 5 =K 0 e 0 ′・K 1 e 1 =K 0 I 0 R 0 sinωt・K 1 I 0 (R S sinωt−1
/ωC S cosωt) =K 0 K 1 I 0 2 R S R 0 (1-cos2ωt)/2-K 0 K 1 I 0 2 R 0 sin2
ωt/2ωC S =K 0 K 1 I 0 2 R S R 0 /2−K 0 K 1 I 0 2 R 0 /2 (R S cos2ωt+1
/ωC S sin2ωt)…(7) (where K 0 and K 1 are constants), AC voltage
Multiplier circuit main body 1 configured to obtain an output e 5 which is the product of the output based on e 0 ′ and the output based on the AC voltage e 1
4, and a low frequency filter 15 connected to the output side and configured to obtain a DC voltage E2 expressed by equation (6) based on the output e5 .

更に乗算回路8及び12より得られる直流電圧
E1及びE2が演算回路23の除算回路24に供給
され、これにより直流電圧E1及びE2に基き、 E2/E1=K0K1I0 2RSR0/2・2CS/K1K3I0 2R0C1R1 =K0/K3C1R1・RSCS=ω0RSCS=tanδ=D …(8) で表わされる被測定容量素子2の損失Dを表わす
出力Qが得られる様になされている。
Furthermore, the DC voltage obtained from multiplier circuits 8 and 12
E 1 and E 2 are supplied to the division circuit 24 of the arithmetic circuit 23, and based on the DC voltages E 1 and E 2 , E 2 /E 1 =K 0 K 1 I 0 2 R S R 0 /2・2C S /K 1 K 3 I 0 2 R 0 C 1 R 1 = K 0 /K 3 C 1 R 1・R S C S = ω 0 R S C S = tan δ = D …(8) An output Q representing the loss D of the capacitive element 2 is obtained.

以上が従来提案されている容量素子の損失測定
装置であるが、斯る容量素子の損失測定装置の場
合、演算回路23の除算回路24より得られる出
力Qにより被測定容量素子2の直列等価回路でみ
たω0RSCS=Dで表わされる損失Dを判知し得る
ものであるが、出力Qが直流電圧E1及びE2の除
算により得られる出力であり、而してその直流電
圧E1及びE2の得られる乗算回路8及び12に対
する夫々交流電圧e3及びe0′と乗算される交流電
圧が、被測定容量素子2の静電容量CS及び抵抗
RSの値に応じたレベルをとる交流電圧e1である
為、乗算回路8及び12より直流電圧E1及びE2
を被測定容量素子2の静電容量CS及び抵抗RS
値に関せず高分解能で得るに困難を伴い、依つて
判知し得る損失Dを被測定容量素子2の静電容量
CS及び抵抗RSの値に関せず高分解能で得ること
が出来ないという欠点を有していた。
The above is a capacitive element loss measuring device that has been proposed conventionally. It is possible to determine the loss D expressed by ω 0 R S C S =D, but since the output Q is the output obtained by dividing the DC voltages E 1 and E 2 , the DC voltage The AC voltages multiplied by the AC voltages e 3 and e 0 ′ for the multiplier circuits 8 and 12 obtained by E 1 and E 2 , respectively, are the capacitance C S and resistance of the capacitive element 2 to be measured.
Since the AC voltage e 1 takes a level according to the value of R S , the DC voltages E 1 and E 2 are generated by the multiplier circuits 8 and 12.
It is difficult to obtain with high resolution regardless of the values of the capacitance C S and the resistance R S of the capacitive element 2 to be measured.
It has the disadvantage that high resolution cannot be obtained regardless of the values of C S and resistance R S.

依つて本発明は斯る欠点のない新規な容量素子
の損失測定装置を提案せんとするもので、以下詳
述する所より明らかとなるであろう。
Therefore, the present invention aims to propose a novel capacitive element loss measuring device free from such drawbacks, which will become clear from the detailed description below.

第2図には本発明による容量素子の損失測定装
置の一例を示し、第1図との対応部分には同一符
号を附して示すも、第1図にて前述せる(1)式で表
わされる交流定電圧e0の得られる交流定電圧源1
を有し、それに静電容量CSと抵抗RSとの直列等
価回路で表わされる被測定容量素子2が、これに
第1図にて前述せる如く前述せる(1)′式で表わさ
れる定電流i0が流れて被測定容量素子2にて前述
せる(2)式で表わされる交流電圧e1が得られる様
に、定電流用抵抗R0を介して接続されている。
FIG. 2 shows an example of a loss measuring device for a capacitive element according to the present invention. Corresponding parts to those in FIG. AC constant voltage source 1 that provides an AC constant voltage e 0
The capacitive element 2 to be measured, which is represented by a series equivalent circuit of a capacitance C S and a resistor R S , has a constant value expressed by equation (1)' as described above in FIG. They are connected via a constant current resistor R 0 so that a current i 0 flows and an alternating current voltage e 1 expressed by the above-mentioned equation (2) is obtained at the capacitive element 2 to be measured.

又定電流用抵抗R0の両端に、第1図にて前述
せると同様に演算増幅器6、抵抗R1及び容量C1
よりなる移相回路5の入力側が接続され、而して
定電流用抵抗R0の両端にて得られる(1)″式で表わ
される降下電圧e0′に基き、移相回路5の出力側
より、第1図にて前述せると同様に前述せる(3)式
で表わされる交流電圧e0′に対して90゜の位相差を
有する交流電圧e3が得られる様になされている。
In addition, an operational amplifier 6, a resistor R 1 and a capacitor C 1 are connected to both ends of the constant current resistor R 0 as described above in FIG.
The output side of the phase shift circuit 5 is connected to the input side of the phase shift circuit 5 consisting of Thus, as described above with reference to FIG. 1, an AC voltage e 3 having a phase difference of 90° with respect to the AC voltage e 0 ' expressed by equation (3) described above is obtained.

而して被測定容量素子2の両端より得られる交
流電圧e1が必要に応じて増幅器7を通じて、入力
電圧のレベルの変化によるも略々一定レベルを有
する出力電圧の得られる様になされた増幅回路3
1に供給され、依つてこの増幅回路31より、交
流電圧e1に基き、 e2=K2I0(RSsinωt−1/ωCScosωt) …(9) で表わされる(但しK2は係数)略々一定レベル
を有する交流電圧e2が得られる様になされてい
る。この場合交流電圧e2が略々一定レベルを有す
るということは、 で表わされる交流電圧e2の絶対値|e2|が略々一
定のレベルを有するということであるが、斯る交
流電圧e2が得られる様になされた増幅回路31
は、被測定容量素子2の静電容量CS及び抵抗RS
が予定の範囲内で変化しても、即ち(9)式中のCS
びRSが予定の範囲内で変化しても、これに応じ
て係数K2(増幅度)が変化して、交流電圧e2
略々一定レベルで得られる様になされた所謂
AGC機能を有する増幅回路の構成でなる。
The alternating current voltage e1 obtained from both ends of the capacitive element 2 to be measured is passed through an amplifier 7 as necessary to obtain an output voltage having a substantially constant level even when the level of the input voltage changes. circuit 3
Based on the AC voltage e 1 from this amplifier circuit 31, e 2 =K 2 I 0 (R S sinωt−1/ωC S cosωt) …(9) (However, K 2 is coefficient) is designed to obtain an AC voltage e 2 having a substantially constant level. In this case, the AC voltage e 2 has an approximately constant level, which means that This means that the absolute value of the AC voltage e 2 expressed by |e 2 | has a substantially constant level.
are the capacitance C S and resistance R S of the capacitive element 2 to be measured.
Even if changes within the planned range, that is, even if C S and R S in equation (9) change within the planned range, the coefficient K 2 (amplification degree) changes accordingly, The so-called AC voltage e 2 is made to be obtained at a substantially constant level.
It consists of an amplifier circuit with AGC function.

又上述せる如くに増幅回路31より得られる
略々一定レベルを有する交流電圧e2が、第1図に
て前述せると同様の乗算回路本体10及び低域
波器11よりなる乗算回路8の一方の入力側に供
給され、一方乗算回路8の他方の入力側に移相回
路5より得られる前述せる(3)式で表わされる交流
電圧e3が第1図にて前述せると同様に必要に応じ
て増幅器9を通じて供給され、依つて乗算回路8
より交流電圧e2及びe3に基き、第1図にて前述せ
る(4)式に準じた E1′=K2K3I0 2R0C1R1/2CS …(4)′ で表わされる、被測定容量素子2の静電容量CS
逆比例した直流電圧E1′が得られる様になされて
いる。この場合乗算回路8の乗算回路本体10よ
りは第1図にて前述せる(5)式に準じた e4′=e2・K3e3 =K2I0(RSsinωt−1/ωCScosωt)×{−K3I0R0ω
C1R1sin(ωt+π/2)} =K2K3I0 2RSR0ωC1R1sin2ωt/2+K2K3I0 2R0C1R1
1+cos2ωt)/2CS =K2K3I0 2R0C1R1/2CS−K2K3I0 2R0ωC1R1/2(RSsin
2ωt−1/ωCScos2ωt)…(5)′ で表わされる交流電圧e4′が得られる様になされ、
これに応じて低域波器11より上述せる(4)′式
で表わされる直流電圧E1′が得られる様になされ
ているものである。
Furthermore, as described above, the AC voltage e2 having a substantially constant level obtained from the amplifier circuit 31 is applied to one side of the multiplier circuit 8 consisting of the multiplier circuit main body 10 and the low frequency converter 11 similar to those described above in FIG. The AC voltage e 3 expressed by the equation (3) mentioned above, which is supplied to the input side of one multiplier circuit 8 and obtained from the phase shift circuit 5 to the other input side of the multiplier circuit 8, is required as described above in FIG. is supplied through the amplifier 9 accordingly, and thus the multiplier circuit 8
Based on the AC voltages e 2 and e 3 , E 1 ′=K 2 K 3 I 0 2 R 0 C 1 R 1 /2C S …(4)′ according to equation (4) shown in FIG. The arrangement is such that a DC voltage E 1 ', which is inversely proportional to the capacitance C S of the capacitive element 2 to be measured, is obtained. In this case, from the multiplier circuit main body 10 of the multiplier circuit 8, e 4 ′=e 2・K 3 e 3 =K 2 I 0 (R S sinωt−1/ωC S cosωt)×{−K 3 I 0 R 0 ω
C 1 R 1 sin(ωt+π/2)} =K 2 K 3 I 0 2 R S R 0 ωC 1 R 1 sin2ωt/2+K 2 K 3 I 0 2 R 0 C 1 R 1 (
1 + cos2ωt) /2C S =K 2 K 3 I 0 2 R 0 C 1 R 1 /2C S −K 2 K 3 I 0 2 R 0 ωC 1 R 1 /2 (R S sin
2ωt−1/ωC S cos2ωt)…(5)′ The alternating current voltage e 4 ′ is obtained,
Correspondingly, the DC voltage E 1 ' expressed by the above-mentioned equation (4)' is obtained from the low frequency converter 11.

更に増幅回路31より得られる略々一定レベル
を有する交流電圧e2が、第1図にて上述せると同
様の乗算回路本体14及び低域波器15よりな
る乗算回路12の一方の入力側に供給され、一方
乗算回路12の他方の入力側に定電流用抵抗R0
の両端より得られる前述せる(1)″式で表わされる
交流電圧e0′が第1図にて前述せると同様に必要
に応じて極性反転を伴う増幅器13を通じて供給
され、依つて乗算回路12より、交流電圧e2及び
e0′に基き第1図にて前述せる(6)式に準じた E2′=K0K2I0 2RSR0/2 …(6)′ で表わされる、被測定容量素子2の抵抗RSに比
例した直流電圧E2′が得られる様になされている。
この場合乗算回路12の乗算回路本体14よりは
第1図にて前述せる(7)式に準じた e5′=e2・K0e0′=K2I0(RSsinωt−1/ωCScosωt)
・K0I0R0sinωt =K0K2I0 2RSR0(1−cos2ωt)/2−K0K2I0 2R0sinω
t/2ωCS =K0K2I0 2RSR0/2−K0K2I0 2R0/2(RScos2ωt+1
/ωCSsin2ωt)…(7)′ で表わされる交流電圧e5′が得られる様になされ、
これに応じて低域波器15より上述せる(6)′式
で表わされる直流電圧E2′が得られる様になされ
ているものである。
Furthermore, the AC voltage e 2 having a substantially constant level obtained from the amplifier circuit 31 is applied to one input side of the multiplier circuit 12 consisting of the multiplier circuit main body 14 and the low-frequency amplifier 15 similar to those described above in FIG. A constant current resistor R0 is supplied to the other input side of the multiplier circuit 12.
The alternating current voltage e 0 ′ expressed by the above-mentioned equation (1)″ obtained from both ends of Therefore, the alternating voltage e 2 and
E 2 ′=K 0 K 2 I 0 2 R S R 0 /2 ...(6)′ according to equation (6) shown in FIG. 1 based on e 0 ′, A DC voltage E 2 ' proportional to the resistance R S is obtained.
In this case, from the multiplier circuit body 14 of the multiplier circuit 12, e 5 ′=e 2・K 0 e 0 ′=K 2 I 0 (R S sinωt−1/ ωC S cosωt)
・K 0 I 0 R 0 sinωt =K 0 K 2 I 0 2 R S R 0 (1−cos2ωt)/2−K 0 K 2 I 0 2 R 0 sinω
t/2ωC S =K 0 K 2 I 0 2 R S R 0 /2−K 0 K 2 I 0 2 R 0 /2 (R S cos2ωt+1
/ωC S sin2ωt)…(7)′ The alternating current voltage e 5 ′ is obtained,
Correspondingly, the DC voltage E 2 ' expressed by the above-mentioned equation (6)' is obtained from the low frequency converter 15.

又乗算回路8及び12より得られる直流電圧
E1′及びE2′が第1図の場合と同様に演算回路23
の除算回路24に供給され、これより直流電圧
E1′及びE2′に基き E1′/E1′=K0K2I0 2RSR0/2・2CS/K2K3I0 2R0C1R1 =K0/K3C1R1・RSCS=ω0RSCS=tanδ=D (8)′ で表わされる、第1図の場合の被測定容量素子2
の損失Dを表わす出力Qと同じ、被測定容量素子
2の損失Dを表わす出力Q′が得られる様になさ
れている。
Also, the DC voltage obtained from multiplier circuits 8 and 12
E 1 ′ and E 2 ′ are connected to the arithmetic circuit 23 as in the case of FIG.
is supplied to the division circuit 24, from which the DC voltage
Based on E 1 ′ and E 2 ′, E 1 ′ / E 1 ′ = K 0 K 2 I 0 2 R S R 0 /2・2C S /K 2 K 3 I 0 2 R 0 C 1 R 1 = K 0 /K 3 C 1 R 1・R S C S = ω 0 R S C S = tan δ=D (8)' The measured capacitive element 2 in the case of Fig. 1
The output Q' representing the loss D of the capacitive element 2 to be measured is the same as the output Q representing the loss D of the capacitive element 2 to be measured.

以上が本発明による容量素子の損失測定装置の
一例構成であるが、斯る構成によればその演算回
路23の除算回路24から直流電圧E1′及びE2′の
除算により得られる出力Q′が、第1図の場合の
出力Qと同じであるので、その出力Q′により第
1図の場合と同様に被測定容量素子2の直列等価
回路でみたω0RSCS=Dで表わされる損失Dを判
知し得ること明らかである。
The above is an example of the configuration of the capacitive element loss measuring device according to the present invention. According to this configuration, the output Q' obtained from the division circuit 24 of the arithmetic circuit 23 by dividing the DC voltages E 1 ' and E 2 ' is the same as the output Q in the case of Fig. 1, so the output Q' can be expressed as ω 0 R S C S = D as seen in the series equivalent circuit of the capacitive element 2 to be measured, as in the case of Fig. 1. It is clear that it is possible to determine the loss D that occurs.

然し乍ら第2図にて上述せる本発明による容量
素子の損失測定装置の場合、出力Q′が直流電圧
E1′及びE2′の除算により得られる出力であり、而
してその直流電圧E1′及びE2′の得られる乗算回路
8及び12に対する夫々交流電圧e3及びe0′と乗
算される交流電圧が被測定容量素子2の静電容量
CS及び抵抗RSの値に関せず略々一定レベルをと
る交流電圧e2である為、乗算回路8及び12より
夫々直流電圧E1′及びE2′を被測定容量素子2の静
電容量CS及び抵抗RSの値に関せず高分解能で得
る様になすことが、乗算回路8及び12に対する
夫々交流電圧e3及びe0と乗算される交流電圧が、
被測定容量素子2の静電容量CS及び抵抗RSの値
に応じて変化するレベルをとる交流電圧e1である
第1図にて上述せる従来の場合に比し、容易であ
り、依つて出力Q′を被測定容量素子2の静電容
量CS及び抵抗RSの値に関せず、第1図にて上述
せる従来の場合の出力Qに比し、高分解能で得る
様になすこと容易であるものである。
However, in the case of the capacitive element loss measuring device according to the present invention as shown in FIG.
It is the output obtained by dividing E 1 ′ and E 2 ′, and the DC voltages E 1 ′ and E 2 ′ are multiplied by the AC voltages e 3 and e 0 ′ for the multiplier circuits 8 and 12, respectively. The AC voltage is the capacitance of the capacitive element 2 to be measured.
Since the AC voltage e 2 has a substantially constant level regardless of the values of C S and resistor R S , the DC voltages E 1 ′ and E 2 ′ are applied to the static voltage of the capacitive element 2 to be measured from the multiplier circuits 8 and 12, respectively. In order to obtain high resolution regardless of the values of the capacitance C S and the resistance R S , the AC voltage to be multiplied by the AC voltages e 3 and e 0 for the multiplier circuits 8 and 12, respectively, is
This method is easier and more reliable than the conventional case described above in FIG . In this way, the output Q ' can be obtained with higher resolution than the output Q in the conventional case described above in FIG. It is something that is easy to do.

依つて第2図にて上述せる本発明による容量素
子の損失測定装置の場合、出力Q′より判知し得
る被測定容量素子2の損失Dを、被測定容量素子
2の静電容量CS及び抵抗RSの値に関せず、第1
図にて上述せる従来の場合に比し高分解能を有す
るものとすることが出来るという大なる特徴を有
するものである。
Therefore, in the case of the capacitive element loss measuring device according to the present invention described above in FIG. and the value of the resistor R S , the first
This method has a great feature of being able to provide higher resolution than the conventional case described above in the figure.

尚上述に於ては本発明の1つの例を示したに留
まり、例えば乗算回路8及び12の夫々と除算回
路24との間に必要に応じて増幅回路を介挿する
ことも出来、又乗算回路8及び12をその乗算回
路本体10及び14をして同期検波回路本体に代
えた同期検波回路に置換せる構成とすることも出
来、その他本発明の精神を脱することなしに種々
の変型変更をなし得るであろう。
The above description has only shown one example of the present invention; for example, an amplifier circuit may be inserted between each of the multiplier circuits 8 and 12 and the divider circuit 24 as necessary; It is also possible to replace the circuits 8 and 12 with a synchronous detection circuit in which the multiplier circuit bodies 10 and 14 are replaced with the synchronous detection circuit body, and various other modifications and changes may be made without departing from the spirit of the present invention. will be able to do it.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は従来の容量素子の損失測定装置を示す
系統図、第2図は本発明による容量素子の損失測
定装置の一例を示す系統図である。 図中1は交流電圧源、2は被測定容量素子、CS
は静電容量、RSは抵抗、R0は定電流用抵抗、5
は移相回路、8及び12は乗算回路、10及び1
4は乗算回路本体、11及び15は低域波器、
31は増幅回路を夫々示す。
FIG. 1 is a system diagram showing a conventional capacitive element loss measuring device, and FIG. 2 is a system diagram showing an example of a capacitive element loss measuring device according to the present invention. In the figure, 1 is an AC voltage source, 2 is a capacitive element to be measured, and C S
is capacitance, R S is resistance, R 0 is constant current resistance, 5
is a phase shift circuit, 8 and 12 are multiplication circuits, 10 and 1
4 is the multiplication circuit main body, 11 and 15 are low frequency devices,
Reference numeral 31 indicates an amplifier circuit.

Claims (1)

【特許請求の範囲】 1 交流電圧源と、 該交流電圧源より得られる交流電圧に基き、こ
れに対して90゜の位相差を有する第3の交流電圧
を得る様になされた移相回路と、 上記交流電圧源に当該交流電圧源側より定電流
が流れるべく接続された被測定容量素子に於ける
降下交流電圧でなる第1の交流電圧に基き、その
レベルが変化しても略々一定レベルを有する第2
の交流電圧を得る様になされたAGC機能を有す
る増幅回路と、 上記第2及び第3の交流電圧に基き、上記被測
定容量素子の静電容量に逆比例した第1の直流電
圧を得る様になされた第1の乗算回路又は同期検
波回路と、 上記交流電圧源より得られる交流電圧と上記第
2の交流電圧とに基き、上記被測定容量素子の抵
抗に比例した第2の直流電圧を得る様になされた
第2の乗算回路又は同期検波回路と、 上記第1及び第2の直流電圧に基き、その第2
の直流電圧を第1の直流電圧で除算してなる上記
被測定容量素子の損失を表す出力を得る様になさ
れた演算回路とを具備することを特徴とする容量
素子の損失測定装置。
[Claims] 1. An AC voltage source, and a phase shift circuit configured to obtain a third AC voltage having a phase difference of 90° with respect to the AC voltage obtained from the AC voltage source. , Based on the first AC voltage that is the AC voltage drop across the capacitive element to be measured, which is connected to the AC voltage source so that a constant current flows from the AC voltage source side, it is approximately constant even if its level changes. 2nd with level
an amplifier circuit having an AGC function configured to obtain an alternating current voltage; and a first direct current voltage inversely proportional to the capacitance of the capacitive element to be measured based on the second and third alternating voltages. A second DC voltage proportional to the resistance of the capacitive element to be measured is calculated based on the first multiplier circuit or synchronous detection circuit, the AC voltage obtained from the AC voltage source, and the second AC voltage. a second multiplier circuit or a synchronous detection circuit designed to obtain
and an arithmetic circuit configured to obtain an output representing the loss of the capacitive element to be measured, which is obtained by dividing the DC voltage of the first DC voltage by the first DC voltage.
JP1627880A 1980-02-13 1980-02-13 Measuring apparatus for loss of capacity element Granted JPS56112663A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1627880A JPS56112663A (en) 1980-02-13 1980-02-13 Measuring apparatus for loss of capacity element

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1627880A JPS56112663A (en) 1980-02-13 1980-02-13 Measuring apparatus for loss of capacity element

Publications (2)

Publication Number Publication Date
JPS56112663A JPS56112663A (en) 1981-09-05
JPS6312263B2 true JPS6312263B2 (en) 1988-03-18

Family

ID=11912072

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1627880A Granted JPS56112663A (en) 1980-02-13 1980-02-13 Measuring apparatus for loss of capacity element

Country Status (1)

Country Link
JP (1) JPS56112663A (en)

Also Published As

Publication number Publication date
JPS56112663A (en) 1981-09-05

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