JPS63121765A - Testing method for semiconductor integrated circuit - Google Patents

Abstract

PURPOSE:To easily execute highly accurate measurement by forming an exclusive test-only output having larger driving force independently of an original output, connecting the exclusive output to a LSI tester and measuring a propagation time. CONSTITUTION:An output from a inverter 4 is branched and the branched output is transmitted to the test-only output 3 through an output buffer 5. Since the branched output is passed through the circuit 5, capacity driving a load is larger than an output 2, i.e. even if an output is connected to a tester through a transmission line having large capacity, a waveform is not weakened by the capacity. The output impedance of the circuit 5 becomes smaller than the intrinsic output 2. Thereby the waveform is not weakened even by a transmission line to be a capacitive load. Consequently, a semiconductor integrated circuit performance test which may have a result approximate to a practical using state can be attained. Thereby highly accurate measurement can be easily executed.

Description

DETAILED DESCRIPTION OF THE INVENTION 0') Technical Field The present invention relates to improvements in performance testing methods for semiconductor integrated circuits. In particular, the present invention relates to a semiconductor integrated circuit testing method that can measure propagation delay time with high accuracy in a manner similar to actual usage conditions.

For example, in the case of an inverter, the propagation delay time is
This is the time from when the input signal changes until the output signal inverts.

The propagation delay time is one of the factors expressing the response speed of an element. Provides the most basic performance evaluation of semiconductor integrated circuits. Therefore, it is important to accurately measure the propagation delay time.

However, signal propagation delays also occur in transmission lines.

Transmission lines do more than simply slow the transmission of signals. Since transmission lines have capacitance, the rise and fall of the signal may be slowed down by the transmission line.

BACKGROUND OF THE INVENTION Conventionally, a dedicated test device called an LSI tester has been used to test digital integrated circuits.

FIG. 4 schematically shows the configuration of the test circuit. For the sake of simplicity, an example of an inverter gate will be explained.

FIG. 5 schematically shows the mounting state in which the IC is actually used. Figure 6 shows the input/output signals of the LSI tester, (a) is the input signal generated by the LSI tester 21, and fbl is the input signal generated by the LSI tester 21.
This is the waveform of the output signal received by the tester 22.

The driver of the LSI tester 21 generates a signal as shown in FIG. 6 fa). It can be rising or falling, but
Here, a rising input signal is shown.

This passes through the transmission line 25 and enters the input pin of the inverter 23 to be tested. Since the inverter 23 produces a signal opposite to the input, an inverted signal is output from the output. This output passes through the transmission line 26 and enters the comparator of the LSI tester 22. At this point, the signal becomes as shown in FIG. 6 rbl.

In actual use, as shown in FIG. 5, it is soldered to a printed circuit board together with other ICs 28 and 29, and signals are transmitted through short lead wires 30 and 31. The lead wire is extremely short, ranging from several meters to several meters.What we want to know by measurement is the propagation delay time of the IC when it is mounted as shown in FIG. Although the propagation delay time can be measured with an LSI tester, this is different from the propagation delay time in actual use because the measurement is performed through a long transmission path.

This poses a problem in that not only is there a delay due to the transmission path, but also that the output waveform becomes blunt.

LSI testers usually have more than 100 drivers and comparators lined up so that they can handle ICs with many pins.

Therefore, there is a limit to how short the transmission lines 25 and 26 can be made.

Since the signal passes through several tens of crn cables, there is a delay due to this. This delay is known. It is the value obtained by dividing the cable length l by the signal propagation speed V.

Let this be Td.

In Fig. 6, the difference between time T1 when an input pulse is generated from the driver and time T2 when the comparator determines whether the inverter output has changed is Tp (= T2 - Tl').
are the quantities directly given by the LSI testers 21 and 22.

The value Ts (=
Tp - Td ) is the propagation delay time of the inverter.

(1) Problems that the invention attempts to solve However, the reality is not as simple as this.

In such measurements, the sum of the transmission line capacity and the comparator capacity is connected to the output of the inverter as a load.

This capacitance is approximately 100 pF. This is a fairly large capacitance. When an IC is actually used, it is mounted on a printed circuit board, for example, but the lead wire length is several meters to several meters.
and is extremely short. It is also designed to be as short as possible.

Of course, there are lead wires C, L, etc. even in actual use. However, this is considerably smaller than C and L of the transmission line for connecting to the LSI tester. It would be possible to shorten the transmission line, but since this is an LSI tester with over 100 drivers and comparators, it is actually not possible to shorten the transmission line.

Therefore, the inverter output during actual use is as shown in Figure 7 fa.
), the output of the LSI tester will be distorted as shown in Figure 7 (bl).

This makes it impossible to accurately measure propagation delay time.

In other words, although the slope of falling and rising points is a problem as well as the delay time, measurement by the L'SI tester tends to reduce the slope.

FIG. 3 shows a conventional IC. Like lal, it simply has an input and an output. To), the input signal is T
Let's say it started up at 1. In actual use, the output waveform is T
Assume that the curve falls steeply (curve 2) at 3. However, LS
When observed with an I tester, the waveform slowly falls at T2 (curve C).

The propagation delay time Tp observed by the tester is considerably longer than the propagation delay time Ts inherent in the inverter element. Also, the waveform is distorted.

Delay time Td (== T2- Ta
), the degree of waveform distortion cannot be determined at all.

This is hardly a problem if the signal changes slowly.

However, as semiconductor integrated circuits become more sophisticated, tens of M
When signals of Hz or higher become a target, the 100 pF capacitance of the transmission line becomes a big problem.

B)) Method of the present invention In the present invention, a semiconductor integrated circuit is provided with a test-specific output having a larger driving force in addition to the original output, and this output is connected to an LSI tester to measure the propagation delay time. shall be measured.

FIG. 1 shows the configuration of an inverter gate according to an embodiment.

Input 1, inverter 4, and output 2 are originally present in a normal inverter gate. In the present invention, the output of the inverter 4 is branched, further passed through the output buffer circuit 5, and outputted to the test-only output 3.

Since it passes through the output buffer circuit 5, its ability to drive a load is greater than the original output 2. In other words, even if the tester is connected to the tester through a transmission line with a large capacity, the waveform will not be distorted by this capacity.

Therefore, the problem with the slope of the waveform is overcome.

FIG. 2 (al) shows the pins of the semiconductor element used in the present invention. A test-only output 3 is added.

Although only three pins are shown in this figure, this does not mean that there are only three pins.

If there are m input pins, there are m outputs and m test outputs. In addition, there are power supply, ground, control input terminals, etc. Since the present invention can be applied to an IC of any configuration, the number of these input signals is arbitrary.

The output buffer circuit 5 amplifies the output 2, but does not amplify the voltage waveform. The waveform of output 2 and
The waveforms of the output buffer circuit 5 must be the same.

However, the output impedance is smaller than the original output 2.

For this reason, the waveform is not blunted even by the transmission line, which is a capacitive load.

A waveform diagram is shown in FIG. 2 fbl.

Assume that the input rises at TI. Curve A is obtained by connecting an LSI tester to the test-only output 3 via a transmission line and observing the output waveform. The falling time of A is assumed to be T2.

The output when actually used is shown with a curved line. This curve cannot be seen directly. However, since the slopes of the curve A and the curve at the mouth are the same, if (T2-Ts) is known, the curve mouth can be estimated from the curve A.

The delay time (T2-Ts) between A and Ts includes Td due to the length l of the transmission path 25°26. But that's not all. Since the output buffer circuit 5 is added, there is also a delay Tb due to this.

The delay of the buffer circuit 5 can be known by separately manufacturing a circuit exactly the same as the buffer circuit and measuring the delay time between input and output.

If this is not possible, the circuit may be measured with a measuring instrument other than an LSI tester with a small load capacity, and corrections may be made.

In any case, the inherent delay Tb caused by the output buffer circuit 5 is known.

There are two disadvantages to providing the output buffer circuit 5.

(1) One is that the load on the inverter 4 increases because of the output buffer circuit 5.

However, the capacitance of the input terminal of the output buffer circuit 5 is small. Increase in capacity due to inverter load is hardly a problem.

(11) When manufacturing a semiconductor integrated circuit, an output buffer circuit and lead pins for testing must be provided in addition to the circuits necessary for the original function. However, this only slightly increases the element area and does not particularly increase the difficulty.

As described above, the disadvantage of providing the output buffer circuit 5 is not excessive.

However, there are conditions imposed on the output buffer circuit. Second
As shown in figure (bl), the slopes of the curves of Kl and (b) must be the same. Otherwise, it is not possible to estimate (b)) from h).

Therefore, the output buffer circuit must have a driving capability that can completely overcome the capacity of the transmission line.

Another is that the delay time Tb of the output buffer circuit must be constant.

E) By testing the output of the output terminal provided exclusively for effect testing with an LSI tester, it is possible to perform a performance test on a semiconductor integrated circuit that will yield results close to those under actual use. It becomes possible to easily perform high-precision measurements.

Here, the explanation is given using an inverter gate as an example. This is because the inverter gate is a basic element in a logic IC.

The present invention is also applicable to more complex digital ICs.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a diagram showing the configuration of an IC for applying the test method of the present invention. Figure 2 fat is a pin layout diagram of the IC used in the present invention, (1
)) are input and output waveform diagrams. Figure 3 (al is a pin layout diagram of a conventional IC, (b) is an input and output waveform diagram. Figure 4 is a wiring diagram when testing IC performance with an LSI tester. Figure 5 is the actual IC on the board. A plan view showing an example of implementation. Figure 6 is a waveform diagram showing changes in the input signal generated by lal driver, and (b) is a waveform diagram showing changes in the output signal detected by the comparator. Figure 7 is a waveform diagram showing changes in the output signal detected by the comparator. (a) is a waveform diagram showing the falling change during actual use, and (b) is a waveform diagram showing the falling change during LSI tester measurement. 1... Input 2... Output 3 ......Test-only output 4...Inverter 21.22...LSI tester 23...
・Inverter 25.26...Transmission line 28.29...IC

Claims (1)

[Claims] An output buffer circuit 5 which has a semiconductor integrated circuit having one or more input terminals 1 and one or more output terminals 2 and has a higher load driving capability by current amplifying the output signal of the output terminal, and the output of the output buffer circuit 5. A test-dedicated output 3 for taking out a signal is provided, and the transmission path of the LSI tester is connected to the input terminal 1 of the semiconductor integrated circuit and the test-dedicated output 3, and the output waveform of the LSI tester and the delay Td due to the transmission path known in advance are A method for testing a semiconductor integrated circuit, characterized in that the propagation delay of the semiconductor integrated circuit is measured from the delay Tb caused by the output buffer circuit 5.