JPS63121346A - Repeater - Google Patents

Abstract

PURPOSE:To securely execute a data transmission by providing preamplification head and end detection circuits, a preamplification removal circuit and a preamplification addition circuit, etc., and also providing a delay circuit which absorbs a time difference corresponding to the missing length of a preamplification part. CONSTITUTION:The peaplification part head and end detection parts 8 and 10 respectively detect the head and the end of the preamplification parts included in demodulated 2 packet data and remove 12 the preamplification part so as to transmit the output to a first in.first out FIFO circuit 6. Based on the detection signal from the circuit 8 the preamplification part addition circuit 22 adds the preamplification part generated in a preamplification part generation circuit 20 to the output from the circuit 6 by normal data length. In this case in order to absorb the time difference corresponding to the head missing length of the preamplification part, the delay circuit 9 consisting of a shift register and a multiplexer is included.

Description

DETAILED DESCRIPTION OF THE INVENTION (A) Field of Industrial Application The present invention mainly relates to intercourse, which relays data transmitted in packet units via a digital transmission path.

(b) Prior art and its problems In general, in digital transmission lines, when the transmission distance becomes long, the transmitted data attenuates along the way, making it impossible to distinguish the data, so relays restore this to the original signal level. A vessel is required.

In data transmission using this repeater, CSMA/
When there is a restriction on the transmission delay time of the entire system, such as in a CD-based local area network (LAN), real-time relay is required. Therefore, conventional repeaters of this type include a first-in first-out circuit (hereinafter referred to as FIF) between the demodulator and modulator.
The packet data demodulated by the demodulator is directly input to the FIFO circuit, and the packet data temporarily buffered in the F summer FO circuit can be taken out at a desired timing, reducing the relay delay time. A shortened method has been proposed.

Incidentally, in packet data transmitted over a LAN, a bit pattern of a certain length called a preamble part is added to a part of the header in order to synchronize the clock in the receiving circuit. Due to the various electronic circuits installed between the time when the preamble is received and the time when the preamble is received, a phenomenon occurs in which part of the preamble section is missing. However, the conventional repeater having the above configuration does not sufficiently take this point into consideration, and is configured to retransmit the received packet data as it is in real time without any processing. Therefore, when packet data with a missing preamble part is transmitted via multiple repeaters, the missing part of the preamble part is amplified.
In the end, the preamble section became too short to perform its function, causing problems such as clock synchronization in the receiving circuit.

The present invention has been made in view of such problems, and an object of the present invention is to minimize the loss of preamble portions during transmission, and to ensure data transmission.

(C) Means for Solving the Problems In order to achieve the above object, the present invention, while relaying packet data, updates the preamble part included in the packet data by a regular data length each time. It is configured so that it can be played back.

That is, the present invention includes a demodulator that demodulates packet data including a preamble section for clock synchronization transmitted from a digital transmission path, and a modulator that modulates and outputs the packet data demodulated by this demodulator. In the repeater, the repeater is provided with a FIFO circuit for correcting relay delay time errors between the demodulator and the modulator; a start detection circuit; a preamble end detection circuit that detects the end of a preamble section included in the packet data demodulated by the demodulator; and a preamble end detection circuit that detects the end of the preamble section included in the packet data demodulated by the demodulator. a preamble part removal circuit that removes the preamble part from the packet data demodulated by the demodulator; a preamble part generation circuit that generates a predetermined bit pattern of the preamble part; a preamble addition circuit that adds a preamble part generated from the preamble part generation circuit based on a detection signal from the preamble part head detection circuit to the packet data that has passed through the FIFO circuit, by a regular data length; The preamble portion removal circuit includes a delay circuit including a shift register and a multiplexer for absorbing a time difference corresponding to the missing length of the preamble portion using the detection signal output of the preamble portion end detection circuit as a reference.

(D) Effect In the repeater of the present invention, the beginning of the preamble part included in the packet data demodulated by the demodulator is detected by the preamble part head detection circuit, and the beginning of the preamble part included in the packet data demodulated by the demodulator is The ends are detected by preamble end detection circuits.

The preamble section removal circuit removes the preamble section from the packet data demodulated by the demodulator based on both detection signals from the preamble section head detection circuit and the preamble section end detection circuit. At this time, a delay circuit including a shift register and a multiplexer absorbs a time difference corresponding to the missing length of the preamble section using the detection signal output of the preamble section end detection circuit as a reference.

On the other hand, the preamble section addition circuit generates a signal from the preamble section generation circuit based on the detection signal from the preamble section head detection circuit for the packet data from which the preamble section has been removed by the preamble section removal circuit and has passed through the FIFO circuit. Add the preamble part by the regular data length.

Therefore, even if a part of the preamble part included in the received packet data is missing, it is removed and a new preamble part with the regular data length is reproduced, so there is This means that the loss of the preamble portion of the preamble section can be minimized.

(P) Examples The present invention will now be described in detail based on examples shown in the drawings.

FIG. 1 is a block diagram of a repeater according to an embodiment of the present invention. In the same figure, the symbol l indicates the entire repeater, and 2
4 is a demodulator that demodulates packet data including a preamble part for clock synchronization transmitted from the digital transmission path; 4 is a modulator that modulates and outputs the packet data demodulated by demodulator 2; 6 is demodulator 2; This is a FIFO circuit installed between the FIFO circuit 6 and the modulator 4, and while the packet data passes through the FIFO circuit 6, the relay delay time caused by the clock phase error between the transmitting station and the main repeater 1 is corrected. Ru.

Further, 8 is a preamble part head detection circuit that detects the head of the preamble part included in the packet data demodulated by the demodulator 2, and 9 is this preamble part head detection circuit 8.
This is a delay circuit that delays the detection signal from the FIFO circuit 6 by a certain time ta, and the delay time ta is set to match the relay delay time corrected by the FIFO circuit 6 described above. 1
0 is a preamble end detection circuit that detects the end of the preamble part included in the packet data demodulated by the demodulator 2.

Reference numeral 12 denotes a preamble part removal circuit that removes the preamble part from the packet data demodulated by the demodulator 2 based on both detection signals from the preamble part head detection circuit 8 and the preamble part end detection circuit 1O. This preamble part removal circuit 12 counts the reception clock given from the demodulator 2 after the detection signal is output from the preamble part end detection circuit 10 until the forecast signal is output from the control circuit 24, which will be described later. The delay circuit 15 includes a counter 16, a serial-in/parallel-out shift register 14, and a multiplexer 18 that inputs the output of the counter 16 as an output selection signal of the shift register 14.

The delay circuit 15 is for absorbing the time difference tc corresponding to the missing length of the preamble section with reference to the detection signal output of the preamble section end detection circuit IO, and is connected to the shift register 14 and the multiplexer! The length of each bit of 8 is set according to the expected dropout time of the preamble section.

Reference numeral 20 denotes a memory (R
OM). Further, 22 is a preamble section removal circuit 1.
The preamble stored in the memory 20 is determined based on the detection signal output from the preamble head detection circuit 8 via the delay circuit 9 for the packet data from which the preamble portion has been removed and passed through the FIFO circuit 6 in step 2. This is a preamble adding circuit that adds a portion of the preamble by a regular data length, and is composed of a control circuit 24 and a switching circuit 26.

The control circuit 24 has a built-in counter, and in response to a detection signal inputted from the preamble section head detection circuit 8 via the delay circuit 9, clock pulses synchronized with the transmission clock from the modulator 4 are sent to the FIFO. Circuit 6 and memory 2
Output each for 0. In addition, control gJ@Ro24
is the time t corresponding to the data length of the regular preamble part
The time obtained by subtracting the relay delay time ta from p (
tp - ta = tc), a forecast signal for stopping the counter 16 is output to the counter 16, and furthermore, after a time tp corresponding to the data length of the regular preamble part has elapsed from the time when the detection signal is given from the delay circuit 9. Outputs data output switching signal. Further, the switching circuit 26 is connected to the control circuit 24.
When a data output switching signal is applied from , the output of the memory 20 is switched to the output of the FIFO circuit 6 .

Next, the operation of the repeater 1 of the present invention having the above configuration will be explained with reference to the time chart shown in FIG.

When packet data is transmitted from the digital transmission path, the demodulator 2 outputs the packet data and reception clock as shown in FIG. 2(a). As shown in FIG. 2(a), this packet data is constructed by adding a preamble section (shaded section) to a part of the header of the data section.

The data length tb of the received preamble portion is shorter than the data length tp of the regular preamble portion due to the omission during transmission. Note that although the data length tp of the regular preamble part is a fixed time, the data length tb of the received preamble part is undefined because it depends on the degree of omission.

Further, the symbol ta in the figure is a relay delay time, and this delay time ta is also constant.

The packet data demodulated and output from the demodulator 2 is
The signal is applied to the shift register 14 and the preamble section head detection circuit 8, respectively. When the packet data is output from the demodulator 2, the preamble section head detection circuit 8 immediately detects the start position of the preamble section and outputs a detection signal. This detection signal is input to the control circuit 24 after being delayed by a predetermined time ta in the delay circuit 9 (time to in FIG. 2). When the control circuit 24 receives this detection signal, it outputs clock pulses synchronized with the transmission clock from the modulator 4 to the FIFO circuit 6 and the memory 20, respectively, in response. As a result, the bit pattern data of the preamble part stored in the memory 20 in advance is read out. At this time, since the switching circuit 26 is connected to the memory 20 side by the control circuit 24, the switching circuit 26 is connected to the memory 20 side.
The data read from 0 is given to the modulator 4 via the switching circuit 26. Therefore, after the relay delay time ta has elapsed since the demodulator 2 received the packet data, the modulator 4 starts outputting the reproduced preamble part.

On the other hand, the packet data input from the demodulator 2 to the shift register 14 is sequentially shifted toward the right side in the figure in synchronization with the reception clock, but the end of the preamble part is not detected by the preamble part end detection circuit 10. In between,
Counter 16 is inactive and therefore multiplexer 1
8 is also stopped. Moreover, since the switching circuit 26 is connected to the memory 20 at that point, the input data is pushed out of the shift register 14 and discarded.

Therefore, during that time, data of a new preamble section read from the memory 20 is output from the modulator 4 instead of the received preamble section.

Next, when the preamble section end detection circuit 10 detects the end of the preamble section of the received packet data (at time to in FIG. 2, the circuit 10 outputs a detection signal, and the detection signal clears the counter 16. This clears the counter 16 and starts counting the received clock input from the demodulator 2.Then, the count output is sent to the multiplexer 18 as an output selection signal of the shift register 14. Therefore, when the data part of the packet data is input to the shift register 14, this data part is sequentially shifted to the right in synchronization with the reception clock.
is switched in response to the count output of the counter 16, so the multiplexer 18 always outputs only the first bit of the data portion.

On the other hand, the control circuit 24 includes a preamble section head detection circuit 8.
After inputting the detection signal from the normal preamble part through the delay circuit 9, the relay delay time ta is calculated from the data length tp of the regular preamble
(tp-ta=tc) (this corresponds to the missing length of the preamble part of the input packet data) (at time tJ in Figure 2, the forecast signal is transferred to the set terminal of counter I6. SET.This sets the counter 16 output to the count value at the time the forecast signal was input, and accordingly, the connection between the multiplexer 18 and the shift register 14 is fixed.Therefore, the packet data The data section is sequentially given to the FIFO circuit 6 from the beginning via the multiplexer 18.The data section input to the FIFO circuit 6 is delayed by the relay delay time ta to correct the clock phase error. Further, the control circuit 24 inputs the detection signal from the delay circuit 10 and outputs it after the time period corresponding to the data length tp of the regular preamble part has elapsed (the second
At time ts in the figure, the data output switching signal is switched to the switching circuit 26.
Output to. In response to this data output switching signal, the switching circuit 26 switches the memory 20 output to the FIr'0 circuit 6 output. As a result, the output timing from the FIFO circuit 6 and the switching timing of the switching circuit 26 match, so that the modulator 4 outputs the preamble portion having the regular data length tp as shown in FIG. 2(b). Packet data consisting of a series of data parts will be output.

In this way, the preamble part included in the received packet data is removed and a new preamble part is reproduced, so no matter how many bits are missing in the received preamble part, it is irrelevant (with the regular data length tp). After the preamble section is added, it is output from the modulator 4. Therefore, even when performing long-distance transmission, clock phase synchronization can be achieved reliably, and the relay delay time ta to be corrected by the FIFO circuit 6 is , even if the data length of the preamble section varies, it is only necessary to correct the clock phase error of a fixed length.

(F) Effect As described above, according to the present invention, while the packet data is being relayed, the preamble part included in the packet data is regenerated by the regular data length each time, so that The loss of the preamble portion is reduced to a minimum, and excellent effects such as reliable data transmission are exhibited.

[Brief explanation of the drawing]

The drawings show an embodiment of the present invention, and FIG. 1 is a block diagram of a mid-wall device, and FIG. 2 is a time chart for explaining the operation of the repeater. l...Repeater, 2...Demodulator, 4...Modulator, 6
... FIFO circuit, 8... Preamble section head detection circuit, IO... Preamble section end detection circuit, 12.
. . . Preamble section removal circuit, 20 . . . Preamble section generation circuit (memory), 22 . . . Preamble section addition circuit.

Claims (1)

[Claims] (1) It includes a demodulator that demodulates packet data including a preamble section for clock synchronization transmitted from a digital transmission path, and a modulator that modulates and outputs the packet data demodulated by the demodulator, and In a repeater in which a first-in/first-out circuit for correcting relay delay time errors is provided between the demodulator and the modulator, a preamble detecting the beginning of a preamble part included in packet data demodulated by the demodulator; a preamble end detection circuit that detects the end of the preamble part included in the packet data demodulated by the demodulator; and a preamble end detection circuit that detects the end of the preamble part included in the packet data demodulated by the demodulator; a preamble part removal circuit that removes a preamble part from packet data demodulated by a demodulator; a preamble part generation circuit that generates a predetermined bit pattern of the preamble part; Preamble addition that adds a preamble part generated from the preamble part generation circuit based on a detection signal from the preamble part head detection circuit to the packet data that has passed through the first-in/first-out circuit by a regular data length. The preamble portion removal circuit includes a delay circuit including a shift register and a multiplexer for absorbing a time difference corresponding to a missing length of the preamble portion with reference to the detection signal output of the preamble portion end detection circuit. A repeater featuring: