JPS63121315A - Digital timing signal generator and voltage regulating circuit - Google Patents

Abstract

A digital timing signal generator and voltage regulator circuit is provided. In one embodiment the circuit includes a delay line. The delay line operating voltage is derived from digitally encoded power/timing signals transmitted by an isolated logic control circuit. The delay line receives and propagates the digitally encoded signals. Outputs of selected stages of the delay line are tapped to provide multiphasic timing signals for use by associated logic circuits. A plurality of gates having inputs connected to various stages of the delay line receive selected timing signals as they propagate along the delay line. Increases in the operating voltage cause the selected timing signals to sequentially activate the gates. The output of each activated gate then goes high and current flows through an associated load resistor connected between the output of the gate and ground to continuously load the supply voltage and thereby regulate it. In variations of this embodiment, two and three levels of gates and load resistors are provided to progressively load the supply voltage and thereby provide additional regulation thereof. In another embodiment, a ring-oscillator comprised of CMOS inverters generates the timing signals. The ring oscillator consumes current in approximately a square relationship with increases in its supply voltage and thereby regulates the voltage.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates generally to timing signal generators, and more particularly to such circuits in which timing signals are also used to control regulation of supply voltages.

The invention particularly relates to circuits in which signals generated by a timing signal generator are used to automatically control the activation of loads used to regulate the supply voltage.

BACKGROUND OF THE INVENTION Many digital logic circuits used today require a multiphase timing signal source for operation. It is known that ring oscillators and delay lines are inexpensive sources of such timing signals, and therefore these timing signal generators are widely used in both separate and integrated logic circuits.

It is also known that the transmission ratio of such timing circuits changes predictively with respect to changes in the supply voltage when a CMOS device, such as a CMOS inverter, is configured. It will therefore be understood that the interval between timing pulses, or the frequency of such pulses, represents the supply voltage level and can be used in known voltage regulators as a control parameter for adjusting the supply voltage. For example, Hashimoto US Patent No. 435872
Please refer to 8.

[Problems to be Solved by the Invention] However, conventional voltage regulation circuits are complex and expensive. Additionally, in the case of integrated circuits, manufacturing additional logic components uses valuable board space that could otherwise be used.

In addition, the fine passive circuits used today require that the power transmitted by the control circuit located away from the operating power be
It is derived from timing signals. Such circuits are often found, for example, in microscopic transponder systems, injectable medical devices, and portable data retrieval devices. U.S. Patent No. 3859624 Kr1ofsky et al. 4408608 Daly et al. 453398
8Daly Others.

Please refer to 4196418Kip and others. Typical circuits of this type operate at low power and are designed to take up minimal space. Therefore, it is particularly desirable in those types of circuits to regulate the operating voltage derived from the power/timing signal without requiring additional voltage regulation circuitry.

Accordingly, it is an object of the present invention to provide a timing signal generator circuit that generates multiphase timing signals while adjusting the supply or operating voltage of the circuit.

It is another object of the present invention to provide a circuit that regulates operating voltage without the need for conventional voltage regulation circuitry, and which can also be used with additional voltage regulation circuitry.

It is a further object of the invention to provide a circuit which is simple in design, construction and operation, has a large degree of freedom and can be conveniently and inexpensively manufactured in integrated circuit form.

SUMMARY OF THE INVENTION It is an object and concomitant effect of the foregoing that a timing signal generator generates a timing signal having a timing relationship related to the level of the operating voltage, and that the timing signal generator generates a timing signal having a timing relationship related to the level of the operating voltage; This is achieved by providing a voltage regulation circuit and a digital timing signal generator that broadly form a regulation circuit connected to the timing signal generator responsive to the timing relationship of the timing signal loading the voltage regulation circuit.

In one aspect, a timing generator transmits a signal at a rate related to a level of a supply voltage to generate at least one timing signal.

When the timing relationship is less than a predetermined minimum value, the gate is activated to selectively load the supply voltage to adjust the supply voltage.

In another aspect, a delay line transmits a signal to generate at least one timing signal. A plurality of gates having inputs connected to selected stages of the delay line receive selected timing signals.

When the signals overlap, the gate is activated and the load connected to it loads the supply voltage to regulate the supply voltage.

In a further aspect, the circuit continuously transmits signals to generate at least one signal. The circuit is arranged and configured to consume current approximately squarely with respect to increases in the supply voltage in order to regulate the voltage.

[Example 1] Referring to the drawings, FIG. 1 shows a timing signal generator, such as a delay line 5, and a combined delay line encoding and voltage regulation receiving the generated timing signal and responsive to the timing signal. 6 shows an embodiment of the invention including a container 6;

In the present invention, the delay line 5 and the voltage regulator 6 are fabricated together with the signal sensing and power supply circuit 2 and the various logic circuits 4 in an integrated circuit chip (tC). The IC is conveniently fabricated using the CMO8 fabrication process known to those skilled in the art.

In one preferred form, the IC receives its operating power from external control logic 7 rather than being powered from its own power supply. In this form, the control logic circuit 7 includes known circuitry for generating and transmitting the power/timing signal VIN at the output terminal 8. The power/timing signal VIN consists of a carrier signal modulated with digital pulses having a predetermined rated vibration, amplitude, and duty cycle. Such control logic circuits are well known and do not constitute the gist of the present invention. See, for example, the circuits described in the various US patents mentioned above.

The power/timing signal VIN is input to the signal input terminal 8a on the IC. The output 8 of the control logic circuit 7 and the signal input terminal 8a of the IC are preferably isolated by inductive coupling, although capacitive, resistive or optical coupling can also be used. However, whatever coupling shape is used, it should rather have a relatively high resistance component compared to the input resistance of the IC. In the case of such inductive coupling, for example, low efficiency coupling is preferred.

The signal input 8a is connected to the input of the signal detection/power supply circuit 2. The signal detection and power supply circuit 2 detects the digital pulses on the modulated carrier and the continuous output corresponding to the digital pulses on the line 3. At the same time, the signal detection and power supply circuit 2 derives from the modulated carrier a supply or operating voltage VREG, which is connected to the delay line 5 on line l, to the voltage regulator 6 and to the supply inputs of the various logic circuits 4.

The signal detection and power supply circuit 2 is a known circuit and is well known to those skilled in the art. One form of circuit specifically designated for use with the present invention was published by the distributor on January 13, 1986.
U.S. patent application no.

No. 818,469.

A delay line 5 receives the digital pulses on line 3 and emits a multiphase timing signal therefrom. Timing signals are received and used by various logic circuits 4 to perform their associated logic functions.

The timing signal is also received by a voltage regulator 6 which encodes the timing signal and adjusts the operating voltage at a predetermined load to reduce or adjust it, if necessary, up to a predetermined rated value. Apply VREG. The delay line also goes to the input 9 of the control logic 7, to the output terminal 9
One of the digital timing signals on a can be output.

Output 9a and input 9 are rather isolated as described above. Preferably, the digital timing signals on lines 9 and 9a can be split in an isolation manner with the power/timing signals on lines 8 and 8a. Control logic 7 is line s
Determine the delay between the output pulse on output 8 and the timing pulse on input 9 as an indication of the actuation voltage VREG, and use this data to determine the width of the encoded digital pulse on output 8 or the magnitude of the power/timing signal VIN. Used to provide additional adjustment by changing.

Control logic 7 may also use the signal on connection 9 to adjust the frequency of the encoded digital pulses on output 8.

FIG. 2 illustrates a delay line timing signal generator and first column voltage regulation circuit according to one embodiment of the invention. Delay line 5 is not fully shown due to space limitations, but lO~
It consists of 60 CMOS inverters connected in series. Delay line 5 generates multiphase timing signals.

Representatives of those signals are inverters 10, 14, 17, 1
9. Signal T with each different phase at the output of 24
I.

T5. T8. TIO, T15.

Up to gates 61-102 including resistors 103-144,
A first row of voltage regulators 6 is provided. Each gate 61-102
each has a corresponding resistor 103-144 connected between the output terminal of the gate and ground. Gate 61-1
The inputs of 02 are connected to the delay line 5 in such a way that they are distributed along its length and are activated sequentially.

The inputs are also connected to the delay line 5 in such a way that the input signals to each gate have the same delay relationship between the gates so that all of the gates are activated or deactivated with the same supply or activation voltage level. Activated sip.

Therefore, one input of the ΔN'DNOR gate 6 is connected to the input 3 of the delay line 5 at the input of the inverter IO. The other input of the ANDNO gate is inverter 1
It is connected to the output of 9.

The inputs of NOR gate 62 are connected to inverters 10 and 20, respectively.
are connected to the outputs of each. The inputs of the ANDNO gates are connected to the outputs of inverters 11 and 21, respectively. The inputs of the N0rt gates 64 are connected to the outputs of inverters 2 and 22, respectively, and in turn the inputs of the last AND gate 101 are connected in this way to the outputs of the inverters 2 and 22, respectively.
and 59, and the input of the last NOR gate 102 is connected to the outputs of inverters 50 and 60.

From the above, there is a relative delay of 10 inverters between the input signals to each gate. Also, since the inputs of gates 61 to 102 are distributed along the length of delay line 5, each input signal to each gate except gate 10 is equal to one signal with respect to the corresponding input signal to the previous gate. delayed by an inverter. In this embodiment, the gates connected to the outputs of the odd stages of the delay line 5, for example gates 62, 64, 66, 68 up to the gate 102, are NOR gates, while the gates connected to the outputs of the even stages of the delay line 5 are NOR gates. For example, gates 61, 63, 65°67 up to gate 101 are AND gates.

Preferably, only one digital pulse travels through the delay line 5 at a given time. It is also preferred that the delay between successive pulses being transmitted through the delay line 5 is a minimum value so that the amount of time during which the force actuation voltage is not regulated is minimized. Their operating performance depends on the required rated operating voltage, the predetermined frequency, and the per-gate transmission delay of the particular equipment selected for use, e.g., delay lines 5 with appropriate lengths.
obtained by selecting an appropriate number of stages.

These are clear from various manufacturers' data sheets as known to those skilled in the art. Typical operating parameters that may be assumed in the following description are: ! Rated pulse frequency of 00 [Hz and 2.5
V is the rated circuit operating voltage. At the selected rated operating voltage, the typical propagation delay of a typical CMOS inverter is about 100 ns. Therefore given 100Kf
(To ensure that at a rated pulse frequency of z, only one pulse travels through the delay line 5 at any time, the delay line 5 must have at least 5'' inverters as shown in the figure.

The nominal duty cycle of each encoded digital pulse is determined by the relative delay time between the respective input signals of gates 61-102. Thus, for the nominal values mentioned above, a per-gate propagation delay of approximately 100 ns and a first
The ten inverter delays between input signals shown in the figure correspond to digital pulses with a nominal on-time of lμs. When the magnitude of the input signal VIN is below its rated value, modest transformations in the width of the pulses have no effect on VREG. When the input signal VAN is at or near its rated level, e.g. the level at which gates 61-102 are activated, an increase in the on-time of the pulse will reduce VREG, while a decrease in the on-time will have no effect. do not. When the input signal VIN exceeds its rated value and is within a range that requires adjustment, an increase in pulse width will reduce V REG, while a decrease in pulse width will reduce VR
Increase EG.

In the above, both change approximately linearly. If it is required to widen or shorten the nominal on-time of the pulse, gate ei-i.

The number of delay gates between the input signals to 2 is relatively increased or decreased as appropriate for best operation as described above. Another consideration in selecting an appropriate rated duty cycle is that the duty cycle affects the cycle-by-cycle energy delivered to the circuit.

Furthermore, the longer the digital pulse is in terms of time, the longer the length t1, the better the operating voltage can be controlled, and the control resolution improved.

Resistors 103-144 are selected based on the particular application of the circuit embodying the invention. In order for the circuit to provide sufficient regulation of the operating voltage, when the gates 61-102 are activated, the circuit will draw most of the current into the portion of the passive circuit that is combined with said circuit. Resistance must be chosen. However, since the delay line encoding and voltage regulation circuit 6 apparently does not draw as much current, it reduces VIN to a level such that the combined logic circuit 4 is inactive. Within those parameters, the particular values of resistors 103-144 are the input impedance of the combined circuit.

The selection is based on the number of resistors used and the total load required to achieve the required adjustment.

For example, resistors with values in the range 500 to 2000 ohms have been found suitable.

In operation, each digital pulse transmitted by the logic control circuit 7 is input to the inverter IO of the delay line 5. The pulse is inverted and delayed by each inverter while propagating through the delay line 5. The output pulses of stages IO-51 are input to the first terminals of corresponding gates 61-102, respectively. The outputs of even stages are non-inverted pulses, while the outputs of odd stages are inverted pulses. The output pulses of stages 19-60 are input to the second terminals of the corresponding gates 61-102. Therefore, a logic high pulse input to inverter lO is also input to one terminal of AND gate 61. The same uninverted signal delayed by 10 inverters appears at the output of inverter 19 and is connected to the other input terminal of AND gate 61. Similarly, the inverted pulse at the output of inverter 10 is input to one terminal of NOR gate 62.

The same inverted pulse delayed by the ten inverters is output by inverter 20 to the other terminal of NOR gate 62. The same goes for the remaining gates 63-1
Applies to 02 inputs.

As long as the control logic circuit 7 continues to transmit VIN with encoded digital pulses at the rated frequency and duty cycle and with an appropriate amplitude to maintain the operating voltage VREG of the delay line 5 at the rated value, the gate There is no overlap between delayed and undelayed pulses at input terminals 61-102. In other words, for even stages, until the time when the delayed logic bipulse reaches the second input terminal of the corresponding AND gate,
An undelayed pulse on the first input terminal changes state and the AND gate is not activated. The same result occurs for the inverted pulses generated by the NOR gates corresponding to the odd stages. as a result,
- No current flows to ground through the resistors 103-144.

When the amplitude of the power/timing signal VIN transmitted by the control logic circuit 7 increases, the operating voltage VREG increases and the propagation delay of the delay line inverter IO~60 decreases correspondingly. When the actuation voltage V REG increases, the propagation delay is such that the delayed pulse reaches the corresponding second input terminal of gate 61-102 before the undelayed pulse on the first input terminal changes state. Decrease in time. In other words, the pulses overlap at the input to the gate. When this occurs, the outputs of gates 61-102 go high and current flows to ground through the corresponding resistors 103-144. In this way, power is supplied to the logic circuit 7. Preferably, when the gates 61-102 are activated, the voltage regulation circuit 6 conducts the maximum amount of current provided by the power supply of the control logic circuit. In this manner, circuits embodying the invention essentially operate at an operating voltage V
Adjust or reduce the level of REG.

As the amplitude of the transmitted power/timing VIN continues to increase, the total overlap between undelayed and delayed pulses increases correspondingly. As a result, the adjustment circuit 6
delivers power over an increasing proportion of each pulse.

Furthermore, as delayed and undelayed input pulses become increasingly overlapping, successive gates become activated simultaneously.

Since the load resistors connected to the outputs of their gates are in parallel, the total resistance present at the operating voltage is reduced and more voltage is applied. This preferred embodiment provides progressive voltage regulation as a function of the level of operating voltage.

When the amplitude of VIN stops increasing, the degree of overlap and rate of each pulse being applied also stops increasing. During this equilibrium state, voltage VREG will be slightly higher than its rated value. When the amplitude of VIN is decreased, the degree of overlap applied and the proportion of each pulse increases such that there is no longer any overlap between undelayed and delayed pulses, VIN.
The rated value of REG is likely to be around and decrease accordingly until some point.

When previously modified, the transmission of pulses through the delay line 5 will be fed back from the output of the inverter, such as the inverter 27 to the input 9 of the control logic circuit 7. The control logic circuit 7 can determine the value of the delay of the delay line by measuring the interval between the output and input pulses of lines 8 and 9, for example by using known edge-actuated counters, respectively. This interval is equal to the operating voltage V
As a function of REG, control logic 7 can use the delay information to provide additional voltage adjustment if needed or required. For example, by changing both the encoded pulse width and the transmitted amplitude.

Since the signal on the first second input terminal of all gates 61-102 has the same number of delay gates between them, all of gates 61-102 are activated at the same supply voltage level. Ru. However, since the inputs of gates 61-102 are distributed along the length of delay line 5,
The gates are activated sequentially rather than simultaneously. As a result, a preferred circuit embodying the invention has gate 61
When ~102 is activated, a large amount of current cannot flow instantaneously, but rather, power is continuously supplied. Such a configuration may minimize the possibility of sudden rises or falls in the output of the power supply.

FIG. 3 illustrates a delay line timing signal generator and second column voltage regulation circuit in accordance with another preferred embodiment of the invention. Delay line! 45 consists of inverters 150 to 200 which are numbered sequentially from left to right in the park and are connected in series. Typical timing signals TI, T5. T8. T
IO and T15 are inverters 150, 154, 157, 159 and 1, respectively, like delay line 5 in FIG.
64 outputs. Second row voltage regulator 1
46 is the first of the combined load resistors 243 to 284 and gates 201 to 242 numbered sequentially from left to right in the park.
Contains the second level. Due to space limitations, not all inverters and first level gates and load resistors are shown. Gates 201-242. Inverter 150~200 and load resistor 243~284
are gates 61 to 102 in FIG. Inverter lO~60
and correspond to each of the load resistors 103-144 in a similar manner and are interconnected in exactly the same manner as described above with respect to FIG.

In addition, the second column of voltage regulators 146 includes load resistors 325-364 that correspond to the second level of gates 285-324 sequentially numbered from left to right in the garden. Due to space limitations, not all second level gates and load resistors are shown. resistance 325
-364 are connected between the outputs of gates 285-324 and ground, respectively. Similar to the first row of regulators in FIG. 2, gate 323. Gates 285, 287 to the end
．． The gates in order 289 are AND gates and have inputs connected to the outputs of even stages of delay line 145. The gates in the order of gates 286 and 288 through the end of gate 324 are NOR gates with inputs connected to the outputs of the odd stages.

In contrasting the delay of 10 gates between the input signals to each of the gates 201-242 at the first level, the input terminals of the gates 285-324 at the second level are connected to the inverters 150-200. Because they are connected, there is a delay of 12 gates between the input signals. Thus, for example, the input terminal of the first gate 285 is connected to the input of the inverter 150 and the output of the inverter 161. The input terminal of the second gate 286 is connected to the outputs of inverters 1.50 and 162.

The input of gate 287 is connected to the outputs of inverters 151 and 163, and so on, and the input of the last gate 324 is connected to the outputs of inverters 188 and 200.

In the circuit of FIG. 3, the first level gate 20
1-242 are activated to power the control logic circuit 7 with a first voltage level that exceeds the rated value of the operating voltage VREG as described above with respect to the circuit of FIG. The second level gates 285-324 are activated at a second higher voltage level to additionally apply power and inhibit increases in the operating voltage VREG. Gates 201 to 24 on the first and second levels
The voltage level that causes activation of gates 285-324 depends on the selected rated operating voltage value and the inverter's propagation delay and the number of gates with the selected delay between the gate input signals. The greater the delay selected, the greater the voltage level required for activation. In the embodiment of FIG. 3, for example, the difference between the first and second level input signal gates is only two gate delays. Accordingly, the second level gates 285-324 are progressively activated with input voltage levels only slightly greater than the input voltage levels required to activate the first level gates 201-242.

FIG. 4 illustrates a delay line timing signal generator and third column voltage regulator in accordance with yet another preferred embodiment of the invention. The delay line 375 connects inverters 400 to 450, which are numbered in series from left to right in the park.
It is equipped with Typical timing signals TI, T5. T
8. TIO and T15 are inverters 400, 404,
407 and 409 are supplied from the output of 414. The third column of voltage regulators 376 includes load resistors associated with three levels of gates numbered consecutively from left to right at each level in the garden. Not all gates, resistors, and inverters are shown due to space limitations.

The first level includes gates 451-492 and associated load resistors 493-534 connected between the outputs of gates 451-492 and ground, respectively. The second level includes gates 535-574 and load resistors 575-614 connected between the outputs of gates 535-574 and ground, respectively. The third level includes gates 620-657 and gate 6, respectively.
It includes load resistors 658-695 connected between the outputs 20-657 and ground.

First level gates 451-492 and load resistance 4
93 to 534 are the first level gates 201 to 242 and load resistors 243 to 284 of the circuit in FIG. 3, and the first level gates 61 to 102 and load resistors 103 to 144. Second level gates 535-574 and load resistors 575-614
are the second level gates 285 to 285 of the circuit of FIG.
324 and the load resistances 325 to 364. 1
Gates 451-49 of the second and second levels respectively
2 and gates 535 to 574 and their respective load resistances 4
93-534 and load resistors 575-614 are interconnected with delay line 375 in exactly the same manner as their corresponding devices described above with respect to FIGS. 1 and 3.

The gates 620-657 of the third level are interconnected by the inverters 400-450 of the delay line 375, so that the digital pulse signals between the respective first and second input terminals of the gates 620-657 are There are 14 gate delays. In this way, for example, the input terminal of the first gate 620 is the input terminal of the inverter 400 and the input terminal of the inverter 413.
connected to the output of Second gate 62! The input terminals of are connected to the outputs of inverter 400 and inverter 4!4. The third input of gate 622 is connected to the outputs of inverter 401 and inverter 415,
The following connections are made in the same manner, and the last gate 6570 input is connected to the outputs of inverter 436 and inverter 450. gate 620 to the end of gate 656,
The gates in order 622.624 are AND gates with inputs connected to the outputs of the even stages of delay line 375. and gate 621 to the end of gate 657
．． The gate in order 623 is a NoR gate and has an input connected to the output of the odd stage of delay line 375.

In the circuit of FIG. 4, the first level gate 45
-1 to 492 are activated to apply power at a first voltage level above the actuation voltage. The second level gates 535-574 are activated to apply additional power at the second slightly higher voltage level. The delay between the input pulses to the third level gates 620-657 is the same as that of the second level gate 53.
Since the delay between the input pulses to 5-574 is two gates greater, the third level gates 620-657 are
It is activated at a third voltage level that is slightly greater than the level required to activate the gates 535-574 of the third level. The three level adjustment thus provides more advanced voltage adjustment than the first and second level implementations.

The preferred two- and three-row regulator embodiments are further advanced by reducing the value of the load resistance at each level. Thus, the third level load resistance has a lower value rather than the second level load resistance which has a lower value than the first level load resistance. In this configuration, the second and third level load resistances apply more power than the first load resistance.

As a result, progressive adjustments can be obtained by very simply activating second and third level gates.

A preferred variation in the basic form of the circuit embodying the invention is shown in FIG. As shown, the gates 752 to 793 and their corresponding load resistors 793 to 834, numbered consecutively from left to right in the garden, are connected to the delay line 700.
1, comprising a first bank of voltage regulators which are interconnected and operate in the same manner as described above with respect to FIG. However, some of the series connected inverters making up the delay line 700 in a preferred variant are NAN
It has been replaced by a D gate. Specifically, with reference to FIG.
5,747,749 and 751. Thus, the last 11 stages of delay line 700 are alternately NAND gates and inverters. Each NAND
One input of gates 741, 743, 745, 747, 749 and 751 is connected to each preceding inverter 7.
40° 742, 744, 746, 748 and 750 outputs. Each NAND gate 741°74
The other inputs of 3.745, 747, 749, and 751 are connected to input 3 of delay line 700.

In this example, the preceding power pulse is connected to delay line 70.
If a power pulse were input to the beginning of delay line 700 before it had fully propagated through the 0 end, the previous power pulse would be extinguished by keeping the output of the NAND gate low. , the power pulse cannot activate any of the last 11 gates 782-793.

This modification compensates for variations in the frequency of the power pulses transmitted by the control logic circuit 7 and allows the circuit with the invention to be used over a wider operating range.

Another variation of the invention is to utilize a CMOS ring oscillator as shown in FIG. 6 in place of the timing signal generator described above and the voltage regulation circuit described above. It has been found that a ring oscillator consisting of a plurality of CMOS inverters will consume approximately square law current, at least for changes in operating voltage over the typical operating range of a CMOS device. In other words, if the operating voltage doubles, the current will be dissipated by ring oscillator 900 approximately four times as much.

However, it will be appreciated that a ring oscillator 900 with the same number of stages as some of the preferred circuits described above will not consume nearly as much current beyond normal operating ranges as the gates and load resistors of the circuits described above will consume. It should be. Therefore, ring oscillator embodiments may only be useful as regulators in circuits with lower current consumption. In a larger circuit, for a ring oscillator,
In order to carry enough current to have a proper regulating effect, the ring oscillator must have a greater number of stages than the embodiments described above.

What has been described are various aspects of various digital timing signal generator and voltage regulation circuit embodiments of the invention. It will be understood that the foregoing description and accompanying drawings are exemplary only and are not intended to limit the scope of the invention as defined by the appended claims. Various modifications and changes to the preferred embodiments will be apparent to those skilled in the art. Such modifications and changes may be included. However, changes in the number or length of delay line stages, changes in the type and number of gates containing delay lines and voltage regulators, changes in circuit elements and ratings of various parameters, interconnections of basic elements, etc. changes, and without limitation to any other. Such changes and modifications may be made without departing from the spirit and scope of the invention. Therefore,
All such changes and modifications and all other equivalents are included within the scope of the appended claims.

[Brief explanation of the drawing]

FIG. 1 is a block diagram illustrating a preferred means of using a delay line in a timing signal generator and voltage regulation circuit embodying the invention; FIG. 2 is a block diagram illustrating a delay line timing signal comprising one preferred embodiment of the invention; FIG. 3 is a schematic diagram illustrating details of the generator and voltage regulation circuitry of the first column; FIG. FIG. 4 is a detailed schematic diagram of a delay line timing signal generator and third column voltage regulating circuit according to yet another preferred embodiment of the invention; FIG. 1 is a schematic diagram illustrating details of a delay line timing signal generator and a first column voltage regulation circuit according to the invention which facilitates erasing the signal passing into the "end" of the delay line when received at the "head"; FIG. Fig. 6 is a schematic diagram of a ring-shaped oscillator consisting of an alternative embodiment of the invention. 2... Signal detection/power supply circuit, 4... Logic circuit, 5...
...delay line, 6...delay line encoding and voltage regulator,
7...Control logic.

Claims (19)

[Claims] (1) means for generating a timing signal having a timing relationship related to the level of the combined actuation voltage;
and means connected to said generating means for applying said actuation voltage to adjust said actuation voltage in response to a timing relationship. (2) The means for generating the timing signal comprises propagation means for transmitting the signal to generate the timing signal, the means having a ratio of transmission related to the level of the operating voltage. The digital timing signal generator and voltage regulation circuit described in Section 1. (3) The propagation means is comprised of a delay line.
The circuit described in section. (4) applying means is connected to said generating means for receiving said timing signal, and gate means is activated when the timing relationship between said signals is less than a predetermined minimum value; 2. A circuit as claimed in claim 1, further comprising load means connected to said gate means to load said operating voltage when said gate means is activated. 5. The circuit of claim 4, wherein the gate means and the load means are arranged to progressively load the operating voltage when the operating voltage exceeds a predetermined value. (6) said gating means comprises a plurality of gates having a plurality of levels of gates having inputs connected to said generating means, each level of the gate being activated with a different predetermined value; Claim 4 comprising a plurality of levels of loading means corresponding to said plurality of levels.
The circuit described in section. (7) a transmission means for receiving said timing signal and said timing signal offset by a timing interval determined by said transmission ratio of said method of transmission, and between said signal and said offset signal; 2. A gate means which is activated when the timing interval of is less than a predetermined value, and a load means connected to said gate means so as to apply said actuation voltage when said gate means is activated. The circuit described in range 2. (8) The circuit according to claim 7, wherein the gate means and the load means are arranged to progressively apply the operating voltage when the operating voltage exceeds a predetermined value. (9) a delay line having a plurality of stages for generating timing signals with a timing relationship related to the level of the supply voltage, and connected to selected stages of said delay line for receiving selected timing signals; a plurality of gates having an input and activated when the selected signals overlap; and the plurality of gates for applying the supply voltage when the gates are activated to adjust the supply voltage. and a plurality of load resistors connected to the output of the gate of the digital timing signal generator and voltage regulation circuit. (10) having a plurality of levels of said gates and a corresponding plurality of levels of said load resistors, the input of each level of gates being connected to a selected stage of said delay line, and each level of gates having a plurality of corresponding levels of said load resistors; 10. The circuit of claim 9, which is activated at different predetermined values of the voltage. (11) The circuit according to claim 9, wherein the delay line includes means for preventing transmission of one or more signals. (12) a remote power source, a transmitter for digitally transmitting an encoded power/timing signal, and a digital logic circuit having logic circuitry for receiving the encoded signal, from which an operating voltage is applied; said encoded signal for generating a timing signal for use by said circuit in a system of said circuits also having logic means for deriving said encoded signal and performing selected functions under control of said encoded signal. a delay line having a plurality of stages for receiving and transmitting a digital signal, the timing signal having a timing relationship related to the level of the actuation voltage, and the delay line receiving a selected timing signal. a plurality of gates having inputs connected to selected stages of the gates, the gates being activated when the selected timing signals overlap, and the gates being activated to adjust the operating voltage; Digital timing signal generator and voltage regulation circuit, characterized in that it comprises a plurality of corresponding load means connected to the output of said gate for applying said power supply at the time. 13. The system of claim 12, further comprising means for preventing said delay line from transmitting more than one digital signal at the same time. (14) having a plurality of levels of gates and a corresponding plurality of levels of load means, the input of each level of gates being connected to a selected stage of said delay line, and each level of gates having a different level of said operating voltage; 13. The system of claim 12, which is activated at a predetermined level. 15. The system of claim 12, wherein the plurality of gates have inputs connected to selected stages along which the delay line is divided, and the gates are activated sequentially. (16) powered by an actuation voltage that continuously transmits a signal for generating at least one timing signal, and consuming a current that increases in response to an increase in the actuation voltage to regulate the actuation voltage; A digital timing signal generator and voltage adjustment circuit characterized by comprising the above means. 17. The circuit of claim 16, wherein said means consumes a current that increases approximately squarely with an increase in said operating voltage. 18. The circuit of claim 16, wherein said means comprises a ring oscillator having a plurality of CMOS gates. (19) In a circuit having a ring oscillator that generates at least one timing signal and a power supply for supplying an operating voltage, generated by the power supply having an approximately square relationship with respect to an increase in the operating voltage in order to adjust the operating voltage. A digital timing signal generator and voltage regulation circuit comprising the ring oscillator having a plurality of CMOS gates consuming a current of.