JPS63120434A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPS63120434A JPS63120434A JP26623786A JP26623786A JPS63120434A JP S63120434 A JPS63120434 A JP S63120434A JP 26623786 A JP26623786 A JP 26623786A JP 26623786 A JP26623786 A JP 26623786A JP S63120434 A JPS63120434 A JP S63120434A
- Authority
- JP
- Japan
- Prior art keywords
- wiring
- electrode
- test
- layer
- testing
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims description 11
- 239000010410 layer Substances 0.000 claims abstract description 34
- 238000012360 testing method Methods 0.000 claims abstract description 28
- 239000011229 interlayer Substances 0.000 claims abstract description 10
- 239000000523 sample Substances 0.000 claims abstract 2
- 238000010586 diagram Methods 0.000 abstract description 3
- 238000000034 method Methods 0.000 abstract description 2
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 15
- 229910052782 aluminium Inorganic materials 0.000 description 15
- 239000004020 conductor Substances 0.000 description 1
- 239000000284 extract Substances 0.000 description 1
- 239000000463 material Substances 0.000 description 1
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
この発明は多層配線の最上層配線以外の配線の電気信号
を取り出し、開発時にテストが行えるようにした半導体
装置に関するものである。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor device in which electrical signals from wiring other than the top layer wiring of a multilayer wiring can be extracted and tested during development.
第３・４図は、従来の二層アルミ配線を用いテストのた
めパンシベーションを行っていない半導体装置の平面図
および断面図であり、図において（１）は第二層アルミ
配線、（２１はＩｌ＋と電気的に接続されていない第−
層アルミ配線、１３）は１１】と電気的に接続されてい
る第−層アルミ配線、）４１は＋１１と（３）を結ぶス
ルーホール、＋５１は山と（２１全電気的に絶縁する絶
縁層、＋６１ｔ／ｉこの半導体装置における上記部分よ
り下にある回路部分、１７）は＋１１に接帥させ電気信
号を取り出すだめの針を示している。Figures 3 and 4 are a plan view and a cross-sectional view of a semiconductor device that uses conventional two-layer aluminum wiring and is not subjected to pansivation for testing. - which is not electrically connected to Il+
layer aluminum wiring, 13) is the -th layer aluminum wiring that is electrically connected to 11],) 41 is a through hole connecting +11 and (3), +51 is a peak and (21) is an insulating layer that is completely electrically insulated. , +61t/i The circuit portion 17) below the above-mentioned portion in this semiconductor device indicates a needle which is connected to +11 and extracts an electric signal.
従来の半導体装置では、回路のテストを行う場合、第二
層アルミ配線＋１１に針（７）をあて、電気信号を取り
出していた。In conventional semiconductor devices, when testing a circuit, a needle (7) is applied to the second layer aluminum wiring +11 to extract an electrical signal.
上記のような半導体装置では、第−層アルミ配線のうち
第二層に接続されていない（２１の電気信号を直接取り
出し、テストを行うことができないという問題点があっ
た。In the semiconductor device as described above, there was a problem in that it was not possible to directly take out the electric signal of the first layer aluminum wiring (21) which was not connected to the second layer and perform a test.
この発明は、かかる問題点を解決するためになされたも
ので、第−層アルミ配線（２）に針をあて電気信号を取
り出し、テストが行えるようＶこすること金目的とする
。This invention was made to solve this problem, and its purpose is to apply a needle to the first layer aluminum wiring (2) to extract an electrical signal and rub it with a V so that it can be tested.
〔問題点を解決−１−るためのｆ段〕
この発明に係る半導体装置（・Ｊ：、層間絶縁膜で分離
され／こ二層以」、の配線に、前記層間絶縁膜ｒイ序わ
ガた前記配ぺにスルーホールにより接続し、最上層の前
記配線と同一層か９絶縁されたコーナーを有する形状の
テスト用電極を取り封目たものである。[F-stage for solving the problem-1] In the wiring of the semiconductor device according to the present invention (J: separated by an interlayer insulating film/two or more layers), the interlayer insulating film r is ordered. A test electrode is connected to the above-mentioned arrangement through a through hole, and is sealed with a shape having a corner insulated from the same layer as the above-mentioned wiring on the uppermost layer.
〔作用Ｊ
この発明ＶＣおいては、テスト用市：極を介して層間絶
縁膜で被われた配線の電気信号を取り出す。[Function J] In the VC of this invention, an electric signal from a wiring covered with an interlayer insulating film is extracted through a test pole.
〔実施例−］
第１・２図は、この発明の一実施例？示す、平Ｉ用図お
よび断面図であり、（１）〜（７）は上記従来装置と全
＜ ｕ−、ｉｌ−のものである。（８）は第二層アルミ
配慌１１）と向−物質で同一層につくられ、Ｈｌとは接
続されていないテスト用電極、（９）−第一層アルミ配
線（２）と１８）？結ぶスルーホールを示している。[Example-] Are Figures 1 and 2 an example of this invention? 1 is a flat view and a cross-sectional view shown in FIG. (8) is a test electrode made in the same layer with the second layer aluminum wiring 11) and a compatible material and is not connected to Hl; (9) - the first layer aluminum wiring (2) and 18)? It shows the through hole for connecting.
第１図に示したように、前記市惚（８）にテスト用綴針
（カケあてることによって、前記ｔ４Ｉ署渫（２１の電
気信号を取り出し、テストをイＪうこ占ができる。As shown in FIG. 1, by applying the test needle to the test needle (8), the electric signal of the t4I signal (21) can be extracted and the test can be made.
テスト用電恰１８１ｉＪ：弔１図で電気信号氾１１定用
の針（７）で紳れているコーナーか存在する形状にする
ことによって、針あてを容易にすることかでき、才だ％
ラスト相電極（８）の形状、大きさケ変えることにより
、そのテスト市４極かどの第−層アルミ配線（２）とつ
ながっているかケ明らかにでき、テストを谷：易にする
ことかできる。第５図にテスト用電極の形状の一例ケ挙
げる。回申の丸印はスルーホールを示す。Test electrical design 181iJ: By making the corner or shape where the electrical signal flood 11 standard needle (7) exists in the diagram 1, it is possible to make it easier to apply the needle, which is a great idea.
By changing the shape and size of the last phase electrode (8), it is possible to clarify which of the four test electrodes is connected to which layer aluminum wiring (2), making the test easier. . FIG. 5 shows an example of the shape of the test electrode. Circular circles indicate through holes.
なお、テスト用電極（８）、スルーホール（９）に１そ
れぞれ第二層アルミ配線ＩＩＩ、スルーホール（４）ト
いっしょに作られるため、プロセス手順の増加はない。Note that since the test electrode (8) and the through hole (9) are made together with the second layer aluminum wiring III and the through hole (4), there is no increase in process steps.
ところで上記脳１明では、この発明をに層アルミ配線の
場合について述べたが、三層以上のアルミ配線、寸たは
、その他の導電物質を用いた多層配線に被われた配線の
電気信号を取り出すことにも利用できることはいうまで
もない。By the way, in the above section, this invention was described in the case of two-layer aluminum wiring, but it is also applicable to electrical signals of three or more layers of aluminum wiring, or wiring covered by multilayer wiring using other conductive materials. Needless to say, it can also be used for taking out.
第６図は三層アルミ配線の場合に、第−層アルミ配線か
ら第３層アルミ配線までスルーホールで打ち抜くことか
できないときに中継電極（１０１ｉ用い、この発明全利
用し、第−層アルミ配線の電気信号全敗り出せるように
した半導体装置の断面図である。Figure 6 shows that in the case of three-layer aluminum wiring, when it is not possible to punch out a through hole from the first layer aluminum wiring to the third layer aluminum wiring, a relay electrode (101i) is used, and this invention is fully utilized. FIG. 2 is a cross-sectional view of a semiconductor device that can output all electrical signals.
この発明は以上説明したとおり、層間絶縁膜に被われた
配線の電気信号を、最上層配線と同一層に作られたコー
ナーを有する形状の電極にスルーホールで取り出すこと
によって、開発時のテストを可能ＶＣするという効果が
ある。As explained above, this invention conducts tests during development by extracting electrical signals from wiring covered by an interlayer insulating film through a through hole to an electrode with a corner formed in the same layer as the top layer wiring. This has the effect of making VC possible.
第１・２図は、この発明の一実施例を示すモ（１）１図
および断面図、第３・４図は従来の半導体装置の平面図
および断面図、第５図はこの発明のテスト用電極の形状
の一例全示す平面図、第６図はこの発明の他の実施例金
示す断面図である。
図において、（１）は最」二層配線、（２１け配線、（
５）は層間絶縁膜、（７）はテスト用グ針、（８）はテ
スト用電極、（９）はスルーホールである。
なお、各図中同一符号は同一または相当部分を示す。1 and 2 are a cross-sectional view of a conventional semiconductor device, and FIG. 5 is a test diagram of the present invention. FIG. 6 is a plan view showing an example of the shape of the electrode, and FIG. 6 is a sectional view showing another embodiment of the present invention. In the figure, (1) is the most two-layer wiring, (21-layer wiring,
5) is an interlayer insulating film, (7) is a test needle, (8) is a test electrode, and (9) is a through hole. Note that the same reference numerals in each figure indicate the same or corresponding parts.
Claims (2)
構成する配線と、前記層間絶縁膜に被われた前記配線に
スルーホールにより接続し、最上層の前記配線と同一層
であるテスト用電極とを備えた半導体装置。(1) A test in which the wiring constituting the main circuit in two or more layers separated by an interlayer insulating film is connected to the wiring covered by the interlayer insulating film through a through hole, and the wiring is in the same layer as the uppermost layer. A semiconductor device equipped with an electrode.
たことを特徴とする特許請求の範囲第１項記載の半導体
装置。(2) The semiconductor device according to claim 1, wherein the test electrode is provided with a recess onto which a test probe is applied.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP26623786A JPS63120434A (en) | 1986-11-08 | 1986-11-08 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP26623786A JPS63120434A (en) | 1986-11-08 | 1986-11-08 | Semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS63120434A true JPS63120434A (en) | 1988-05-24 |
Family
ID=17428172
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP26623786A Pending JPS63120434A (en) | 1986-11-08 | 1986-11-08 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS63120434A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5239191A (en) * | 1990-01-19 | 1993-08-24 | Kabushiki Kaisha Toshiba | Semiconductor wafer |
| JPH0737929A (en) * | 1993-07-23 | 1995-02-07 | Nec Corp | Semiconductor integrated circuit device |
| US5757079A (en) * | 1995-12-21 | 1998-05-26 | International Business Machines Corporation | Method for repairing defective electrical connections on multi-layer thin film (MLTF) electronic packages and the resulting MLTF structure |
-
1986
- 1986-11-08 JP JP26623786A patent/JPS63120434A/en active Pending
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5239191A (en) * | 1990-01-19 | 1993-08-24 | Kabushiki Kaisha Toshiba | Semiconductor wafer |
| JPH0737929A (en) * | 1993-07-23 | 1995-02-07 | Nec Corp | Semiconductor integrated circuit device |
| US5757079A (en) * | 1995-12-21 | 1998-05-26 | International Business Machines Corporation | Method for repairing defective electrical connections on multi-layer thin film (MLTF) electronic packages and the resulting MLTF structure |
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