JPS63120374A - Image work station - Google Patents

Abstract

PURPOSE:To store many images in an image memory and to read them out for display at a high speed by securing a large capacity image memory that can read plural picture element data in parallel with each other and reading the image data out of the image memory in parallel to transfer them to an image display memory. CONSTITUTION:Total data on the check image of a patient are sent to a image memory 2 from a magnetic disk 1 via an address processor 9 under the control of a CPU 5. When the data read mode is set, a summary image is produced at a high speed from all image of the patient written in the memory 2. Then the summary image is sent to an image display memory 3a and displayed on a monitor 4a. Then the data on the corresponding original images are read out of the memory 2 in parallel with each other and sent to image display memories 3a-3n at a high speed to be displayed on monitors 4a-4n.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention relates to an image workstation that displays and interprets, for example, medical images using a plurality of monitors, and particularly to an image workstation that displays images on the screens of the monitors at high speed. related to image workstations.

BACKGROUND OF THE INVENTION Conventional image workstations include a magnetic disk that stores a large amount of image data, an image storage memory that stores image data that is transferred from the magnetic disk, and that writes image data that is transferred from the image storage memory. It consisted of a plurality of image display memories and a plurality of monitors that displayed image data read from the respective image display memories as images. Here, the above-mentioned image storage memory is.

It was considered a small capacity read/write memory.

Problems to be Solved by the Invention However, in such conventional image workstations, the image storage memory is a small-capacity read/write memory. The data of the desired image must be sequentially transferred pixel by pixel from the memory to the image display memory and displayed.
It took several seconds to display one screen.

With this, when displaying a large number of images of a certain patient one after another, such as medical images, for interpretation and diagnosis, it takes a lot of time to display the images to be interpreted on the monitor, and the interpretation of the medical images becomes difficult. The overall diagnosis took a long time. Therefore, the efficiency of image diagnosis is reduced.

Therefore, the present invention aims to provide an image workstation capable of solving such problems.Means for solving the problems The means of the present invention for solving the above problems are as follows. A magnetic disk that stores a large amount of image data, an image storage memory that stores image data transferred from the magnetic disk, and a plurality of image display memories that write image data transferred from the image storage memory. In an image workstation having a plurality of monitors that display image data read from each image display memory as an image, the image storage memory has a large capacity and is capable of parallel reading of data of multiple pixels, and This is done by an image workstation equipped with an address processor that performs address calculations for reading image data in parallel from this image storage memory and transferring it to the image display memory.

Embodiments The following five embodiments of the present invention will be described in detail with reference to the accompanying drawings.

FIG. 1 is a block diagram illustrating an embodiment of an image workstation according to the present invention. This image workstation uses a plurality of monitors to display and interpret medical images, for example, and includes a magnetic disk 1, one image storage memory 2, and a plurality of image display memories 3a, 3b, . . . 3n. Multiple monitors 4a.

4b,...4n.

The magnetic disk 1 stores a large amount of image data, for example, data of a plurality of medical images of a plurality of patients. The image storage memory 2 includes the magnetic disk 1
For example, the data of medical images arranged in chronological order of photographic layers of a certain patient is stored. The image display memories 33 to 3n are for writing image data transferred from the image storage memory 2 6.
For example, per pixel]-6 bits of read/write memory, such as dual port RAM, with a capacity of 1 megaword per monitor. The monitors 4a to 4n display image data read from the respective image display memories 38 to 3n as images, and are made of, for example, a CRT. In addition,
In FIG. 1, reference numeral 5 indicates a CPU that controls each component.
(central processing unit) and has built-in main memory.

Further, reference numeral 6 denotes a magnetic disk interface, which connects the CPU 5 and the magnetic disk 1 as an external storage device. Further, reference numeral 7 is a data bus, and reference numeral 8 is a bus connected to the CPU 5.

Here, in the present invention, the image storage memory 2 is a memory having a large capacity and capable of reading out data of a plurality of pixels in parallel, such as a dynamic RAM, as shown in FIG. 2.

For example, its capacity is increased to 32 megawords in total, and four blocks 2a and 2b of 8 megawords each are arranged in parallel.
2c and 2d, and each block has an address designation line 21. a to 21d and data output lines 22a to 22d are provided. and.

By reading and writing each block 2a, 2b, 2e, 2d at 16 bits per pixel.

Parallel reading and writing of 4 pixels and 64 bits is possible in all of the four blocks 28 to 2d. The address specification for this image storage memory 2 is as follows.

The lower 2 bits (2°,
21), it is sufficient to specify the division of each memory block 28 to 2d, and to specify a "row" common to each memory block 2a to 2d using higher-order bits. For example, to specify address 6, specify the second block 2b as the block classification and the second line as the row.6 Also, in the image storage memory 2, as shown in FIG. An address processor 9 is connected. This address processor 9 reads the image data from the image storage memory 2 in parallel and reads the image data from the image display memories 3a to 3n.
As shown in FIG. 3, it consists of a Z address designation circuit 11, an S address designation circuit 11, and a data creation circuit 2. The Z address designation circuit 10 includes a register 13 that stores the initial address set by the CPU 5, and an addition constant, such as It4, for designating the next initial address when reading consecutive addresses.
It consists of an addition constant register 1-4 that stores N, and an adder 15 that adds an addition constant written in J to the address read from the register 13. Note that reference numeral 16 is a Z address bus. Further, the S address designation circuit 11
It has a register 17 that stores the initial address set by U 5 and increments the address by 1 in order to sequentially write data into the image display memories 3a to 3n. Note that reference numeral 18 is an S address bus. Furthermore, the Z data creation circuit 12 connects a bus 8 connected to the CPU 5 and a Z data bus 1.
For example, four output latches 20a, 20b, 2Qc perform conversion and exchange with 9.

20d.Next, the operation of the image workstation of the present invention constructed in this way will be explained. now.

It is assumed that medical image data stored on the magnetic disk 1 is displayed on a plurality of monitors 48 to 4n for interpretation. First, before starting image interpretation, all of the examination images of a certain patient from the magnetic disk shown in FIG. .

Here, from the above magnetic disk], @image storage memory 2
The state in which image data is written to is shown in FIG. 4. That is, the imaging layers of a certain patient are read from the magnetic disk 1 in the order of the oldest and written to the image storage memory 2. For example, if the first tomographic image C1 is a 320x320 X-ray CT image, 102
Write up to address 400. If the second one is the second tomographic *CZ of the X-ray CT image, write from address 102401 to address 204800. Similarly,
When writing up to the 18th tomographic image C1l of the line CT image, the final address becomes address 1843200. Then, if the next one is a 1024×1024 X-ray film image F, then 1
Write from address 843201 to address 2891776, and if there are any further photographed images, they will be written sequentially after that.

In this case, the image storage memory 2 has a large capacity of, for example, 32 megabytes, so it can be used for X-ray CT of 320x320.
Can store 320 images, 1024
32 X-ray film images can be stored, and 1 normal patient's examination images to date can be stored.

Next, when we start interpretation, first, as shown in Figure S,
All images of the patient written in the image storage memory 2 Ct +
Summary image c> for specifying an interpretation image from C2g...C1Il, F,...? e 2 H...cl
lllL... is created at high speed, transferred to the first image display memory 3a, and displayed on the screen of the first monitor 4a. At this time, the above summarized images C1p, C21, etc. are created by C,..., written in the image storage memory 2 shown in FIG.
The data of original images such as C, . Here, regardless of the size of the first tomographic image Cyu or the X-ray film image F as the original Fm image, the summary images cit02t...f,... are 128X128, and the image display is ]-024X1024. Write 64 images to memory 3a and write this to monitor 4.
64 summary images are displayed on one screen of a. if,
If 64 or more test images are stored and the summary image is 64 or more, the images in excess of 64 may be displayed on the second monitor 41). Then, the interpretation doctor looks at the summary image displayed on the screen of the first monitor 4a and learns what kind of image tests the patient has undergone so far, and determines which images are necessary for the two-way interpretation. Determine and specify.

Next, when the image necessary for image interpretation is specified in this way, the data of the corresponding original image is read out in parallel from the image storage memory 2 by specifying the address by the address calculation of the address processor 9 shown in FIG. 6th
As shown in the figure, the data is transferred to the image display memories 3a, 3b, . . . at high speed.

Here, the state in which the address processor 9 specifies an address in the image storage memory 2 and reads out image data will be described with reference to FIG. first.

As mentioned above, the image storage memory 2 is divided into, for example, four blocks 2a, 2b, 2e, and 2d in parallel.
Each block has address designation lines 21a, 2, respectively.
l b , 2 ], c , 21 d and data output lines 22a, 22b, 22c, 22a are provided. Therefore, the address processor 9 determines that address 1 is the first line of the first block 2a, address 2 is the first line of the second block 2b, address 3 is the first line of the third block 2c, and address 4 is the first line of the fourth block 2d. If you specify as in the first line of
Image data stored up to an address can be read out at once. Similarly, number 5 is the second row of the first block 2a,
Address 6 is specified as the second line of the second block 2b, address 8 is specified as the second line of the fourth block 2d, etc., and the image data stored from addresses 5 to 8 is stored once. Read out. As a result, the readout speed per pixel is four times faster in the example of FIG. 2 than in the conventional series-configured image storage memory. And finally, the first block 2
Specify address 9 in the third row of a and read it. In this way, for example, the first stroke data stored at addresses 1 to 9 are read out in parallel and transferred to the first image display memory 3a.

Next, assuming that the second image data is stored at addresses 10 to 18, the address processor 9
Since the first block 2a is read up to address 9 on the third line as the first image data, specify address 13 on the fourth line for this first block 2a,
For the second block 2b, specify address 10 on the third line, for the third block 2c, specify address 11 on the third line, and for the fourth block 2d, specify address 12 on the third line. Specify and read the image data at once.

However, the addresses of this read image data are 13.10, 11.12 from the left, and the order is wrong, so the multiplexer 23 transfers the addresses to 1.0, 1.0, 11.12 from the left, etc.
The images are rearranged to the correct addresses in the order of 11, 12, and 13, and transferred to the second image display memory 3b via the data bus 7. Similarly, in the fifth read, address 17 on the fifth row is specified for the first block 2a, and the second block 2b
For , specify address 14 on the 4th line, and move to the third block 2.
For c, address 15 on the fourth line is specified, and for fourth block 2d, address 16 on the fourth line is specified, and the image data thereof are read out at once. In this case as well, the address order of the read image data is 17. Since they have been inserted incorrectly like J4.15.16, the multiplexer 23 rearranges them in the correct address order and transfers them to the second image display memory 3b. Finally, address 18 on the fifth row is specified for the second block 2b and read out. In this way, the second image data stored at addresses 10 to 18 are read out in parallel and are all transferred to the second image display memory 3b.

As a result, the image data necessary for image interpretation is stored in the image storage memory 2.
are read out at high speed from the image display memory 3a, 3b, .
..., etc., and those images are displayed on each monitor 4a, 4b.
, etc. are displayed. For example, 1024x1024
Even images can be transferred and displayed at 50rnsee, so
Doctors who read images almost never experience any waiting time. In addition,
When changing the monitors 4a, 4b, . . . for displaying an image, the data of the image to be displayed is transferred again from the image storage memory 2 to the corresponding image display memory 3a, 3b, .
You can forward it to etc.

FIG. 7 is an explanatory diagram showing a modification of the configuration of the image storage memory 2 and the reading of image data by the address processor. In this modification, an odd number of blocks, for example five blocks 2a+ 2b+, are arranged in parallel in the image storage memory 2.
2c, 2d, and 2e, and address designation lines 21a to 21e and data output lines 22a to 22e for each block.
It has been established. Here, as shown in FIG.
2゜...Summary image cxtaz*...Q, 9rf*... for specifying an interpretation image from C engineering, 2F,...
For example, when creating a 128x128 summary image from both 512x512 original images, it is necessary to reduce the size to 1/4 in both the vertical and horizontal directions, so from the image storage memory 2, every 4 addresses are No. 1,
That is, it is necessary to read out the image data at addresses 1°5, 9, 13, etc. by thinning out the space by three addresses. At this time, if the image storage memory 2 is divided into four blocks 2a to 2d as shown in FIG.゜No. 13... are all in the first block 2a
It's within.

Therefore, when creating such a summary image, even if the image storage memory 2 is divided into a plurality of blocks, the data will not be read out in parallel, but the transfer speed of summary image data to the single image display memory 3a will be increased. It is not possible.

Therefore, as shown in FIG. 7, if the image storage memory 2 is divided into, for example, five blocks 2a to 2e in parallel, the
1.28 x 12 from 12 x 512 original image
Addresses 1, 5, 9, 13, 17, etc., which are the readout addresses of the image data when creating a summary image of 8, are the 1st line of the first block 2a and 1 of the 5th block 2e, respectively.
The data are distributed to each block in the following manner: the second row of the fourth block 2d, the third row of the third block 2c, the fourth row of the second block 2b, and so on. In this case, image data is read out in a first-order manner. First, the address processor 9 specifies address 1 on the first line for the first block 2a, address 7 on the fourth line for the second block 2b, and specifies address 7 on the fourth line for the second block 2b. For the fourth block 2d, specify address 133 on the third line.
Specify the 9th address of the row, and 1 for the fifth block 2e.
Specify address 5 of the row and read the image data at once. However, since the addresses of the read image data are 1, 17, 13, 9, and 5 from the left, and the order is wrong, the multiplexer 23 reads them from the left to 1.
The data are rearranged to the correct addresses in the order of 5, 9, 13, and 17, and transferred to the image display memory 3a via the data bus 7. In this way, a summary image is created from the data of all images of the patient written in the image storage memory 2, and is transferred at high speed to the image display memory 3a, and the summarized image is displayed on the monitor 4a.

Therefore, according to the modification shown in FIG.
By dividing the image data into odd-numbered blocks, the image data can be transferred and displayed at high speed even when creating and displaying a summary image obtained by appropriately reducing the original image. Although the image storage memory 2 is shown divided into five blocks in parallel in FIG. 7, the present invention is not limited to this, and may be divided into three blocks or multiple blocks, for example.

Effects of the Invention Since the present invention is configured as described above, a large amount of image data, for example, a large number of medical images of a certain patient, can be stored in the image storage memory 2, and this image data can be transferred from the image storage memory 2 to an image. Data of a plurality of pixels can be read out in rows and transferred to the display memories 3a to 3n at high speed. Therefore, the desired image can be displayed on the monitor 48.
4n can be displayed at a higher speed than before. From this, 1. For example, when a large number of images of a certain patient, such as medical images, are displayed one after another for interpretation and diagnosis, it is possible to display the images to be interpreted on the monitors 4a to 4n in a short time with almost no waiting time. This reduces the overall time required for medical image interpretation and diagnosis. Therefore, it is possible to improve the efficiency of image diagnosis by the image interpreting doctor.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an embodiment of the image workstation according to the present invention, FIG. 2 is an explanatory diagram showing the configuration of the image storage memory and the state of reading image data by the address processor, and FIG. 3 is the configuration of the address processor. FIG. 4 is an explanatory diagram showing the state of writing image data to the image storage memory, FIG. 5 is an explanatory diagram showing the state of creating and displaying a summary image, and FIG. 6 is an explanatory diagram showing the state of creating and displaying a summary image. FIG. 7 is an explanatory diagram showing a state in which data is transferred to a memory and displayed on a monitor. FIG. 7 is an explanatory diagram showing a modification of the configuration of an image storage memory and the reading of image data by an address processor. 1... Magnetic disk, 2... Image storage memory,
2a to 2e...blocks of image storage memory, 3a
~3n...Image display memory, 4a~4n...Monitor, 5...CPU, 7...Data bus, 8
...CPU bus, 9...Address processor,
21a-21e... address designation line, 22a-22e
...Data output line.

Claims (1)

[Claims] A magnetic disk that stores a large amount of image data, an image storage memory that stores image data transferred from this magnetic disk, a plurality of image display memories that write image data transferred from this image storage memory, and each image. In an image workstation having a plurality of monitors that display image data read from a display memory as an image, the image storage memory has a large capacity and can read data of multiple pixels in parallel; An image workstation comprising an address processor that performs address calculations for reading image data from a memory in parallel and transferring it to the image display memory.