JPS63118580U

JPS63118580U -

Info

Publication number: JPS63118580U
Application number: JP846187U
Authority: JP
Priority date: 1987-01-23
Filing date: 1987-01-23
Publication date: 1988-08-01

Description

[Brief explanation of the drawing]

第１図はこの考案の一実施例を示した図、第２
図は従来のＩ，Ｑ位相検波回路のブロツク構成図
である。図において、１は電力分配器、２は第１の周波
数混合器、３は第２の周波数混合器、４は９０°
電力分配器、５は電力合成器、６は電力分配器、
７は第１の位相調整用の可変抵抗器、８は第２の
位相調整用の可変抵抗器、９は加算器、１０は振
幅調整用の増幅器である。なお、各図中同一符号
は同一または相当部分を示す。 Figure 1 shows an embodiment of this invention, Figure 2
The figure is a block diagram of a conventional I,Q phase detection circuit. In the figure, 1 is a power divider, 2 is a first frequency mixer, 3 is a second frequency mixer, and 4 is a 90°
a power divider, 5 a power combiner, 6 a power divider,
7 is a variable resistor for first phase adjustment, 8 is a variable resistor for second phase adjustment, 9 is an adder, and 10 is an amplifier for amplitude adjustment. Note that the same reference numerals in each figure indicate the same or corresponding parts.

Claims

[Scope of utility model registration request]

a first power divider that divides an intermediate frequency signal into two in-phase signals within the receiver; two frequency mixers that respectively detect the intermediate frequency signals that are the two outputs of the first power divider; a 90° power divider that divides and outputs the local oscillator signal used for detection in the two frequency mixers into two with a relative phase of 90°;
a second power divider that divides the output of one of the two frequency mixers into three; one phase correction variable resistor, the output of the other frequency mixer and the two above.
An adder that adds the three outputs of the two phase correction variable resistors, an amplifier that amplifies the adjusted signal output from the adder, and a phase of the output of the amplifier and the three outputs of the second power divider. A phase detection circuit comprising a power combiner that combines one output without a correction variable resistor.