WO2018109871A1 - Phase and amplitude detection circuit, transmission module and array antenna - Google Patents

Phase and amplitude detection circuit, transmission module and array antenna Download PDF

Info

Publication number
WO2018109871A1
WO2018109871A1 PCT/JP2016/087240 JP2016087240W WO2018109871A1 WO 2018109871 A1 WO2018109871 A1 WO 2018109871A1 JP 2016087240 W JP2016087240 W JP 2016087240W WO 2018109871 A1 WO2018109871 A1 WO 2018109871A1
Authority
WO
WIPO (PCT)
Prior art keywords
signal
phase
amplitude
reference signal
output
Prior art date
Application number
PCT/JP2016/087240
Other languages
French (fr)
Japanese (ja)
Inventor
浩之 水谷
一二三 能登
英之 中溝
田島 賢一
Original Assignee
三菱電機株式会社
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 三菱電機株式会社 filed Critical 三菱電機株式会社
Priority to PCT/JP2016/087240 priority Critical patent/WO2018109871A1/en
Priority to JP2018541229A priority patent/JP6452915B2/en
Publication of WO2018109871A1 publication Critical patent/WO2018109871A1/en

Links

Images

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01QANTENNAS, i.e. RADIO AERIALS
    • H01Q21/00Antenna arrays or systems
    • H01Q21/06Arrays of individually energised antenna units similarly polarised and spaced apart
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01QANTENNAS, i.e. RADIO AERIALS
    • H01Q23/00Antennas with active circuits or circuit elements integrated within them or attached to them
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01QANTENNAS, i.e. RADIO AERIALS
    • H01Q3/00Arrangements for changing or varying the orientation or the shape of the directional pattern of the waves radiated from an antenna or antenna system
    • H01Q3/26Arrangements for changing or varying the orientation or the shape of the directional pattern of the waves radiated from an antenna or antenna system varying the relative phase or relative amplitude of energisation between two or more active radiating elements; varying the distribution of energy across a radiating aperture
    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03DDEMODULATION OR TRANSFERENCE OF MODULATION FROM ONE CARRIER TO ANOTHER
    • H03D5/00Circuits for demodulating amplitude-modulated or angle-modulated oscillations at will

Definitions

  • the present invention relates to a phase / amplitude detection circuit, and more particularly to a phase / amplitude detection circuit for detecting the phase and amplitude of a transmission signal, and a transmission module and an array antenna using the same.
  • An antenna that can have directivity in the direction of radiating radio waves by arranging a plurality of element antennas and controlling the amplitude and phase of a signal that excites each element antenna is called an array antenna.
  • FIG. 8 shows an example of a conventional transmitting array antenna.
  • the conventional transmission array antenna includes a reference signal generation source 101, an in-phase distributor 102, a plurality of transmission modules 103, and a plurality of element antennas 104.
  • a transmission module 103a and a transmission module 103b are shown as the plurality of transmission modules 103.
  • the transmission module 103a and the transmission module 103b have the same configuration.
  • Each transmission module 103 includes a phase shifter 105, a variable attenuator 106, and an amplifier 107.
  • an element antenna 104a and an element antenna 104b are shown as the plurality of element antennas 104.
  • the element antenna 104a is connected to the transmission module 103a
  • the element antenna 104b is connected to the transmission module 103b.
  • the element antenna 104a and the element antenna 104b have the same configuration.
  • the alphabets “a” and “b” are attached to the end of the reference numerals so as to distinguish between the plurality of components provided.
  • the transmission module 103a and the transmission module 103b have the same configuration, and the element antenna 104a and the element antenna 104b have the same configuration, in the following description, the transmission module 103a and the transmission module 103b are The element antenna 104a and the element antenna 104b are simply referred to as the “element antenna 104” without being distinguished from each other.
  • the reference signal generation source 101 outputs a reference signal.
  • the reference signal is input to the in-phase distributor 102.
  • the in-phase distributor 102 distributes the reference signal to each transmission module 103 in the same phase.
  • the signal input from the in-phase distributor 102 is input to the phase shifter 105.
  • a phase control signal is input to the phase shifter 105 from the outside.
  • the phase shifter 105 changes the phase of the signal by the amount of phase shift corresponding to the phase control signal input from the outside.
  • a signal output from the phase shifter 105 is input to the variable attenuator 106.
  • An amplitude control signal is input to the variable attenuator 106 from the outside.
  • the variable attenuator 106 changes the amplitude of the signal output from the phase shifter 105 by the amount of attenuation corresponding to the amplitude control signal input from the outside.
  • the signal output from the variable attenuator 106 is input to the amplifier 107.
  • the amplifier 107 amplifies the amplitude of the signal output from the variable attenuator 106.
  • the signal output from the amplifier 107 is input to the element antenna 104.
  • the element antenna 104 radiates the signal as a radio wave.
  • the amplifier 107 has a large variation in characteristics among individuals, and the characteristics vary greatly with temperature. Therefore, due to the unstable characteristics of the amplifier 107, the amplitude and phase of the signal supplied to each element antenna 104 are transferred to the phase shifter 105 and the variable attenuator 106 based on the phase control signal and the amplitude control signal. There is a possibility that the desired directivity may not be obtained in each element antenna 104 because the value fluctuates from the set value. Therefore, it is necessary to detect and calibrate the amplitude and phase of the signal supplied to each element antenna 104.
  • Patent Document 1 there is a method described in Patent Document 1 as a conventional calibration method.
  • Patent Document 1 the output terminals of adjacent transmission modules are connected with a cable, and the amplitude difference and phase difference of the transmission signals of those transmission modules are detected. Then, the amplitude and phase of the transmission signal of one transmission module are calibrated so that the detected amplitude difference and phase difference are eliminated.
  • this configuration requires that the output terminals of the two transmission modules be connected by a cable, there is a problem in that the degree of freedom of arrangement of these transmission modules is reduced.
  • the arrangement of the element antennas 104 is determined according to a function to be realized as an array antenna.
  • the installation location of the transmission module 103 depends not only on the arrangement of the element antennas 104 but also on the size and weight of the transmission module 103 itself and the size and weight of other components not shown in FIG. Also depends. For this reason, it is desirable that the transmission module 103 has a degree of freedom as much as possible.
  • phase of the transmission signal can be detected for each transmission module without connecting a plurality of transmission modules with cables.
  • a reference signal is distributed to each transmission module 103 using an in-phase distributor 102.
  • the reference signal distributed to each transmission module 103 is in phase. Therefore, in each transmission module 103, if the phase difference between the transmission signal transmitted by the transmission module and the reference signal is detected, the phase of the transmission signal supplied to each element antenna 104 can be calibrated.
  • Patent Document 2 discloses a phase detection circuit using this fact.
  • the phase of the transmission signal is detected by detecting the phase difference between the transmission signal and the reference signal.
  • the phase detection circuit described in Patent Document 2 has phase shift means for changing the phase of the reference signal by 0 ° or 90 °, and the reference signal and the transmission signal shifted by 0 ° or 90 ° are combined into a single mixer. Mix with.
  • the voltage (Q component) is acquired in time division. Then, the phase difference between the reference signal and the transmission signal is detected based on these two voltages. Further, the phase of the transmission signal is detected for each transmission module based on the detected phase difference. Then, the phase of the transmission signal of each transmission module is calibrated by calculating the difference between the detected phase and the desired phase.
  • Patent Document 1 As described above, in Patent Document 1, two transmission modules are required for detection of the phase and amplitude of a transmission signal, and the phase and amplitude of the transmission signal cannot be detected with only a single transmission module. There was a problem.
  • the phase detection circuit disclosed in Patent Document 2 has a problem that it can detect the phase of the transmission signal but cannot detect the amplitude of the transmission signal.
  • Patent Document 2 when it is attempted to detect the amplitude of the transmission signal, it is necessary to add another circuit for detecting the amplitude. Therefore, there is a problem that the circuit scale increases.
  • the present invention has been made to solve such a problem, and a phase / amplitude detection circuit capable of detecting the phase and amplitude of a transmission signal with a single circuit, and transmission using the same.
  • An object is to provide a module and an array antenna.
  • the present invention provides a first state in which a reference signal and a signal under measurement are input, the phase of the reference signal and the signal under measurement is changed by 0 °, and the reference signal and the signal under measurement are output, the reference signal or A second state in which only one phase of the signal under measurement is changed by 90 ° to output the reference signal and the signal under measurement, and only the signal under measurement is blocked by passing the reference signal
  • a signal switching unit that operates by sequentially switching the three states of the third state to be output, and the signal switching unit connected to the signal switching unit, and the state of the signal switching unit is the first state or the second state
  • a low-pass filter that extracts a DC component
  • an A / D converter that converts a voltage of the DC component output from the low-pass filter into a digital signal
  • the signal switching unit includes the first state and
  • the signal switching unit sequentially switches the first state, the second state, and the third state, and the digital signal in the three states is sent from the A / D converter.
  • the signal processing circuit calculates the phase and amplitude of the signal under measurement based on the digital signal, the phase and amplitude of the signal under measurement can be detected by a single circuit. The effect is obtained.
  • FIG. 1 is a configuration diagram showing the configuration of a phase amplitude detection circuit according to Embodiment 1 of the present invention.
  • the phase amplitude detection circuit is a circuit for receiving a reference signal and a signal under measurement and detecting a phase difference between the reference signal and the signal under measurement and an amplitude of the signal under measurement.
  • the phase / amplitude detection circuit includes a switch 1, a transmission line 2, a transmission line 3, a terminator 4, a switch 5, a terminator 6, a mixer 7, an LPF (Low Pass Filter) 8, and an A / D conversion.
  • a signal processing circuit 10 10.
  • reference numerals 11 to 21 are assigned to the terminals as shown in FIG. That is, the reference signal input terminal 11, the signal under test input terminal 12, the signal processing circuit 10 output terminal 13, the switch 1 input terminal 14, and the switch 1 three output terminals 15, 16, respectively. 17, the three input terminals of the switch 5 are 18, 19, 20 and the output terminal of the switch 5 is 21, respectively.
  • the reference signal is input to the input terminal 11 of the phase amplitude detection circuit.
  • a reference signal generation source is connected to the input terminal 11.
  • a CW (Continuous Wave) signal is used as the reference signal.
  • the signal under measurement to be measured is input to the input terminal 12 of the phase amplitude detection circuit.
  • a transmission signal transmitted from the transmission module can be cited.
  • the switch 1 has one input terminal 14 and three output terminals 15, 16, and 17.
  • the input terminal 14 of the switch 1 is connected to the input terminal 11 of the phase amplitude detection circuit, and a reference signal is input from the input terminal 11.
  • a reference signal is input from the input terminal 11.
  • the switch 1 outputs a reference signal input to the input terminal 14 from any one of the output terminals 15, 16, and 17 according to the state of the connection destination. Note that switching of the connection destination of the switch 1 is sequentially performed in a preset cycle, for example, in the order of the output terminals 15, 16, and 17. Alternatively, the connection destination of the switch 1 may be switched based on an external control signal.
  • the transmission line 2 is connected between the output terminal 15 of the switch 1 and the input terminal 18 of the switch 5.
  • the transmission line 2 receives a reference signal from the output terminal 15 of the switch 1 and outputs the reference signal to the input terminal 18 of the switch 5.
  • the transmission line 3 is connected between the output terminal 16 of the switch 1 and the input terminal 19 of the switch 5.
  • the transmission line 3 receives a reference signal from the output terminal 16 of the switch 1 and outputs the reference signal to the input terminal 19 of the switch 5.
  • the transmission line 2 and the transmission line 3 are configured such that their electrical lengths are 90 ° different from each other.
  • the transmission line 2 changes the phase of the reference signal by 0 ° and outputs it, that is, the transmission line 2 outputs the reference signal as it is, and the transmission line 3 changes the phase of the reference signal by 90 °. Output.
  • the terminator 4 is connected to the output terminal 17 of the switch 1.
  • the terminator 4 terminates the reference signal input to the output terminal 17 of the switch 1 and blocks the output of the reference signal to the switch 5.
  • the switch 5 has three input terminals 18, 19, 20 and one output terminal 21. An output terminal 21 of the switch 5 is connected to the mixer 7. As the connection destination of the switch 5, one of the three input terminals 18, 19, and 20 is selected. The switch 5 outputs the reference signal input to any one of the input terminals 18 and 19 from the output terminal 21 to the mixer 7 according to the state of the connection destination. Note that switching of the connection destination of the switch 5 is performed in synchronization with switching of the connection destination of the switch 1.
  • the terminator 6 is connected to the input terminal 20 of the switch 5. When the connection destination of the switch 5 is the input terminal 20, the terminator 6 terminates the signal input to the input terminal 20 and blocks the output of the signal to the mixer 7.
  • the mixer 7 is connected to the input terminal 12 of the phase amplitude detection circuit, and the signal under measurement is input from the input terminal 12.
  • the mixer 7 is connected to the output terminal 21 of the switch 5.
  • the mixer 7 mixes the reference signal input from the output terminal 21 of the switch 5 and the signal under measurement input from the input terminal 12, and the sum frequency component, the difference frequency component of the reference signal and the signal under measurement, and
  • the mixed wave including the three components of the higher-order mixed wave component is output to the LPF 8.
  • the difference frequency component between the two signals is a DC component, that is, a constant value.
  • the DC component has a voltage value corresponding to the phase difference between the reference signal and the signal under measurement.
  • the mixer 7 detects the signal under measurement and outputs a mixed wave including a DC component corresponding to the amplitude of the signal under measurement to the LPF 8.
  • the DC component has a voltage value corresponding to the amplitude of the signal under measurement.
  • the LPF 8 extracts only the DC component from the plurality of components included in the mixed wave output from the mixer 7 and outputs it to the A / D converter 9.
  • the LPF 8 blocks other components included in the mixed wave and does not output them.
  • the A / D converter 9 quantizes the DC component voltage value output from the LPF 8 and converts it into a digital signal.
  • the digital signal includes voltage value information corresponding to the phase difference between the reference signal and the signal under measurement and voltage value information corresponding to the amplitude of the signal under measurement.
  • the digital signal is input to the signal processing circuit 10.
  • the signal processing circuit 10 calculates the relative phase of the signal under measurement with respect to the reference signal and the amplitude of the signal under measurement based on the digital signal output from the A / D converter 9.
  • the output terminal 13 of the phase / amplitude detection circuit outputs the relative phase and amplitude calculated by the signal processing circuit 10 to the outside.
  • the switch 1, the transmission line 2, the transmission line 3, the terminator 4, and the switch 5 constitute a “signal switching unit” that switches the output of the reference signal and the signal under measurement.
  • the signal switching unit has the following three states (1) to (3), and operates by selecting one of these states.
  • the three states of the signal switching unit are switched by switching the connection destination of the switch 1 and the switch 5.
  • the signal processing circuit 10 uses the two digital signals output from the A / D converter 9 when the signal switching unit is in the first state and the second state, The phase difference of the signal under measurement is calculated, and the amplitude of the signal under measurement is calculated using one digital signal output from the A / D converter 9 when the signal switching unit is in the third state. The operation of the signal processing circuit 10 will be described later.
  • the input units are the input terminals 11 and 12, and the output unit is the output terminal 13.
  • the switches 1 and 5 are composed of switching elements such as FETs or PIN diodes.
  • the transmission lines 2 and 3 are composed of, for example, a coaxial line, a strip line, a microstrip line, a coplanar line, and the like.
  • the mixer 7 is composed of a non-linear element such as an FET or a Schottky diode.
  • the LPF 8 is configured by combining a resistor, a capacitor, an inductor, and the like.
  • phase amplitude detection circuit includes a processing circuit for performing A / D conversion of signals and performing various calculations. Even if the processing circuit is dedicated hardware, a CPU that executes a program stored in a memory (Central Processing Unit, central processing unit, processing unit, arithmetic unit, microprocessor, microcomputer, processor, DSP) It may be.
  • a memory Central Processing Unit, central processing unit, processing unit, arithmetic unit, microprocessor, microcomputer, processor, DSP
  • the processing circuit is dedicated hardware, the processing circuit is, for example, a single circuit, a composite circuit, a programmed processor, a parallel programmed processor, an ASIC, an FPGA, or a combination thereof.
  • the functions of each part of the A / D converter 9 and the signal processing circuit 10 may be realized by a processing circuit, or the functions of each part may be collectively realized by a processing circuit.
  • each function of the A / D converter 9 and the signal processing circuit 10 is realized by software, firmware, or a combination of software and firmware.
  • Software and firmware are described as programs and stored in a memory.
  • the processing circuit reads out and executes the program stored in the memory, thereby realizing the function of each unit. That is, a step for performing A / D conversion of a signal and a step for performing various signal processing include a memory for storing a program to be executed as a result. These programs can also be said to cause a computer to execute the procedures and methods of the A / D converter 9 and the signal processing circuit 10.
  • the memory corresponds to, for example, a nonvolatile or volatile semiconductor memory such as RAM, ROM, flash memory, EPROM, or EEPROM, a magnetic disk, a flexible disk, an optical disk, a compact disk, a mini disk, a DVD, or the like. To do.
  • a nonvolatile or volatile semiconductor memory such as RAM, ROM, flash memory, EPROM, or EEPROM, a magnetic disk, a flexible disk, an optical disk, a compact disk, a mini disk, a DVD, or the like.
  • a / D converter 9 and the signal processing circuit 10 may be realized by dedicated hardware, and a part may be realized by software or firmware.
  • the function of the A / D converter 9 is realized by a processing circuit as dedicated hardware, and the processing circuit of the signal processing circuit 10 is read by the processing circuit stored in the memory and executed. You may make it implement
  • the processing circuit can realize the above functions by hardware, software, firmware, or a combination thereof.
  • the relative phase ⁇ of the signal under measurement with respect to the reference signal that is, the phase difference between the reference signal and the signal under measurement is calculated as the phase of the signal under measurement.
  • a reference signal input from the outside to the input terminal 11 is input to the input terminal 14 of the switch 1 and is output from any one of the output terminals 15, 16, and 17 according to the state of the connection destination of the switch 1. .
  • connection destination of the switch 1 When the connection destination of the switch 1 is selected as the output terminal 15, the connection destination of the switch 5 is switched to the input terminal 18. This state is the first state described above. At this time, the reference signal input to the input terminal 14 of the switch 1 is output from the output terminal 15 of the switch 1 and input to the input terminal 18 of the switch 5 through the transmission line 2. The reference signal input to the input terminal 18 of the switch 5 is output from the output terminal 21 of the switch 5 and input to the mixer 7.
  • the signal under measurement input to the input terminal 12 is input to the mixer 7.
  • the mixer 7 mixes the reference signal input from the output terminal 21 and the signal under measurement input from the input terminal 12.
  • the mixer 7 generates a mixed wave including a sum frequency component, a difference frequency component, and a higher-order mixed wave component of the signal under measurement and the reference signal, and the mixed wave is input to the LPF 8.
  • the LPF 8 outputs only the DC component that is the difference frequency component among the plurality of components of these mixed waves, and blocks the passage of other components.
  • the voltage value of the DC component includes information on the phase difference between the signal under measurement and the reference signal.
  • the DC component output from the LPF 8 is input to the A / D converter 9.
  • the A / D converter 9 quantizes the DC component voltage value and converts it into a digital signal.
  • the digital signal output from the A / D converter 9 is input to the signal processing circuit 10.
  • the signal processing circuit 10 stores the digital signal in a memory (not shown).
  • connection destination of the switch 1 is selected as the output terminal 16
  • connection destination of the switch 5 is switched to the input terminal 19.
  • This state is the second state described above.
  • the reference signal input to the input terminal 14 of the switch 1 is output from the output terminal 16 of the switch 1 and input to the input terminal 19 of the switch 5 via the transmission line 3.
  • the phase of the reference signal is shifted by 90 ° by the transmission line 3.
  • the reference signal input to the input terminal 19 is output from the output terminal 21 of the switch 5 and input to the mixer 7.
  • the subsequent operation is the same as when the connection destination of the switch 1 is selected as the output terminal 15. That is, of the mixed wave generated by mixing the reference signal and the signal under measurement by the mixer 7, the DC component voltage value is quantized by the A / D converter 9 and input to the signal processing circuit 10. Is remembered.
  • the voltage value of the DC component obtained here includes information on the phase difference between the reference signal and the signal under measurement.
  • the digital signal stored in the memory when the connection destination of the switch 1 is selected as the output terminal 15 is defined as an I component.
  • the digital signal stored in the memory when the connection destination of the switch 1 is selected as the output terminal 16 is defined as the Q component.
  • the signal processing circuit 10 calculates the relative phase of the signal under measurement with respect to the reference signal based on the I component and the Q component stored in the memory. The calculation method will be described below. When the voltage of the I component is VI, the voltage of the Q component is VQ, and the relative phase of the signal under measurement with respect to the reference signal is ⁇ , ⁇ can be obtained by the following equation (1). Therefore, the signal processing circuit 10 calculates the relative phase ⁇ of the signal under measurement with respect to the reference signal using the following equation (1).
  • the signal processing circuit 10 stores the relative phase ⁇ thus obtained in the memory as phase data of the signal under measurement.
  • connection destination of the switch 1 is selected as the output terminal 17.
  • connection destination of the switch 5 is switched to the input terminal 20. This state is the third state described above.
  • the reference signal input to the input terminal 11 is output from the output terminal 17 of the switch 1 and input to the terminator 4.
  • the terminator 4 terminates the reference signal. For this reason, the reference signal is not input to the mixer 7.
  • the mixer 7 Only the signal under measurement is input to the mixer 7.
  • the signal under measurement input from the input terminal 12 to the mixer 7 is detected by the mixer 7 and a DC component corresponding to the amplitude of the signal under measurement is output. That is, at this time, the mixer 7 functions as a detector.
  • the mixer 7 outputs a leakage component of the signal under measurement and a harmonic component of the signal under measurement in addition to the DC component.
  • the LPF 8 passes only the DC component among the plurality of components output from the mixer 7 and blocks the passage of other components.
  • the DC component voltage includes information on the amplitude of the signal under measurement.
  • the voltage of the DC component output from the LPF 8 is quantized by the A / D converter 9 and converted into a digital signal.
  • the digital signal is input to the signal processing circuit 10.
  • the signal processing circuit 10 stores the digital signal in the memory as amplitude data of the signal under measurement.
  • the connection destination of the switch 1 and the connection destination of the switch 5 are sequentially switched, and the three data of the I component, the Q component, and the amplitude are sequentially acquired.
  • the phase difference between the reference signal and the signal under measurement and the amplitude of the signal under measurement can be detected.
  • the phase difference between the reference signal and the signal under measurement and the amplitude of the signal under measurement are detected by the same circuit simply by switching the connection destination of the switches 1 and 5. be able to.
  • FIG. 1 although it showed about comprising the circuit which has a phase difference of 90 degrees using the transmission line 2 and the transmission line 3, as shown in FIG. 2, instead of the transmission line 2 and the transmission line 3, Even if the 90 °, 3 dB coupler 22 is used, the same effect can be obtained. 2, the same components as those in FIG. 1 are denoted by the same reference numerals as those in FIG. 1, and description thereof is omitted here.
  • the 90 °, 3 dB coupler 22 shifts the phase of the reference signal input from the output terminal 15 by 0 °, and outputs it from the terminal written “0 °”. In addition, the 90 °, 3 dB coupler 22 shifts the phase of the reference signal input from the output terminal 16 by 90 °, and outputs it from the terminal written “0 °”. In either case, the signal is output from the terminal where “0 °” is written.
  • a switch 23 is provided instead of the switch 5 of FIG.
  • the switch 23 has two input terminals 25 and 26 and one output terminal 27.
  • the output terminal 27 is connected to the mixer 7.
  • the switch 23 outputs a reference signal input to the input terminal 25 to the output terminal 27.
  • the terminator 6 terminates the signal input to the input terminal 26 and cuts off the output to the output terminal 27 of the switch 23. Further, the terminal written as “90 °” of the 90 °, 3 dB coupler 22 is terminated by the terminator 24.
  • connection destination of the switch 1 When the connection destination of the switch 1 is selected as the output terminal 15 or the output terminal 16, the connection destination of the switch 23 is switched to the input terminal 25.
  • the reference signal is output from the output terminal 15 and input to the 90 °, 3 dB coupler 22.
  • the 90 °, 3 dB coupler 22 shifts the phase of the reference signal by 0 ° and inputs it to the input terminal 25 of the switch 23. This state is the first state described above.
  • the reference signal is output from the output terminal 16 and input to the 90 °, 3 dB coupler 22.
  • the 90 °, 3 dB coupler 22 shifts the phase of the reference signal by 90 ° and inputs it to the input terminal 25 of the switch 23. This state is the second state described above.
  • the 90 °, 3 dB coupler 22 operates as described above according to the state of the connection destination of the switch 1, and therefore performs the same operation as the combination of the transmission line 2 and the transmission line 3 shown in FIG. As a result, the phase amplitude detection circuit in FIG. 2 performs the same operation as the phase amplitude detection circuit in FIG.
  • phase shifter 57 may be used instead of the transmission lines 2 and 3 of FIG.
  • the same components as those in FIG. 1 are denoted by the same reference numerals as those in FIG. 1, and description thereof is omitted here.
  • the phase shifter 57 is connected between the output terminal 15 of the switch 1 and the input terminal 18 of the switch 5.
  • the phase shifter 57 shifts the phase of the reference signal input from the output terminal 15 by 0 ° according to the control signal input from the outside. Or the phase of the reference signal is shifted by 90 ° and output.
  • phase shifter 57 Since the phase shifter 57 operates as described above in accordance with the state of the connection destination of the switch 1 and the control signal from the outside, the operation equivalent to the combination of the transmission line 2 and the transmission line 3 shown in FIG. Do. As a result, the phase amplitude detection circuit of FIG. 3 performs the same operation as the phase amplitude detection circuit of FIG.
  • FIG. 2 and FIG. 3 are the same as those in FIG. 1, and thus the description thereof is omitted here.
  • the phase of the reference signal is output by shifting the phase by 0 °
  • the phase of the reference signal is output by shifting the phase by 90 °
  • the reference signal is terminated.
  • three data of the I component, the Q component, and the amplitude are acquired.
  • the relative phase ⁇ of the signal under measurement with respect to the reference signal and the amplitude of the signal under measurement can be detected.
  • the relative phase ⁇ of the signal under measurement with respect to the reference signal and the amplitude of the signal under measurement are detected by the same circuit by simply switching the connection destination of the switches 1 and 5.
  • the circuit scale of the phase amplitude detection circuit can be reduced. Therefore, when the phase / amplitude detection circuit according to the first embodiment is mounted on the transmission module and the array antenna, the relative phase and amplitude of the transmission signal, which is the signal under measurement, are detected for each transmission module and transmitted with a simple configuration. It becomes possible to calibrate the phase and amplitude of the signal.
  • the phase / amplitude detection circuit according to the first embodiment is applied to an array antenna, there is no need to connect two transmission modules with a cable as described in Patent Document 1, and the phase of a signal can be obtained with one transmission module. Therefore, the degree of freedom in installing the transmission module in the array antenna can be ensured.
  • FIG. FIG. 4 is a configuration diagram of a phase amplitude detection circuit according to the second embodiment of the present invention.
  • the reference signal has a phase difference of 90 ° in the first state and the second state.
  • the first state and the second state The signal under measurement has a phase difference of 90 °.
  • the phase / amplitude detection circuit includes a switch 28, a terminator 4, a switch 29, a transmission line 30, a transmission line 31, a switch 32, a mixer 7, an LPF (Low Pass Filter) 8. , An A / D converter 9 and a signal processing circuit 10.
  • each terminal is the reference signal input terminal 11, the signal under test input terminal 12, the signal processing circuit 10 output terminal 13, the switch 28 input terminal 33, and the switch 28 two output terminals 34 and 35, respectively.
  • the input terminal of the switch 29 is 36
  • the two output terminals of the switch 29 are 37 and 38
  • the two input terminals of the switch 32 are 39 and 40, respectively
  • the output terminal of the switch 32 is 41.
  • the switch 28 has one input terminal 33 and two output terminals 34 and 35.
  • the input terminal 11 is connected to the input terminal 33, and a reference signal is input from the input terminal 11.
  • the switch 28 outputs the reference signal input to the input terminal 33 to one of the output terminals 34 and 35.
  • the output terminal 34 is connected to the mixer 7.
  • the output terminal 35 is connected to the terminator 4.
  • the switch 29 has one input terminal 36 and two output terminals 37 and 38.
  • the input terminal 12 is connected to the input terminal 36, and a signal under measurement is input from the input terminal 12.
  • the switch 29 outputs the signal under measurement input to the input terminal 36 to one of the output terminals 37 and 38.
  • the output terminal 37 is connected to the transmission line 30.
  • the output terminal 38 is connected to the transmission line 31.
  • the transmission line 30 is connected between the output terminal 37 of the switch 29 and the input terminal 39 of the switch 32.
  • the transmission line 30 shifts the phase of the signal under measurement input from the output terminal 37 of the switch 29 by 0 ° and outputs it to the input terminal 39 of the switch 32.
  • the transmission line 31 is connected between the output terminal 38 of the switch 29 and the input terminal 40 of the switch 32.
  • the transmission line 30 and the transmission line 31 are configured so that the electrical length differs by 90 °.
  • the transmission line 31 shifts the phase of the signal under measurement input from the output terminal 38 of the switch 29 by 90 ° and outputs it to the input terminal 40 of the switch 32.
  • the switch 32 has two input terminals 39 and 40 and one output terminal 41.
  • the switch 32 outputs the signal under measurement input to any one of the input terminals 39 and 40 from the output terminal 41 to the mixer 7.
  • phase / amplitude detection circuit in FIG. 4 may be the same as that of the phase / amplitude detection circuit according to the first embodiment, and thus the description thereof is omitted here.
  • the switches 28, 29, 32, the transmission lines 30, 31, and the terminator 4 are in the first state, the second state, and the third state.
  • a signal switching unit that operates by selecting one of the states is configured.
  • phase of the signal under measurement the relative phase ⁇ of the signal under measurement with respect to the reference signal, that is, the phase difference between the reference signal and the signal under measurement is obtained.
  • connection destination of the switch 28 is selected as the output terminal 34.
  • the reference signal input to the input terminal 11 is input to the input terminal 33 of the switch 28 and output from the output terminal 34 of the switch 28 to the mixer 7.
  • connection destination of the switch 29 is selected to the output terminal 37.
  • connection destination of the switch 29 is selected as the output terminal 37
  • connection destination of the switch 32 is selected as the input terminal 39.
  • the signal under measurement input to the input terminal 36 is output from the output terminal 37 of the switch 29 and input to the input terminal 39 of the switch 32 via the transmission line 30. Thereafter, the signal under measurement is output from the output terminal 41 of the switch 32 and input to the mixer 7.
  • the subsequent operations are the same as those in the first embodiment. That is, the reference signal and the signal under measurement are mixed by the mixer 7, and the voltage of the DC component included in the mixed wave output as a result is quantized by the A / D converter 9 and input to the signal processing circuit 10. Stored in memory.
  • the DC component voltage (I component) obtained here includes information on the phase difference between the reference signal and the signal under measurement.
  • connection destination of the switch 28 is selected as the output terminal 34.
  • the reference signal input to the input terminal 11 is input to the input terminal 33 of the switch 28 and output from the output terminal 34 of the switch 28 to the mixer 7.
  • connection destination of the switch 29 is selected as the output terminal 38
  • connection destination of the switch 32 is selected as the input terminal 40.
  • the signal under measurement input to the input terminal 12 is input to the input terminal 36 of the switch 29 and output from the output terminal 38 of the switch 29 to the transmission line 31.
  • the transmission line 31 shifts the phase of the signal under measurement by 90 ° and outputs it to the input terminal 40 of the switch 32.
  • the signal under measurement input to the input terminal 40 of the switch 32 is output from the output terminal 41 of the switch 32 and input to the mixer 7.
  • the subsequent operation is the same as when the connection destination of the switch 29 is selected as the output terminal 37. That is, the reference signal and the signal under measurement are mixed by the mixer 7, and the voltage of the DC component included in the mixed wave output as a result is quantized by the A / D converter 9 and input to the signal processing circuit 10. Stored in memory.
  • the DC component voltage (Q component) obtained here includes information on the phase difference between the reference signal and the signal under measurement.
  • is obtained by the above-described equation (1), where I is the voltage of I component, VQ is the voltage of Q component, V is the relative phase of the signal under measurement with respect to the reference signal,
  • connection destination of the switch 28 is selected as the output terminal 35.
  • the reference signal input to the input terminal 33 of the switch 28 is input from the output terminal 35 to the terminator 4 and not input to the mixer 7. This state is the third state described above.
  • connection destination of the switch 29 may select any of the output terminals 37 and 38.
  • connection destination of the switch 32 may select any of the input terminals 39 and 40.
  • Terminal 40 is used.
  • the mixer 7 operates as a detector.
  • the mixer 7 outputs a leakage component of the signal under measurement and a harmonic component of the signal under measurement in addition to the DC component.
  • LPF 8 passes the direct current component and blocks the passage of other components.
  • the DC component voltage output from the LPF 8 is quantized by the A / D converter 9 and converted into a digital signal.
  • the digital signal is input to the signal processing circuit 10.
  • the signal processing circuit 10 stores the digital signal in the memory as amplitude data of the signal under measurement.
  • the switch 28, the switch 29, and the switch 32 are sequentially switched to acquire three data of the I component, the Q component, and the amplitude, and the signal processing circuit 10 performs the calculation.
  • the signal processing circuit 10 performs the calculation.
  • FIG. 4 a circuit having a phase difference of 90 ° using the transmission line 30 and the transmission line 31 is shown.
  • the same effect can be obtained by using a 90 °, 3 dB coupler instead of the transmission lines 30, 31. Is obtained.
  • the configuration and operation of the 90 °, 3 dB coupler are the same as those of the 90 °, 3 dB coupler 22 described with reference to FIG. 2 in the first embodiment, and thus the description thereof is omitted here.
  • a phase shift of 90 ° can be provided using a phase shifter 57 instead of the transmission lines 30 and 31.
  • the switch 29 and the switch 32 can be eliminated, there is an effect that the phase / amplitude detection circuit is reduced in size.
  • connection destinations of the switches 28, 29, and 32 are switched in a predetermined cycle, for example, in the order of the first state, the second state, and the third state. Are performed sequentially.
  • the connection destinations of the switches 28, 29, and 32 may be switched based on an external control signal.
  • the relative phase ⁇ of the signal under measurement with respect to the reference signal and the measurement target are simply switched by switching the connection destination of the switches 28, 29, and 32.
  • the signal amplitude can be detected by the same circuit.
  • the circuit scale of the phase amplitude detection circuit can be reduced. Therefore, when the phase amplitude detection circuit of the second embodiment is applied to the transmission module and the array antenna, it is possible to detect and calibrate the signal phase and amplitude with a simple configuration.
  • phase amplitude detection circuit of the second embodiment when the phase amplitude detection circuit of the second embodiment is applied to a transmission module and an array antenna, it is not necessary to connect two transmission modules with a cable as in Patent Document 1, and one transmission module can Since the phase and amplitude can be detected, a degree of freedom in installing the transmission module can be ensured.
  • FIG. 6 is a configuration diagram of a transmission module and an array antenna according to the third embodiment of the present invention.
  • the array antenna includes a reference signal generation source 42, an in-phase distributor 43, a plurality of transmission modules 44, a plurality of element antennas 45, and a control circuit 46.
  • a transmission module 44 a and a transmission module 44 b are shown as the plurality of transmission modules 44.
  • the transmission module 44a and the transmission module 44b have the same configuration.
  • the number of transmission modules 44 may be an arbitrary number.
  • an element antenna 45 a and an element antenna 44 b are shown as the plurality of element antennas 45.
  • the element antenna 45a is connected to the transmission module 44a
  • the element antenna 45b is connected to the transmission module 44b.
  • one element antenna 45 is provided for each transmission module 44.
  • the element antenna 45a and the element antenna 45b have the same configuration.
  • the alphabets “a” and “b” are added to the end of the reference numerals so as to distinguish between the components provided in plural.
  • the transmission module 44a and the transmission module 44b have the same configuration, and the element antenna 45a and the element antenna 45b have the same configuration, in the following description, the transmission module 44a and the transmission module 44b are The element antenna 45a and the element antenna 44b are simply referred to as the “element antenna 44” without being distinguished from each other. The same applies to each component in the transmission module 44.
  • the transmission module 44 includes a directional coupler 47, a phase shifter 48, a variable attenuator 49, an amplifier 50, a directional coupler 51, and a phase amplitude detection circuit 52.
  • the phase amplitude detection circuit 52 is mounted in the transmission module 44.
  • the phase amplitude detection circuit 52 basically has the same configuration and function as any of the phase amplitude detection circuits shown in FIGS. 1 to 5 described in the first and second embodiments.
  • the phase amplitude detection circuit 52 according to the present embodiment further generates and outputs a phase control signal for the phase shifter 48 and an amplitude control signal for the variable attenuator 49. This point is different from the first and second embodiments.
  • the configuration of the phase amplitude detection circuit 52 will be described below with reference to FIG.
  • phase amplitude detection circuit 52 A configuration example of the phase amplitude detection circuit 52 is shown in FIG.
  • the configuration of the phase / amplitude detection circuit 52 is almost the same as the configuration of the phase / amplitude detection circuit shown in FIG. 1, but in FIG. 7, a signal processing circuit 56 is provided instead of the signal processing circuit 10 of FIG. ing.
  • the difference between the signal processing circuit 56 and the signal processing circuit 10 is that the signal processing circuit 56 generates and outputs a phase control signal for the phase shifter 48 and an amplitude control signal for the variable attenuator 49.
  • the reference signal input terminal 11 the signal under measurement input terminal 12, the control signal input terminal 53 from the control circuit 46 to the phase amplitude detection circuit 52, and the phase amplitude detection circuit 52 to the phase shifter 48.
  • the output terminal of the control signal to be output is 54
  • the output terminal of the control signal output from the phase amplitude detection circuit 52 to the variable attenuator 49 is 55.
  • the input terminal 11 and the input terminal 12 are the same as those shown in FIGS.
  • control circuit 46 outputs a control signal for setting the phase and amplitude of the signal supplied to the element antenna 45 for each element antenna 45 to the phase amplitude detection circuit 52 of each transmission module 44.
  • the reference signal generation source 42 outputs a reference signal.
  • a CW (Continuous Wave) signal is used as the reference signal.
  • the in-phase distributor 43 distributes the reference signal output from the reference signal generation source 42 to each transmission module 44 in the same phase.
  • the directional coupler 47 outputs a part of the reference signal output from the in-phase distributor 43 to the input terminal 11 and outputs the rest to the phase shifter 48.
  • phase control signal is input to the phase shifter 48 from the output terminal 54 of the phase amplitude detection circuit 52.
  • the phase shifter 48 changes the phase of the reference signal input from the directional coupler 47 according to the phase control signal.
  • the variable attenuator 49 receives an amplitude control signal from the output terminal 55 of the phase amplitude detection circuit 52.
  • the variable attenuator 49 changes the amplitude of the reference signal output from the phase shifter 48 according to the amplitude control signal.
  • the amplifier 50 amplifies the amplitude of the reference signal output from the variable attenuator 49.
  • the reference signal output from the amplifier 50 is input to the directional coupler 51.
  • the directional coupler 51 inputs a part of the reference signal input from the amplifier 50 to the input terminal 12, and the remaining signal is input to the element antenna 45.
  • the “part of the reference signal” input to the input terminal 12 is input to the phase amplitude detection circuit 52 as a signal under measurement.
  • the element antenna 45 radiates the signal input from the directional coupler 51 as a radio wave.
  • the phase amplitude detection circuit 52 receives a reference signal from the input terminal 11, receives a signal under measurement from the input terminal 12, and receives a control signal from the input terminal 53.
  • the phase amplitude detection circuit 52 performs the same operation as that described in the first and second embodiments, and detects the relative phase ⁇ of the signal under measurement with respect to the reference signal and the amplitude of the signal under measurement. Further, in the present embodiment, the phase amplitude detection circuit 52 compares the detected relative phase ⁇ with the set value of the phase set by the control signal input from the control circuit 46, and compares the relative phase ⁇ with the set value. A phase correction value corresponding to the difference between the two is obtained, and a phase shift amount value including the correction value is generated as a phase control signal and output to the phase shifter 48.
  • the phase amplitude detection circuit 52 compares the detected amplitude of the signal under measurement with the set value of the amplitude set by the control signal input from the control circuit 46, and compares the detected amplitude with the set value. An amplitude correction value corresponding to the difference is obtained, and an attenuation value with the correction value taken into account is generated as an amplitude control signal and output to the variable attenuator 49.
  • the phase / amplitude detection circuit 52 has a correction unit for generating the phase control signal and the amplitude control signal based on the phase correction value and the amplitude correction value.
  • the reference signal output from the reference signal generation source 42 is distributed in phase to each transmission module 44 by the in-phase distributor 43.
  • a part of the signal input to each transmission module 44 is output to the input terminal 11 by the directional coupler 47.
  • the remaining signal is input to the phase shifter 48.
  • the phase shifter 48 changes the phase of the signal by the amount of phase shift according to the phase control signal input from the output terminal 54 of the phase amplitude detection circuit 52 to the phase shifter 48.
  • a signal output from the phase shifter 48 is input to the variable attenuator 49.
  • the variable attenuator 49 changes the amplitude of the signal by an attenuation amount according to the amplitude control signal output from the output terminal 55 of the phase amplitude detection circuit 52.
  • a signal output from the variable attenuator 49 is input to the amplifier 50.
  • the amplifier 50 amplifies the amplitude of the signal.
  • a part of the signal output from the amplifier 50 is output to the input terminal 12 by the directional coupler 51, and the remaining signal is radiated as a radio wave from the element antenna 45.
  • phase amplitude detection circuit 52 Next, the operation of the phase amplitude detection circuit 52 will be described.
  • a part of the reference signal input to the transmission module 44 by the directional coupler 47 is input to the input terminal 11.
  • a part of the signal under measurement output from the amplifier 50 is input to the input terminal 12 by the directional coupler 51.
  • a control signal for setting the phase and amplitude of the signal supplied to the element antenna 45 is input from the control circuit 46 to the input terminal 53.
  • a digital signal including information on the relative phase ⁇ of the signal under measurement with respect to the reference signal and the amplitude of the signal under measurement is A / Since the operation until the D converter 9 outputs is as described in the first embodiment and the second embodiment, the description thereof is omitted here.
  • the three digital signals of I component, Q component, and amplitude output from the A / D converter 9 are input to the signal processing circuit 56 and stored in the memory.
  • the signal processing circuit 56 obtains the relative phase ⁇ of the signal under measurement with respect to the reference signal from the voltage VI of the I component and the voltage VQ of the Q component by the above-described equation (1). Further, the signal processing circuit 56 compares the value of ⁇ obtained by the equation (1) with the set value of the phase input from the input terminal 53, obtains a phase correction value corresponding to the difference, and performs the correction. A new phase shift amount is calculated based on the value, and the phase shift amount is output from the output terminal 54 as a phase control signal.
  • the signal processing circuit 56 calculates the amplitude of the signal under measurement from the digital signal input from the A / D converter 9. Then, the signal processing circuit 56 compares the calculated amplitude value with the set amplitude value input from the input terminal 53 to obtain an amplitude correction value corresponding to the difference, and based on the correction value. The new attenuation amount is calculated, and the attenuation amount is output from the output terminal 55 as an amplitude control signal.
  • phase control signal output from the output terminal 54 of the phase amplitude detection circuit 52 is input to the phase shifter 48.
  • the phase of the reference signal is changed from the current value by the amount of phase shift based on the phase control signal.
  • the amplitude control signal output from the output terminal 55 of the phase amplitude detection circuit 52 is input to the variable attenuator 49.
  • the variable attenuator 49 changes the amplitude of the reference signal from the current value by the amount of attenuation based on the amplitude control signal.
  • control circuit 46 sets the phase and amplitude of the signal supplied to each element antenna 45 by correcting the characteristic variation among the individual amplifiers 50 and the variation in the phase characteristic and amplitude characteristic due to temperature. It is possible to approach the set values of the phase and the amplitude, respectively.
  • the signal processing circuit 56 includes the phase control signal and the amplitude control in consideration of the phase and amplitude correction values in addition to the functions of the signal processing circuit 10 described in the first and second embodiments. It has a function of a correction circuit that generates a signal.
  • the array antenna shown in FIG. 6 uses the same circuit to detect the phase and amplitude of the signal under measurement. Moreover, since it is not necessary to connect the output terminals of adjacent transmission modules with a cable as in Patent Document 1, it is possible to increase the flexibility of arrangement of the transmission modules and calibrate the phase and amplitude of the signal with a simple configuration. is there.
  • FIG. 7 based on the configuration of FIG. 1 is shown as a configuration example of the phase amplitude detection circuit 52, the configurations of FIGS. 2 to 5 may be used.
  • FIG. 6 shows an example in which two transmission modules 44 are provided.
  • the present invention is not limited to this, and an arbitrary number of transmission modules 44 may be provided. In that case, the same effect can be obtained.
  • the transmission module 44 receives the reference signal, the phase control signal, and the amplitude control signal from the outside, changes the phase of the reference signal in accordance with the phase control signal, and changes the amplitude.
  • a phase shifter 48 and a variable attenuator 49 that change the amplitude of the reference signal in accordance with the control signal, an amplifier 50 that amplifies the amplitude of the signal output from the phase amplitude switching unit, and a phase amplitude switching
  • a phase amplitude detection circuit 52 that receives the reference signal input to the unit and the signal under measurement that is the output signal of the amplifier 50 and calculates the phase difference between the reference signal and the signal under measurement and the amplitude of the signal under measurement. I have.
  • the phase amplitude detection circuit 52 compares the calculated phase difference value with the phase setting value input from the outside, and includes information on the amount of phase shift that takes into account the phase correction value corresponding to the difference.
  • An amplitude control signal that outputs a phase control signal, compares the calculated amplitude value with an externally input amplitude setting value, and includes attenuation information that takes into account the amplitude correction value corresponding to the difference between them Has a correction circuit as a correction unit for outputting. Therefore, similarly to the first and second embodiments described above, it is possible to detect the phase and amplitude of the transmission signal with one phase amplitude detection circuit.
  • Patent Document 1 it is not necessary to connect two transmission modules with a cable, and the phase and amplitude of a transmission signal can be detected with one transmission module. As a result, it is possible to ensure the degree of freedom in installing the transmission module.
  • the array antenna according to the present embodiment includes a plurality of transmission modules 44, and an element antenna 45 that radiates a signal output from the amplifier 50 of each transmission module 44 as a radio wave, and is in phase with the transmission module.
  • a reference signal generation source 42 for inputting a reference signal and an in-phase distributor 43 are provided. Therefore, in the array antenna, the phase and amplitude of the transmission signal can be detected for each transmission module, and the phase and amplitude of the transmission signal can be calibrated with a simple configuration. Therefore, there is an effect that the degree of freedom of arrangement of the transmission modules in the array antenna is ensured, and the design work of the array antenna becomes easy.

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Variable-Direction Aerials And Aerial Arrays (AREA)
  • Monitoring And Testing Of Transmission In General (AREA)
  • Measurement Of Resistance Or Impedance (AREA)

Abstract

Provided is a phase and amplitude detection circuit comprising: switches 1, 5 that, using transmission lines 2,3, operate to sequentially switch among three states, namely a first state in which the phase of a reference signal is varied by 0° and then output, a second state in which the phase of the reference signal is varied by 90° and then output, and a third state in which passage of the reference signal is blocked; a mixer 7 that mixes the reference signal and a signal to be measured if in the first or second state, and detects the amplitude of the signal to be measured if in the third state; an LPF 8 that extracts the direct current component from a signal output from the mixer 7; an A/D converter 9 that converts the voltage value of the direct current component output from the LPF 8 to a digital signal; and a signal processing circuit 10 that, in the case of the first state and the second state, calculates the phase difference between the reference signal and the signal to be measured on the basis of two digital signals output respectively from the A/D converter 9, and that, in the case of the third state, calculates the amplitude of the signal to be measured on the basis of the digital signal output from the A/D converter 9.

Description

位相振幅検波回路、送信モジュール、および、アレーアンテナPhase amplitude detection circuit, transmission module, and array antenna
 この発明は、位相振幅検波回路に関し、特に、送信信号の位相および振幅を検出する位相振幅検波回路、および、それを用いた送信モジュール及びアレーアンテナに関する。 The present invention relates to a phase / amplitude detection circuit, and more particularly to a phase / amplitude detection circuit for detecting the phase and amplitude of a transmission signal, and a transmission module and an array antenna using the same.
 複数の素子アンテナを並べ、各素子アンテナを励振する信号の振幅および位相を制御することで、電波を放射する方向に指向性を持たせることのできるアンテナをアレーアンテナという。 An antenna that can have directivity in the direction of radiating radio waves by arranging a plurality of element antennas and controlling the amplitude and phase of a signal that excites each element antenna is called an array antenna.
 図8に、従来の送信用アレーアンテナの一例を示す。図8に示すように、従来の送信用アレーアンテナは、基準信号発生源101、同相分配器102、複数の送信モジュール103、および、複数の素子アンテナ104から構成されている。図8においては、複数の送信モジュール103として、送信モジュール103aと送信モジュール103bとが示されている。送信モジュール103aと送信モジュール103bとは同じ構成を有している。各送信モジュール103は、移相器105、可変減衰器106、および、増幅器107から構成される。また、図8においては、複数の素子アンテナ104として、素子アンテナ104aと素子アンテナ104bとが示されている。素子アンテナ104aは送信モジュール103aに接続され、素子アンテナ104bは送信モジュール103bに接続されている。素子アンテナ104aと素子アンテナ104bとは同じ構成を有している。 FIG. 8 shows an example of a conventional transmitting array antenna. As shown in FIG. 8, the conventional transmission array antenna includes a reference signal generation source 101, an in-phase distributor 102, a plurality of transmission modules 103, and a plurality of element antennas 104. In FIG. 8, a transmission module 103a and a transmission module 103b are shown as the plurality of transmission modules 103. The transmission module 103a and the transmission module 103b have the same configuration. Each transmission module 103 includes a phase shifter 105, a variable attenuator 106, and an amplifier 107. In FIG. 8, an element antenna 104a and an element antenna 104b are shown as the plurality of element antennas 104. The element antenna 104a is connected to the transmission module 103a, and the element antenna 104b is connected to the transmission module 103b. The element antenna 104a and the element antenna 104b have the same configuration.
 なお、図8においては、複数個ずつ設けられている構成要素については、それらを区別できるように、符号の末尾に、「a」,「b」というアルファベットを付している。しかしながら、送信モジュール103aと送信モジュール103bとは同じ構成を有し、素子アンテナ104aと素子アンテナ104bとは同じ構成を有しているため、以下の説明においては、送信モジュール103aと送信モジュール103bとを区別せずに、単に「送信モジュール103」と呼び、同様に、素子アンテナ104aと素子アンテナ104bとを区別せずに、単に「素子アンテナ104」と呼ぶこととする。 In addition, in FIG. 8, the alphabets “a” and “b” are attached to the end of the reference numerals so as to distinguish between the plurality of components provided. However, since the transmission module 103a and the transmission module 103b have the same configuration, and the element antenna 104a and the element antenna 104b have the same configuration, in the following description, the transmission module 103a and the transmission module 103b are The element antenna 104a and the element antenna 104b are simply referred to as the “element antenna 104” without being distinguished from each other.
 次に、図8に示す従来の送信用アレーアンテナの動作について説明する。
 基準信号発生源101は、基準信号を出力する。当該基準信号は、同相分配器102に入力される。同相分配器102は、当該基準信号を各送信モジュール103に対して同相で分配する。
Next, the operation of the conventional transmitting array antenna shown in FIG. 8 will be described.
The reference signal generation source 101 outputs a reference signal. The reference signal is input to the in-phase distributor 102. The in-phase distributor 102 distributes the reference signal to each transmission module 103 in the same phase.
 各送信モジュール103においては、同相分配器102から入力された信号が、移相器105に入力される。また、移相器105には外部から位相制御信号が入力される。移相器105は、当該信号の位相を、外部から入力された位相制御信号に応じた移相量だけ変化させる。移相器105から出力される信号は、可変減衰器106に入力される。可変減衰器106には外部から振幅制御信号が入力される。可変減衰器106は、移相器105から出力された信号の振幅を、外部から入力された振幅制御信号に応じた減衰量だけ変化させる。可変減衰器106から出力された信号は、増幅器107に入力される。増幅器107は、可変減衰器106から出力された信号の振幅を増幅する。増幅器107から出力された信号は、素子アンテナ104に入力される。素子アンテナ104は、当該信号を電波として放射する。 In each transmission module 103, the signal input from the in-phase distributor 102 is input to the phase shifter 105. A phase control signal is input to the phase shifter 105 from the outside. The phase shifter 105 changes the phase of the signal by the amount of phase shift corresponding to the phase control signal input from the outside. A signal output from the phase shifter 105 is input to the variable attenuator 106. An amplitude control signal is input to the variable attenuator 106 from the outside. The variable attenuator 106 changes the amplitude of the signal output from the phase shifter 105 by the amount of attenuation corresponding to the amplitude control signal input from the outside. The signal output from the variable attenuator 106 is input to the amplifier 107. The amplifier 107 amplifies the amplitude of the signal output from the variable attenuator 106. The signal output from the amplifier 107 is input to the element antenna 104. The element antenna 104 radiates the signal as a radio wave.
 図8に示した構成要素101~107の中で、特に、増幅器107が、個体間での特性のばらつきが大きく、かつ、その特性は、温度により大きく変動する。そのため、増幅器107の特性の不安定さに起因して、各素子アンテナ104に供給される信号の振幅および位相が、位相制御信号及び振幅制御信号に基づいて移相器105および可変減衰器106に設定された値から変動してしまい、各素子アンテナ104において所望の指向性が得られない可能性がある。そこで、各素子アンテナ104に供給される信号の振幅および位相を検出し、校正する必要がある。 Among the constituent elements 101 to 107 shown in FIG. 8, in particular, the amplifier 107 has a large variation in characteristics among individuals, and the characteristics vary greatly with temperature. Therefore, due to the unstable characteristics of the amplifier 107, the amplitude and phase of the signal supplied to each element antenna 104 are transferred to the phase shifter 105 and the variable attenuator 106 based on the phase control signal and the amplitude control signal. There is a possibility that the desired directivity may not be obtained in each element antenna 104 because the value fluctuates from the set value. Therefore, it is necessary to detect and calibrate the amplitude and phase of the signal supplied to each element antenna 104.
 従来の校正方法として、例えば、特許文献1に記載の方法がある。 For example, there is a method described in Patent Document 1 as a conventional calibration method.
 特許文献1では、隣接する送信モジュールの出力端子間をケーブルで接続し、それらの送信モジュールの送信信号の振幅差および位相差を検出する。そうして、検出した振幅差および位相差が無くなるように、一方の送信モジュールの送信信号の振幅および位相を校正する。しかしながら、この構成は、2つの送信モジュールの出力端子間をケーブルで接続する必要があるため、それらの送信モジュールの配置の自由度が低くなるという問題がある。 In Patent Document 1, the output terminals of adjacent transmission modules are connected with a cable, and the amplitude difference and phase difference of the transmission signals of those transmission modules are detected. Then, the amplitude and phase of the transmission signal of one transmission module are calibrated so that the detected amplitude difference and phase difference are eliminated. However, since this configuration requires that the output terminals of the two transmission modules be connected by a cable, there is a problem in that the degree of freedom of arrangement of these transmission modules is reduced.
 一般的に、素子アンテナ104の配列は、アレーアンテナとして実現したい機能に応じて決定される。一方、送信モジュール103の設置場所は、素子アンテナ104の配列に依存するだけでなく、送信モジュール103自身のサイズ、重量、並びに、図8に示されていない他の構成要素のサイズ、重量などにも依存する。そのため、送信モジュール103の設置に関しては、なるべく自由度があることが望ましい。 Generally, the arrangement of the element antennas 104 is determined according to a function to be realized as an array antenna. On the other hand, the installation location of the transmission module 103 depends not only on the arrangement of the element antennas 104 but also on the size and weight of the transmission module 103 itself and the size and weight of other components not shown in FIG. Also depends. For this reason, it is desirable that the transmission module 103 has a degree of freedom as much as possible.
 そのため、複数の送信モジュールをケーブルで接続せずに、1つの送信モジュールごとに送信信号の位相が検出できることが望ましい。 Therefore, it is desirable that the phase of the transmission signal can be detected for each transmission module without connecting a plurality of transmission modules with cables.
 従来の送信用アレーアンテナでは、図8に示すように、同相分配器102を用いて、各送信モジュール103に、基準信号を分配している。また、各送信モジュール103に分配される基準信号は同相である。そのため、各送信モジュール103において、送信モジュールによって送信される送信信号と基準信号との間の位相差を検出すれば、各素子アンテナ104に供給する送信信号の位相を校正することが可能である。 In the conventional transmitting array antenna, as shown in FIG. 8, a reference signal is distributed to each transmission module 103 using an in-phase distributor 102. The reference signal distributed to each transmission module 103 is in phase. Therefore, in each transmission module 103, if the phase difference between the transmission signal transmitted by the transmission module and the reference signal is detected, the phase of the transmission signal supplied to each element antenna 104 can be calibrated.
 そのことを利用した位相検波回路が、例えば特許文献2に記載されている。特許文献2に記載の位相検波回路では、送信信号と基準信号との間の位相差を検出することで、送信信号の位相を検出している。特許文献2に記載の位相検波回路においては、基準信号の位相を0°あるいは90°変化させる移相手段を有し、0°あるいは90°移相した基準信号と送信信号とを単一のミクサで混合する。 For example, Patent Document 2 discloses a phase detection circuit using this fact. In the phase detection circuit described in Patent Document 2, the phase of the transmission signal is detected by detecting the phase difference between the transmission signal and the reference signal. The phase detection circuit described in Patent Document 2 has phase shift means for changing the phase of the reference signal by 0 ° or 90 °, and the reference signal and the transmission signal shifted by 0 ° or 90 ° are combined into a single mixer. Mix with.
 特許文献2では、基準信号が0°に移相された状態の場合にミクサから出力される電圧(I成分)と、基準信号が90°に移相された状態の場合にミクサから出力される電圧(Q成分)とを、時分割でそれぞれ取得する。そうして、それら2つの電圧に基づいて基準信号と送信信号との位相差を検出する。また、検出した位相差に基づいて、送信モジュールごとに、送信信号の位相を検出する。そうして、検出した位相と所望の位相との差を算出することにより、各送信モジュールの送信信号の位相の校正を行う。 In Patent Document 2, a voltage (I component) output from the mixer when the reference signal is shifted to 0 ° and a voltage output from the mixer when the reference signal is shifted to 90 °. The voltage (Q component) is acquired in time division. Then, the phase difference between the reference signal and the transmission signal is detected based on these two voltages. Further, the phase of the transmission signal is detected for each transmission module based on the detected phase difference. Then, the phase of the transmission signal of each transmission module is calibrated by calculating the difference between the detected phase and the desired phase.
特開2016-122895号公報Japanese Unexamined Patent Publication No. 2016-122895 特開昭64-068107号公報JP-A 64-068107
 上述のように、特許文献1においては、送信信号の位相と振幅の検出において2つの送信モジュールが必要であり、単一の送信モジュールだけでは、送信信号の位相と振幅とを検出することができないという問題点があった。 As described above, in Patent Document 1, two transmission modules are required for detection of the phase and amplitude of a transmission signal, and the phase and amplitude of the transmission signal cannot be detected with only a single transmission module. There was a problem.
 また、特許文献2に示された位相検波回路では、送信信号の位相を検出することはできるが、送信信号の振幅を検出することはできないという問題点があった。また、もし、特許文献2において、送信信号の振幅を検出しようとした場合には、振幅を検出するための別の回路を追加する必要がある。そのため、回路規模の増大につながるという問題点があった。 In addition, the phase detection circuit disclosed in Patent Document 2 has a problem that it can detect the phase of the transmission signal but cannot detect the amplitude of the transmission signal. In Patent Document 2, when it is attempted to detect the amplitude of the transmission signal, it is necessary to add another circuit for detecting the amplitude. Therefore, there is a problem that the circuit scale increases.
 この発明は、かかる問題点を解決するためになされたものであり、送信信号の位相と振幅とを1つの回路で検出することを可能にした、位相振幅検波回路、および、それを用いた送信モジュール及びアレーアンテナを提供することを目的とする。 The present invention has been made to solve such a problem, and a phase / amplitude detection circuit capable of detecting the phase and amplitude of a transmission signal with a single circuit, and transmission using the same. An object is to provide a module and an array antenna.
 この発明は、基準信号及び被測定信号が入力され、前記基準信号および前記被測定信号の位相を0°変化させて前記基準信号および前記被測定信号を出力する第1の状態、前記基準信号または前記被測定信号のいずれか一方の位相のみを90°変化させて前記基準信号および前記被測定信号を出力する第2の状態、および、前記基準信号の通過を遮断して前記被測定信号のみを出力する第3の状態の3つの状態を順に切り替えて動作する信号切替部と、前記信号切替部に接続され、前記信号切替部の状態が前記第1の状態または前記第2の状態の場合に前記基準信号と前記被測定信号とを混合させるとともに、前記信号切替部の状態が前記第3の状態の場合に前記被測定信号の振幅を検波する、ミクサと、前記ミクサから出力される信号から直流成分を抽出する低域通過フィルタと、前記低域通過フィルタから出力される前記直流成分の電圧をディジタル信号に変換するA/D変換器と、前記信号切替部が前記第1の状態及び前記第2の状態の場合に前記A/D変換器から出力される2つの前記ディジタル信号に基づいて前記基準信号と前記被測定信号との位相差を算出するとともに、前記信号切替部が前記第3の状態の場合に前記A/D変換器から出力される前記ディジタル信号に基づいて前記被測定信号の振幅を算出する信号処理回路とを備えた、位相振幅検波回路である。 The present invention provides a first state in which a reference signal and a signal under measurement are input, the phase of the reference signal and the signal under measurement is changed by 0 °, and the reference signal and the signal under measurement are output, the reference signal or A second state in which only one phase of the signal under measurement is changed by 90 ° to output the reference signal and the signal under measurement, and only the signal under measurement is blocked by passing the reference signal A signal switching unit that operates by sequentially switching the three states of the third state to be output, and the signal switching unit connected to the signal switching unit, and the state of the signal switching unit is the first state or the second state From the mixer that mixes the reference signal and the signal under measurement and detects the amplitude of the signal under measurement when the state of the signal switching unit is the third state, and a signal output from the mixer A low-pass filter that extracts a DC component, an A / D converter that converts a voltage of the DC component output from the low-pass filter into a digital signal, and the signal switching unit includes the first state and the A phase difference between the reference signal and the signal under measurement is calculated based on the two digital signals output from the A / D converter in the second state, and the signal switching unit is configured to output the third signal. And a signal processing circuit that calculates the amplitude of the signal under measurement based on the digital signal output from the A / D converter in the state of (2).
 この発明に係る位相振幅検波回路によれば、信号切替部によって第1の状態、第2の状態、および、第3の状態を順に切り替えて、3つの状態におけるディジタル信号をA/D変換器から得て、当該ディジタル信号に基づいて信号処理回路が被測定信号の位相と振幅とを算出するようにしたので、被測定信号の位相の検出と振幅の検出とを1つの回路で行うことができるという効果が得られる。 According to the phase amplitude detection circuit of the present invention, the signal switching unit sequentially switches the first state, the second state, and the third state, and the digital signal in the three states is sent from the A / D converter. Thus, since the signal processing circuit calculates the phase and amplitude of the signal under measurement based on the digital signal, the phase and amplitude of the signal under measurement can be detected by a single circuit. The effect is obtained.
この発明の実施の形態1に係る位相振幅検波回路の構成を示す構成図である。It is a block diagram which shows the structure of the phase amplitude detection circuit which concerns on Embodiment 1 of this invention. この発明の実施の形態1に係る位相振幅検波回路の変形例の構成を示す構成図である。It is a block diagram which shows the structure of the modification of the phase amplitude detection circuit which concerns on Embodiment 1 of this invention. この発明の実施の形態1に係る位相振幅検波回路の変形例の構成を示す構成図である。It is a block diagram which shows the structure of the modification of the phase amplitude detection circuit which concerns on Embodiment 1 of this invention. この発明の実施の形態2に係る位相振幅検波回路の構成を示す構成図である。It is a block diagram which shows the structure of the phase amplitude detection circuit which concerns on Embodiment 2 of this invention. この発明の実施の形態2に係る位相振幅検波回路の変形例の構成を示す構成図である。It is a block diagram which shows the structure of the modification of the phase amplitude detection circuit which concerns on Embodiment 2 of this invention. この発明の実施の形態3に係る送信モジュール及びアレーアンテナの構成を示す構成図である。It is a block diagram which shows the structure of the transmission module and array antenna which concern on Embodiment 3 of this invention. この発明の実施の形態3に係るアレーアンテナを構成する位相振幅検波回路の構成を示す構成図である。It is a block diagram which shows the structure of the phase amplitude detection circuit which comprises the array antenna which concerns on Embodiment 3 of this invention. 従来の送信用アレーアンテナの一例を示す構成図である。It is a block diagram which shows an example of the conventional array antenna for transmission.
 実施の形態1.
 図1は、この発明の実施の形態1に係る位相振幅検波回路の構成を示す構成図である。位相振幅検波回路は、基準信号と被測定信号とが入力されて、基準信号と被測定信号との位相差と被測定信号の振幅とを検出するための回路である。図1に示すように、位相振幅検波回路は、スイッチ1、伝送線路2、伝送線路3、終端器4、スイッチ5、終端器6、ミクサ7、LPF(Low Pass Filter)8、A/D変換器9、信号処理回路10とから構成される。
Embodiment 1 FIG.
FIG. 1 is a configuration diagram showing the configuration of a phase amplitude detection circuit according to Embodiment 1 of the present invention. The phase amplitude detection circuit is a circuit for receiving a reference signal and a signal under measurement and detecting a phase difference between the reference signal and the signal under measurement and an amplitude of the signal under measurement. As shown in FIG. 1, the phase / amplitude detection circuit includes a switch 1, a transmission line 2, a transmission line 3, a terminator 4, a switch 5, a terminator 6, a mixer 7, an LPF (Low Pass Filter) 8, and an A / D conversion. And a signal processing circuit 10.
 また、説明の便宜上、図1に示すように、各端子に符号11~21を割り振る。すなわち、基準信号の入力端子を11、被測定信号の入力端子を12、信号処理回路10の出力端子を13、スイッチ1の入力端子を14、スイッチ1の3つの出力端子をそれぞれ15,16,17、スイッチ5の3つの入力端子をそれぞれ18,19,20、スイッチ5の出力端子を21とする。 Also, for convenience of explanation, reference numerals 11 to 21 are assigned to the terminals as shown in FIG. That is, the reference signal input terminal 11, the signal under test input terminal 12, the signal processing circuit 10 output terminal 13, the switch 1 input terminal 14, and the switch 1 three output terminals 15, 16, respectively. 17, the three input terminals of the switch 5 are 18, 19, 20 and the output terminal of the switch 5 is 21, respectively.
 位相振幅検波回路の入力端子11には、基準信号が入力される。入力端子11には、例えば、基準信号発生源が接続されている。ここでは、基準信号として、例えば、CW(Continuous Wave)信号を用いる。 The reference signal is input to the input terminal 11 of the phase amplitude detection circuit. For example, a reference signal generation source is connected to the input terminal 11. Here, for example, a CW (Continuous Wave) signal is used as the reference signal.
 位相振幅検波回路の入力端子12には、測定対象の被測定信号が入力される。ここでは、被測定信号の例として、例えば、送信モジュールから送信される送信信号が挙げられる。 The signal under measurement to be measured is input to the input terminal 12 of the phase amplitude detection circuit. Here, as an example of the signal under measurement, for example, a transmission signal transmitted from the transmission module can be cited.
 スイッチ1は、1つの入力端子14と3つの出力端子15,16,17を有している。スイッチ1の入力端子14は、位相振幅検波回路の入力端子11に接続され、入力端子11から基準信号が入力される。スイッチ1の接続先は、3つの出力端子15,16,17の中から1つが選択される。スイッチ1は、接続先の状態に応じて、入力端子14に入力される基準信号を、出力端子15,16,17のいずれか1つから出力する。なお、スイッチ1の接続先の切り替えは、予め設定された周期で、例えば出力端子15,16,17の順で、順次行われる。あるいは、外部からの制御信号に基づいてスイッチ1の接続先の切り替えを行うようにしてもよい。 The switch 1 has one input terminal 14 and three output terminals 15, 16, and 17. The input terminal 14 of the switch 1 is connected to the input terminal 11 of the phase amplitude detection circuit, and a reference signal is input from the input terminal 11. As the connection destination of the switch 1, one of the three output terminals 15, 16, and 17 is selected. The switch 1 outputs a reference signal input to the input terminal 14 from any one of the output terminals 15, 16, and 17 according to the state of the connection destination. Note that switching of the connection destination of the switch 1 is sequentially performed in a preset cycle, for example, in the order of the output terminals 15, 16, and 17. Alternatively, the connection destination of the switch 1 may be switched based on an external control signal.
 伝送線路2は、スイッチ1の出力端子15とスイッチ5の入力端子18との間に接続されている。伝送線路2は、スイッチ1の出力端子15から基準信号が入力され、当該基準信号をスイッチ5の入力端子18に出力する。 The transmission line 2 is connected between the output terminal 15 of the switch 1 and the input terminal 18 of the switch 5. The transmission line 2 receives a reference signal from the output terminal 15 of the switch 1 and outputs the reference signal to the input terminal 18 of the switch 5.
 伝送線路3は、スイッチ1の出力端子16とスイッチ5の入力端子19との間に接続されている。伝送線路3は、スイッチ1の出力端子16から基準信号が入力され、当該基準信号をスイッチ5の入力端子19に出力する。 The transmission line 3 is connected between the output terminal 16 of the switch 1 and the input terminal 19 of the switch 5. The transmission line 3 receives a reference signal from the output terminal 16 of the switch 1 and outputs the reference signal to the input terminal 19 of the switch 5.
 ここで、伝送線路2と伝送線路3とは電気長が互いに90°異なるように構成されている。図1の例においては、伝送線路2は基準信号の位相を0°変化させて出力し、すなわち、伝送線路2は基準信号をそのまま出力し、伝送線路3は基準信号の位相を90°変化させて出力する。 Here, the transmission line 2 and the transmission line 3 are configured such that their electrical lengths are 90 ° different from each other. In the example of FIG. 1, the transmission line 2 changes the phase of the reference signal by 0 ° and outputs it, that is, the transmission line 2 outputs the reference signal as it is, and the transmission line 3 changes the phase of the reference signal by 90 °. Output.
 終端器4は、スイッチ1の出力端子17に接続されている。終端器4は、スイッチ1の出力端子17に入力される基準信号を終端し、当該基準信号のスイッチ5への出力を遮断する。 The terminator 4 is connected to the output terminal 17 of the switch 1. The terminator 4 terminates the reference signal input to the output terminal 17 of the switch 1 and blocks the output of the reference signal to the switch 5.
 スイッチ5は、3つの入力端子18,19,20と1つの出力端子21とを有している。スイッチ5の出力端子21はミクサ7に接続されている。スイッチ5の接続先は、3つの入力端子18,19,20の中から1つが選択される。スイッチ5は、接続先の状態に応じて、入力端子18,19のいずれか1つに入力された基準信号を、出力端子21からミクサ7に出力する。なお、スイッチ5の接続先の切り替えは、スイッチ1の接続先の切り替えと同期して行われる。 The switch 5 has three input terminals 18, 19, 20 and one output terminal 21. An output terminal 21 of the switch 5 is connected to the mixer 7. As the connection destination of the switch 5, one of the three input terminals 18, 19, and 20 is selected. The switch 5 outputs the reference signal input to any one of the input terminals 18 and 19 from the output terminal 21 to the mixer 7 according to the state of the connection destination. Note that switching of the connection destination of the switch 5 is performed in synchronization with switching of the connection destination of the switch 1.
 終端器6は、スイッチ5の入力端子20に接続されている。終端器6は、スイッチ5の接続先が入力端子20の場合に、入力端子20に入力される信号を終端し、当該信号のミクサ7への出力を遮断する。 The terminator 6 is connected to the input terminal 20 of the switch 5. When the connection destination of the switch 5 is the input terminal 20, the terminator 6 terminates the signal input to the input terminal 20 and blocks the output of the signal to the mixer 7.
 ミクサ7は、位相振幅検波回路の入力端子12に接続され、入力端子12から被測定信号が入力される。また、ミクサ7は、スイッチ5の出力端子21に接続されている。ミクサ7は、スイッチ5の出力端子21から入力される基準信号と、入力端子12から入力される被測定信号とを混合し、基準信号と被測定信号との和周波数成分、差周波数成分、および、高次の混合波成分の3つの成分を含む混合波をLPF8に出力する。ここで、基準信号と被測定信号とは周波数が同一であるため、2つの信号の差周波数成分は直流成分、すなわち、一定値となる。当該直流成分は、基準信号と被測定信号との位相差に対応した電圧値を有する。一方、基準信号が終端器4により終端された場合には、ミクサ7には、被測定信号のみが入力される。その場合には、ミクサ7は、被測定信号を検波して、被測定信号の振幅に応じた直流成分を含む混合波をLPF8に出力する。当該直流成分は、被測定信号の振幅に対応した電圧値を有する。 The mixer 7 is connected to the input terminal 12 of the phase amplitude detection circuit, and the signal under measurement is input from the input terminal 12. The mixer 7 is connected to the output terminal 21 of the switch 5. The mixer 7 mixes the reference signal input from the output terminal 21 of the switch 5 and the signal under measurement input from the input terminal 12, and the sum frequency component, the difference frequency component of the reference signal and the signal under measurement, and The mixed wave including the three components of the higher-order mixed wave component is output to the LPF 8. Here, since the reference signal and the signal under measurement have the same frequency, the difference frequency component between the two signals is a DC component, that is, a constant value. The DC component has a voltage value corresponding to the phase difference between the reference signal and the signal under measurement. On the other hand, when the reference signal is terminated by the terminator 4, only the signal under measurement is input to the mixer 7. In that case, the mixer 7 detects the signal under measurement and outputs a mixed wave including a DC component corresponding to the amplitude of the signal under measurement to the LPF 8. The DC component has a voltage value corresponding to the amplitude of the signal under measurement.
 LPF8は、ミクサ7から出力される混合波に含まれる複数の成分のうち、直流成分のみを抽出してA/D変換器9に出力する。LPF8は、当該混合波に含まれる他の成分については遮断して出力しない。 The LPF 8 extracts only the DC component from the plurality of components included in the mixed wave output from the mixer 7 and outputs it to the A / D converter 9. The LPF 8 blocks other components included in the mixed wave and does not output them.
 A/D変換器9は、LPF8から出力される直流成分の電圧値を量子化して、ディジタル信号に変換する。当該ディジタル信号には、基準信号と被測定信号との位相差に対応した電圧値の情報と被測定信号の振幅に対応した電圧値の情報とが含まれている。当該ディジタル信号は、信号処理回路10に入力される。 The A / D converter 9 quantizes the DC component voltage value output from the LPF 8 and converts it into a digital signal. The digital signal includes voltage value information corresponding to the phase difference between the reference signal and the signal under measurement and voltage value information corresponding to the amplitude of the signal under measurement. The digital signal is input to the signal processing circuit 10.
 信号処理回路10は、A/D変換器9から出力されるディジタル信号に基づいて、基準信号に対する被測定信号の相対位相と被測定信号の振幅とを算出する。 The signal processing circuit 10 calculates the relative phase of the signal under measurement with respect to the reference signal and the amplitude of the signal under measurement based on the digital signal output from the A / D converter 9.
 位相振幅検波回路の出力端子13は、信号処理回路10で算出された相対位相と振幅とを外部に出力する。 The output terminal 13 of the phase / amplitude detection circuit outputs the relative phase and amplitude calculated by the signal processing circuit 10 to the outside.
 図1においては、スイッチ1、伝送線路2、伝送線路3、終端器4、および、スイッチ5が、基準信号と被測定信号の出力を切り替える「信号切替部」を構成している。信号切替部は、以下の(1)~(3)の3つの状態を有しており、それらの状態のうちの1つを選択して動作する。信号切替部の3つの状態は、スイッチ1及びスイッチ5の接続先の切り替えによって、切り替えられる。
 (1)基準信号および被測定信号の位相を0°変化させて基準信号および被測定信号を出力する第1の状態、
 (2)基準信号または被測定信号のいずれか一方の位相のみを90°変化させて基準信号および被測定信号を出力する第2の状態、
 (3)基準信号の通過を遮断して被測定信号のみを出力する第3の状態。
In FIG. 1, the switch 1, the transmission line 2, the transmission line 3, the terminator 4, and the switch 5 constitute a “signal switching unit” that switches the output of the reference signal and the signal under measurement. The signal switching unit has the following three states (1) to (3), and operates by selecting one of these states. The three states of the signal switching unit are switched by switching the connection destination of the switch 1 and the switch 5.
(1) A first state in which the phase of the reference signal and the signal under measurement is changed by 0 ° and the reference signal and the signal under measurement are output.
(2) a second state in which only the phase of either the reference signal or the signal under measurement is changed by 90 ° and the reference signal and the signal under measurement are output;
(3) A third state in which the passage of the reference signal is blocked and only the signal under measurement is output.
 本実施の形態においては、信号処理回路10が、信号切替部が第1の状態及び第2の状態のときにA/D変換器9から出力される2つのディジタル信号を用いて、基準信号と被測定信号の位相差を算出し、信号切替部が第3の状態のときにA/D変換器9から出力される1つのディジタル信号を用いて、被測定信号の振幅を算出する。信号処理回路10の動作については、後述する。 In the present embodiment, the signal processing circuit 10 uses the two digital signals output from the A / D converter 9 when the signal switching unit is in the first state and the second state, The phase difference of the signal under measurement is calculated, and the amplitude of the signal under measurement is calculated using one digital signal output from the A / D converter 9 when the signal switching unit is in the third state. The operation of the signal processing circuit 10 will be described later.
 ここで、実施の形態1に係る位相振幅検波回路のハードウェア構成について説明する。位相振幅検波回路における入力部は入力端子11,12であり、出力部は出力端子13である。スイッチ1,5は、FETまたはPINダイオードなどのスイッチング素子から構成される。伝送線路2,3は、例えば、同軸線路、ストリップ線路、マイクロストリップ線路、コプレーナー線路などから構成される。ミクサ7は、FETまたはショットキーダイオードなどの非線形素子から構成される。LPF8は、抵抗、コンデンサ、インダクタなどを組み合わせて構成される。A/D変換器9、および、信号処理回路10の各機能は、処理回路により実現される。すなわち、位相振幅検波回路は、信号のA/D変換を行い、種々の演算を行うための処理回路を備える。処理回路は、専用のハードウェアであっても、メモリに格納されるプログラムを実行するCPU(Central Processing Unit、中央処理装置、処理装置、演算装置、マイクロプロセッサ、マイクロコンピュータ、プロセッサー、DSPともいう)であってもよい。 Here, the hardware configuration of the phase amplitude detection circuit according to the first embodiment will be described. In the phase / amplitude detection circuit, the input units are the input terminals 11 and 12, and the output unit is the output terminal 13. The switches 1 and 5 are composed of switching elements such as FETs or PIN diodes. The transmission lines 2 and 3 are composed of, for example, a coaxial line, a strip line, a microstrip line, a coplanar line, and the like. The mixer 7 is composed of a non-linear element such as an FET or a Schottky diode. The LPF 8 is configured by combining a resistor, a capacitor, an inductor, and the like. Each function of the A / D converter 9 and the signal processing circuit 10 is realized by a processing circuit. That is, the phase amplitude detection circuit includes a processing circuit for performing A / D conversion of signals and performing various calculations. Even if the processing circuit is dedicated hardware, a CPU that executes a program stored in a memory (Central Processing Unit, central processing unit, processing unit, arithmetic unit, microprocessor, microcomputer, processor, DSP) It may be.
 処理回路が専用のハードウェアである場合、処理回路は、例えば、単一回路、複合回路、プログラム化したプロセッサー、並列プログラム化したプロセッサー、ASIC、FPGA、またはこれらを組み合わせたものが該当する。A/D変換器9、および、信号処理回路10の各部の機能それぞれを処理回路で実現してもよいし、各部の機能をまとめて処理回路で実現してもよい。 When the processing circuit is dedicated hardware, the processing circuit is, for example, a single circuit, a composite circuit, a programmed processor, a parallel programmed processor, an ASIC, an FPGA, or a combination thereof. The functions of each part of the A / D converter 9 and the signal processing circuit 10 may be realized by a processing circuit, or the functions of each part may be collectively realized by a processing circuit.
 処理回路がCPUの場合、A/D変換器9、および、信号処理回路10の各機能は、ソフトウェア、ファームウェア、またはソフトウェアとファームウェアとの組み合わせにより実現される。ソフトウェアやファームウェアはプログラムとして記述され、メモリに格納される。処理回路は、メモリに記憶されたプログラムを読み出して実行することにより、各部の機能を実現する。すなわち、信号のA/D変換を行うステップ、種々の信号処理を行うステップが、結果的に実行されることになるプログラムを格納するためのメモリを備える。また、これらのプログラムは、A/D変換器9、および、信号処理回路10の手順や方法をコンピュータに実行させるものであるともいえる。ここで、メモリとは、例えば、RAM、ROM、フラッシュメモリー、EPROM、EEPROM等の、不揮発性または揮発性の半導体メモリや、磁気ディスク、フレキシブルディスク、光ディスク、コンパクトディスク、ミニディスク、DVD等が該当する。 When the processing circuit is a CPU, each function of the A / D converter 9 and the signal processing circuit 10 is realized by software, firmware, or a combination of software and firmware. Software and firmware are described as programs and stored in a memory. The processing circuit reads out and executes the program stored in the memory, thereby realizing the function of each unit. That is, a step for performing A / D conversion of a signal and a step for performing various signal processing include a memory for storing a program to be executed as a result. These programs can also be said to cause a computer to execute the procedures and methods of the A / D converter 9 and the signal processing circuit 10. Here, the memory corresponds to, for example, a nonvolatile or volatile semiconductor memory such as RAM, ROM, flash memory, EPROM, or EEPROM, a magnetic disk, a flexible disk, an optical disk, a compact disk, a mini disk, a DVD, or the like. To do.
 なお、A/D変換器9、および、信号処理回路10の各機能について、一部を専用のハードウェアで実現し、一部をソフトウェアまたはファームウェアで実現するようにしてもよい。例えば、A/D変換器9については、専用のハードウェアとしての処理回路でその機能を実現し、信号処理回路10については、処理回路がメモリに格納されたプログラムを読み出して実行することによってその機能を実現するようにしてもよい。 Note that a part of the functions of the A / D converter 9 and the signal processing circuit 10 may be realized by dedicated hardware, and a part may be realized by software or firmware. For example, the function of the A / D converter 9 is realized by a processing circuit as dedicated hardware, and the processing circuit of the signal processing circuit 10 is read by the processing circuit stored in the memory and executed. You may make it implement | achieve a function.
 このように、処理回路は、ハードウェア、ソフトウェア、ファームウェア、またはこれらの組み合わせによって、上述の各機能を実現することができる。 As described above, the processing circuit can realize the above functions by hardware, software, firmware, or a combination thereof.
 次に、図1に示す位相振幅検波回路の動作を説明する。 Next, the operation of the phase amplitude detection circuit shown in FIG. 1 will be described.
 まずはじめに、位相振幅検波回路の被測定信号の位相を算出するための動作について説明する。ここでは、被測定信号の位相として、基準信号に対する被測定信号の相対位相θ、すなわち、基準信号と被測定信号との位相差を算出する。 First, the operation for calculating the phase of the signal under measurement of the phase amplitude detection circuit will be described. Here, the relative phase θ of the signal under measurement with respect to the reference signal, that is, the phase difference between the reference signal and the signal under measurement is calculated as the phase of the signal under measurement.
 外部から入力端子11に入力された基準信号は、スイッチ1の入力端子14に入力され、スイッチ1の接続先の状態に応じて、出力端子15,16,17のいずれか1つから出力される。 A reference signal input from the outside to the input terminal 11 is input to the input terminal 14 of the switch 1 and is output from any one of the output terminals 15, 16, and 17 according to the state of the connection destination of the switch 1. .
 スイッチ1の接続先を出力端子15に選択した場合、スイッチ5の接続先は入力端子18に切り替わる。この状態が、上述した第1の状態である。このとき、スイッチ1の入力端子14に入力された基準信号はスイッチ1の出力端子15から出力され、伝送線路2を介して、スイッチ5の入力端子18に入力される。スイッチ5の入力端子18に入力された基準信号は、スイッチ5の出力端子21から出力され、ミクサ7に入力される。 When the connection destination of the switch 1 is selected as the output terminal 15, the connection destination of the switch 5 is switched to the input terminal 18. This state is the first state described above. At this time, the reference signal input to the input terminal 14 of the switch 1 is output from the output terminal 15 of the switch 1 and input to the input terminal 18 of the switch 5 through the transmission line 2. The reference signal input to the input terminal 18 of the switch 5 is output from the output terminal 21 of the switch 5 and input to the mixer 7.
 また、入力端子12に入力された被測定信号が、ミクサ7に入力される。ミクサ7は、出力端子21から入力された基準信号と、入力端子12から入力された被測定信号とを混合する。こうして、ミクサ7において、被測定信号と基準信号との和周波数成分、差周波数成分、および、高次の混合波成分を含む混合波が生成され、当該混合波はLPF8に入力される。LPF8は、これらの混合波の複数の成分のうち、差周波数成分である直流成分のみを出力し、他の成分の通過を遮断する。直流成分の電圧値には、被測定信号と基準信号との位相差の情報が含まれている。 In addition, the signal under measurement input to the input terminal 12 is input to the mixer 7. The mixer 7 mixes the reference signal input from the output terminal 21 and the signal under measurement input from the input terminal 12. Thus, the mixer 7 generates a mixed wave including a sum frequency component, a difference frequency component, and a higher-order mixed wave component of the signal under measurement and the reference signal, and the mixed wave is input to the LPF 8. The LPF 8 outputs only the DC component that is the difference frequency component among the plurality of components of these mixed waves, and blocks the passage of other components. The voltage value of the DC component includes information on the phase difference between the signal under measurement and the reference signal.
 LPF8から出力された直流成分はA/D変換器9に入力される。A/D変換器9は、直流成分の電圧値を量子化し、ディジタル信号へ変換する。A/D変換器9から出力されたディジタル信号は、信号処理回路10に入力される。信号処理回路10は、当該ディジタル信号を、図示しないメモリに記憶する。 The DC component output from the LPF 8 is input to the A / D converter 9. The A / D converter 9 quantizes the DC component voltage value and converts it into a digital signal. The digital signal output from the A / D converter 9 is input to the signal processing circuit 10. The signal processing circuit 10 stores the digital signal in a memory (not shown).
 一方、スイッチ1の接続先を出力端子16に選択した場合は、スイッチ5の接続先は入力端子19に切り替わる。この状態が、上述した第2の状態である。このとき、スイッチ1の入力端子14に入力された基準信号は、スイッチ1の出力端子16から出力され、伝送線路3を介して、スイッチ5の入力端子19に入力される。このとき、伝送線路3により、基準信号の位相は、90°移相されている。こうして、入力端子19に入力された基準信号は、スイッチ5の出力端子21から出力され、ミクサ7に入力される。 On the other hand, when the connection destination of the switch 1 is selected as the output terminal 16, the connection destination of the switch 5 is switched to the input terminal 19. This state is the second state described above. At this time, the reference signal input to the input terminal 14 of the switch 1 is output from the output terminal 16 of the switch 1 and input to the input terminal 19 of the switch 5 via the transmission line 3. At this time, the phase of the reference signal is shifted by 90 ° by the transmission line 3. Thus, the reference signal input to the input terminal 19 is output from the output terminal 21 of the switch 5 and input to the mixer 7.
 これ以降の動作は、スイッチ1の接続先を出力端子15に選択した場合と同様である。すなわち、ミクサ7で基準信号と被測定信号とが混合されて生成された混合波のうち、直流成分の電圧値がA/D変換器9で量子化され、信号処理回路10に入力され、メモリに記憶される。ここで得られる直流成分の電圧値には、基準信号と被測定信号との位相差の情報が含まれる。 The subsequent operation is the same as when the connection destination of the switch 1 is selected as the output terminal 15. That is, of the mixed wave generated by mixing the reference signal and the signal under measurement by the mixer 7, the DC component voltage value is quantized by the A / D converter 9 and input to the signal processing circuit 10. Is remembered. The voltage value of the DC component obtained here includes information on the phase difference between the reference signal and the signal under measurement.
 このとき、スイッチ1の接続先を出力端子15に選択した場合のメモリに記憶されたディジタル信号を、I成分とする。また、スイッチ1の接続先を出力端子16に選択した場合のメモリに記憶されたディジタル信号を、Q成分とする。信号処理回路10は、メモリに記憶されたI成分及びQ成分に基づいて、基準信号に対する被測定信号の相対位相を算出する。以下に、当該算出の方法について説明する。I成分の電圧をVI、Q成分の電圧をVQ、基準信号に対する被測定信号の相対位相をθとすると、θは、下式(1)で求めることができる。従って、信号処理回路10は、下式(1)を用いて、基準信号に対する被測定信号の相対位相θを算出する。 At this time, the digital signal stored in the memory when the connection destination of the switch 1 is selected as the output terminal 15 is defined as an I component. The digital signal stored in the memory when the connection destination of the switch 1 is selected as the output terminal 16 is defined as the Q component. The signal processing circuit 10 calculates the relative phase of the signal under measurement with respect to the reference signal based on the I component and the Q component stored in the memory. The calculation method will be described below. When the voltage of the I component is VI, the voltage of the Q component is VQ, and the relative phase of the signal under measurement with respect to the reference signal is θ, θ can be obtained by the following equation (1). Therefore, the signal processing circuit 10 calculates the relative phase θ of the signal under measurement with respect to the reference signal using the following equation (1).
  θ=arctan(VQ/VI) ・・・(1) Θ = arctan (VQ / VI) (1)
 信号処理回路10は、こうして得られた相対位相θを、被測定信号の位相データとしてメモリに記憶する。 The signal processing circuit 10 stores the relative phase θ thus obtained in the memory as phase data of the signal under measurement.
 次に、位相振幅検波回路の被測定信号の振幅を算出するための動作について説明する。スイッチ1の接続先を出力端子17に選択する。この場合、スイッチ5の接続先は、入力端子20に切り替わる。この状態が、上述した第3の状態である。 Next, the operation for calculating the amplitude of the signal under measurement of the phase amplitude detection circuit will be described. The connection destination of the switch 1 is selected as the output terminal 17. In this case, the connection destination of the switch 5 is switched to the input terminal 20. This state is the third state described above.
 従って、入力端子11に入力された基準信号は、スイッチ1の出力端子17から出力され、終端器4に入力される。終端器4は、当該基準信号を終端させる。そのため、当該基準信号は、ミクサ7には入力されない。 Therefore, the reference signal input to the input terminal 11 is output from the output terminal 17 of the switch 1 and input to the terminator 4. The terminator 4 terminates the reference signal. For this reason, the reference signal is not input to the mixer 7.
 ミクサ7には、被測定信号のみが入力される。入力端子12からミクサ7に入力された被測定信号は、ミクサ7により検波され、被測定信号の振幅に対応する直流成分が出力される。つまり、このとき、ミクサ7が検波器として機能する。 Only the signal under measurement is input to the mixer 7. The signal under measurement input from the input terminal 12 to the mixer 7 is detected by the mixer 7 and a DC component corresponding to the amplitude of the signal under measurement is output. That is, at this time, the mixer 7 functions as a detector.
 ミクサ7からは、上記直流成分の他に、被測定信号の漏洩成分、被測定信号の高調波成分が出力される。 The mixer 7 outputs a leakage component of the signal under measurement and a harmonic component of the signal under measurement in addition to the DC component.
 LPF8は、ミクサ7から出力される複数の成分のうち、直流成分のみを通過させ、他の成分の通過を遮断する。直流成分の電圧には、被測定信号の振幅の情報が含まれる。 The LPF 8 passes only the DC component among the plurality of components output from the mixer 7 and blocks the passage of other components. The DC component voltage includes information on the amplitude of the signal under measurement.
 LPF8から出力される直流成分の電圧はA/D変換器9で量子化され、ディジタル信号に変換される。当該ディジタル信号は、信号処理回路10に入力される。信号処理回路10は、当該ディジタル信号を被測定信号の振幅データとしてメモリに記憶する。 The voltage of the DC component output from the LPF 8 is quantized by the A / D converter 9 and converted into a digital signal. The digital signal is input to the signal processing circuit 10. The signal processing circuit 10 stores the digital signal in the memory as amplitude data of the signal under measurement.
 以上のように、本実施の形態に係る位相振幅検波回路においては、スイッチ1の接続先およびスイッチ5の接続先を順次切り替えて、I成分、Q成分、振幅の3つのデータを順に取得し、それらのデータを用いて信号処理回路10で演算を行うことにより、基準信号と被測定信号との位相差と被測定信号の振幅とを検出することができる。このように、本実施の形態1においては、単に、スイッチ1,5の接続先を切り替えるだけで、基準信号と被測定信号との位相差と被測定信号の振幅とを同一の回路で検出することができる。 As described above, in the phase / amplitude detection circuit according to the present embodiment, the connection destination of the switch 1 and the connection destination of the switch 5 are sequentially switched, and the three data of the I component, the Q component, and the amplitude are sequentially acquired. By calculating the signal processing circuit 10 using these data, the phase difference between the reference signal and the signal under measurement and the amplitude of the signal under measurement can be detected. As described above, in the first embodiment, the phase difference between the reference signal and the signal under measurement and the amplitude of the signal under measurement are detected by the same circuit simply by switching the connection destination of the switches 1 and 5. be able to.
 以下、本実施の形態1に係る位相振幅検波回路の変形例について、図2及び図3を用いて説明する。 Hereinafter, modifications of the phase amplitude detection circuit according to the first embodiment will be described with reference to FIGS.
 図1では、伝送線路2と伝送線路3とを用いて90°の位相差を有する回路を構成することについて示したが、図2に示すように、伝送線路2及び伝送線路3の代わりに、90°,3dBカップラ22を用いても同等の効果が得られる。なお、図2において、図1と同じ構成要素については、図1と同じ符号を付して示し、ここでは、その説明を省略する。 In FIG. 1, although it showed about comprising the circuit which has a phase difference of 90 degrees using the transmission line 2 and the transmission line 3, as shown in FIG. 2, instead of the transmission line 2 and the transmission line 3, Even if the 90 °, 3 dB coupler 22 is used, the same effect can be obtained. 2, the same components as those in FIG. 1 are denoted by the same reference numerals as those in FIG. 1, and description thereof is omitted here.
 90°,3dBカップラ22は、出力端子15から入力された基準信号の位相を0°移相して、「0°」と書かれた端子から出力する。また、90°,3dBカップラ22は、出力端子16から入力された基準信号の位相を90°移相して、「0°」と書かれた端子から出力する。いずれの場合も「0°」と書かれた端子から出力する。 The 90 °, 3 dB coupler 22 shifts the phase of the reference signal input from the output terminal 15 by 0 °, and outputs it from the terminal written “0 °”. In addition, the 90 °, 3 dB coupler 22 shifts the phase of the reference signal input from the output terminal 16 by 90 °, and outputs it from the terminal written “0 °”. In either case, the signal is output from the terminal where “0 °” is written.
 図2においては、図1のスイッチ5の代わりに、スイッチ23が設けられている。スイッチ23は、2つの入力端子25,26と、1つの出力端子27とを有している。出力端子27は、ミクサ7に接続されている。スイッチ23は、入力端子25に入力される基準信号を、出力端子27に出力する。終端器6は、入力端子26に入力される信号を終端し、スイッチ23の出力端子27への出力を遮断する。また、90°,3dBカップラ22の「90°」と書かれた端子は、終端器24により終端されている。 In FIG. 2, a switch 23 is provided instead of the switch 5 of FIG. The switch 23 has two input terminals 25 and 26 and one output terminal 27. The output terminal 27 is connected to the mixer 7. The switch 23 outputs a reference signal input to the input terminal 25 to the output terminal 27. The terminator 6 terminates the signal input to the input terminal 26 and cuts off the output to the output terminal 27 of the switch 23. Further, the terminal written as “90 °” of the 90 °, 3 dB coupler 22 is terminated by the terminator 24.
 スイッチ1の接続先が、出力端子15または出力端子16に選択されている場合は、スイッチ23の接続先が入力端子25に切り替わる。 When the connection destination of the switch 1 is selected as the output terminal 15 or the output terminal 16, the connection destination of the switch 23 is switched to the input terminal 25.
 スイッチ1の接続先が出力端子15に選択された場合は、基準信号が、出力端子15から出力され、90°,3dBカップラ22に入力される。90°,3dBカップラ22は、基準信号の位相を0°移相させ、スイッチ23の入力端子25に入力する。この状態が、上記の第1の状態である。 When the connection destination of the switch 1 is selected to the output terminal 15, the reference signal is output from the output terminal 15 and input to the 90 °, 3 dB coupler 22. The 90 °, 3 dB coupler 22 shifts the phase of the reference signal by 0 ° and inputs it to the input terminal 25 of the switch 23. This state is the first state described above.
 一方、スイッチ1の接続先が出力端子16に選択された場合は、基準信号が、出力端子16から出力され、90°,3dBカップラ22に入力される。90°,3dBカップラ22は、基準信号の位相を90°移相させ、スイッチ23の入力端子25に入力する。この状態が、上記の第2の状態である。 On the other hand, when the connection destination of the switch 1 is selected as the output terminal 16, the reference signal is output from the output terminal 16 and input to the 90 °, 3 dB coupler 22. The 90 °, 3 dB coupler 22 shifts the phase of the reference signal by 90 ° and inputs it to the input terminal 25 of the switch 23. This state is the second state described above.
 なお、図2において、スイッチ1の接続先が出力端子17の場合は、図1と同様に、終端器4により基準信号は終端される。この状態が、上記の第3の状態である。 In FIG. 2, when the connection destination of the switch 1 is the output terminal 17, the reference signal is terminated by the terminator 4 as in FIG. This state is the third state described above.
 90°,3dBカップラ22は、スイッチ1の接続先の状態に応じて、上記のように動作するため、図1に示した伝送線路2および伝送線路3の組合せと同等の動作を行う。その結果、図2の位相振幅検波回路は、図1の位相振幅検波回路と同等の動作を行う。 The 90 °, 3 dB coupler 22 operates as described above according to the state of the connection destination of the switch 1, and therefore performs the same operation as the combination of the transmission line 2 and the transmission line 3 shown in FIG. As a result, the phase amplitude detection circuit in FIG. 2 performs the same operation as the phase amplitude detection circuit in FIG.
 さらに、図3に示すように、図1の伝送線路2,3の代わりに、移相器57を用いて、90°の位相差をもたせるようにしてもよい。なお、図3において、図1と同じ構成要素については、図1と同じ符号を付して示し、ここでは、その説明を省略する。 Further, as shown in FIG. 3, a phase shifter 57 may be used instead of the transmission lines 2 and 3 of FIG. In FIG. 3, the same components as those in FIG. 1 are denoted by the same reference numerals as those in FIG. 1, and description thereof is omitted here.
 図3に示すように、移相器57は、スイッチ1の出力端子15とスイッチ5の入力端子18との間に接続されている。移相器57は、スイッチ1の接続先が出力端子15を選択された場合に、外部から入力される制御信号に応じて、出力端子15から入力される基準信号の位相を0°移相させて出力するか、あるいは、基準信号の位相を90°移相させて出力する。 As shown in FIG. 3, the phase shifter 57 is connected between the output terminal 15 of the switch 1 and the input terminal 18 of the switch 5. When the output terminal 15 is selected as the connection destination of the switch 1, the phase shifter 57 shifts the phase of the reference signal input from the output terminal 15 by 0 ° according to the control signal input from the outside. Or the phase of the reference signal is shifted by 90 ° and output.
 移相器57は、スイッチ1の接続先の状態および外部からの制御信号に応じて、上記のように動作するため、図1に示した伝送線路2および伝送線路3の組合せと同等の動作を行う。その結果、図3の位相振幅検波回路は、図1の位相振幅検波回路と同等の動作を行う。 Since the phase shifter 57 operates as described above in accordance with the state of the connection destination of the switch 1 and the control signal from the outside, the operation equivalent to the combination of the transmission line 2 and the transmission line 3 shown in FIG. Do. As a result, the phase amplitude detection circuit of FIG. 3 performs the same operation as the phase amplitude detection circuit of FIG.
 なお、図3の構成の場合、図1に示したスイッチ1の出力端子16とスイッチ5の入力端子19とが不要となる。従って、スイッチ1およびスイッチ5の端子をそれぞれ1つずつ少なくすることができるため、スイッチ1,5が小型になるという効果が得られる。 In the case of the configuration shown in FIG. 3, the output terminal 16 of the switch 1 and the input terminal 19 of the switch 5 shown in FIG. Accordingly, since the terminals of the switch 1 and the switch 5 can be reduced by one each, the effect that the switches 1 and 5 are reduced in size can be obtained.
 なお、図3において、スイッチ1の接続先が出力端子17の場合は、図1と同様に、終端器4により基準信号は終端される。 In FIG. 3, when the connection destination of the switch 1 is the output terminal 17, the reference signal is terminated by the terminator 4 as in FIG.
 図2及び図3の他の構成および他の動作は、図1と同じであるため、ここでは、その説明を省略する。 2 and FIG. 3 are the same as those in FIG. 1, and thus the description thereof is omitted here.
 以上のように、本実施の形態1の位相振幅検波回路においては、基準信号の位相を0°移相させて出力する、基準信号の位相を90°移相させて出力する、基準信号を終端させるという3つの動作を、順次、スイッチ1,5で切り替えることで、I成分、Q成分、振幅の3つのデータを取得する。そうして、それらのデータを用いて信号処理回路10で演算を行うことにより、基準信号に対する被測定信号の相対位相θと被測定信号の振幅とを検出することができる。このように、本実施の形態1においては、スイッチ1,5の接続先を単に切り替えることにより、基準信号に対する被測定信号の相対位相θと被測定信号の振幅とを、同一の回路で検出することができる。その結果、位相振幅検波回路の回路規模を小さくすることができる。そのため、本実施の形態1の位相振幅検波回路を送信モジュール及びアレーアンテナに搭載した場合、被測定信号である送信信号の相対位相と振幅とを送信モジュールごとに検出して、簡易な構成で送信信号の位相と振幅とを校正することが可能になる。また、本実施の形態1の位相振幅検波回路をアレーアンテナに適用した場合、特許文献1に記載のように2つの送信モジュールをケーブルで接続する必要もなく、1つの送信モジュールで、信号の位相と振幅とが検出可能であるため、アレーアンテナ内での送信モジュールの設置における自由度を確保することができる。 As described above, in the phase amplitude detection circuit of the first embodiment, the phase of the reference signal is output by shifting the phase by 0 °, the phase of the reference signal is output by shifting the phase by 90 °, and the reference signal is terminated. By sequentially switching the three operations to be performed by the switches 1 and 5, three data of the I component, the Q component, and the amplitude are acquired. Then, by performing calculations in the signal processing circuit 10 using those data, the relative phase θ of the signal under measurement with respect to the reference signal and the amplitude of the signal under measurement can be detected. Thus, in the first embodiment, the relative phase θ of the signal under measurement with respect to the reference signal and the amplitude of the signal under measurement are detected by the same circuit by simply switching the connection destination of the switches 1 and 5. be able to. As a result, the circuit scale of the phase amplitude detection circuit can be reduced. Therefore, when the phase / amplitude detection circuit according to the first embodiment is mounted on the transmission module and the array antenna, the relative phase and amplitude of the transmission signal, which is the signal under measurement, are detected for each transmission module and transmitted with a simple configuration. It becomes possible to calibrate the phase and amplitude of the signal. In addition, when the phase / amplitude detection circuit according to the first embodiment is applied to an array antenna, there is no need to connect two transmission modules with a cable as described in Patent Document 1, and the phase of a signal can be obtained with one transmission module. Therefore, the degree of freedom in installing the transmission module in the array antenna can be ensured.
 実施の形態2.
 図4は、この発明の実施の形態2に係る位相振幅検波回路の構成図である。上記の実施の形態1では、第1の状態と第2の状態とにおいて基準信号に90°の位相差を持たせたが、本実施の形態においては、第1の状態と第2の状態とにおいて被測定信号に90°の位相差を持たせる。
Embodiment 2. FIG.
FIG. 4 is a configuration diagram of a phase amplitude detection circuit according to the second embodiment of the present invention. In the first embodiment described above, the reference signal has a phase difference of 90 ° in the first state and the second state. However, in the present embodiment, the first state and the second state The signal under measurement has a phase difference of 90 °.
 図4に示すように、実施の形態2に係る位相振幅検波回路は、スイッチ28、終端器4、スイッチ29、伝送線路30、伝送線路31、スイッチ32、ミクサ7、LPF(Low Pass Filter)8、A/D変換器9、信号処理回路10とから構成される。 As shown in FIG. 4, the phase / amplitude detection circuit according to the second embodiment includes a switch 28, a terminator 4, a switch 29, a transmission line 30, a transmission line 31, a switch 32, a mixer 7, an LPF (Low Pass Filter) 8. , An A / D converter 9 and a signal processing circuit 10.
 また、説明の便宜上、図4に示すように、各端子に番号を割り振る。すなわち、基準信号の入力端子を11、被測定信号の入力端子を12、信号処理回路10の出力端子を13、スイッチ28の入力端子を33、スイッチ28の2つの出力端子をそれぞれ34,35、スイッチ29の入力端子を36、スイッチ29の2つの出力端子をそれぞれ37,38、スイッチ32の2つの入力端子をそれぞれ39,40、スイッチ32の出力端子を41とする。 Also, for convenience of explanation, numbers are assigned to each terminal as shown in FIG. That is, the reference signal input terminal 11, the signal under test input terminal 12, the signal processing circuit 10 output terminal 13, the switch 28 input terminal 33, and the switch 28 two output terminals 34 and 35, respectively. The input terminal of the switch 29 is 36, the two output terminals of the switch 29 are 37 and 38, the two input terminals of the switch 32 are 39 and 40, respectively, and the output terminal of the switch 32 is 41.
 以下、図1に示す実施の形態1の構成と同一の部分については、同一符号を付して示し、ここでは、その説明は省略する。 Hereinafter, the same parts as those of the first embodiment shown in FIG. 1 are denoted by the same reference numerals, and description thereof is omitted here.
 スイッチ28は、1つの入力端子33と、2つの出力端子34,35を有している。入力端子33には入力端子11が接続され、入力端子11から基準信号が入力される。スイッチ28は、入力端子33に入力される基準信号を、出力端子34,35のいずれかに出力する。出力端子34は、ミクサ7に接続されている。出力端子35は、終端器4に接続されている。 The switch 28 has one input terminal 33 and two output terminals 34 and 35. The input terminal 11 is connected to the input terminal 33, and a reference signal is input from the input terminal 11. The switch 28 outputs the reference signal input to the input terminal 33 to one of the output terminals 34 and 35. The output terminal 34 is connected to the mixer 7. The output terminal 35 is connected to the terminator 4.
 スイッチ29は、1つの入力端子36と、2つの出力端子37,38とを有している。入力端子36には入力端子12が接続され、入力端子12から被測定信号が入力される。スイッチ29は、入力端子36に入力される被測定信号を、出力端子37,38のいずれかに出力する。出力端子37は、伝送線路30に接続されている。出力端子38は、伝送線路31に接続されている。 The switch 29 has one input terminal 36 and two output terminals 37 and 38. The input terminal 12 is connected to the input terminal 36, and a signal under measurement is input from the input terminal 12. The switch 29 outputs the signal under measurement input to the input terminal 36 to one of the output terminals 37 and 38. The output terminal 37 is connected to the transmission line 30. The output terminal 38 is connected to the transmission line 31.
 伝送線路30は、スイッチ29の出力端子37とスイッチ32の入力端子39との間に接続されている。伝送線路30は、スイッチ29の出力端子37から入力される被測定信号の位相を0°移相させて、スイッチ32の入力端子39に出力する。 The transmission line 30 is connected between the output terminal 37 of the switch 29 and the input terminal 39 of the switch 32. The transmission line 30 shifts the phase of the signal under measurement input from the output terminal 37 of the switch 29 by 0 ° and outputs it to the input terminal 39 of the switch 32.
 伝送線路31は、スイッチ29の出力端子38とスイッチ32の入力端子40との間に接続されている。伝送線路30と伝送線路31とは電気長が90°異なるように構成されている。伝送線路31は、スイッチ29の出力端子38から入力される被測定信号の位相を90°移相させて、スイッチ32の入力端子40に出力する。 The transmission line 31 is connected between the output terminal 38 of the switch 29 and the input terminal 40 of the switch 32. The transmission line 30 and the transmission line 31 are configured so that the electrical length differs by 90 °. The transmission line 31 shifts the phase of the signal under measurement input from the output terminal 38 of the switch 29 by 90 ° and outputs it to the input terminal 40 of the switch 32.
 スイッチ32は、2つの入力端子39,40と、1つの出力端子41とを有している。スイッチ32は、入力端子39,40のいずれか1つに入力された被測定信号を、出力端子41からミクサ7に出力する。 The switch 32 has two input terminals 39 and 40 and one output terminal 41. The switch 32 outputs the signal under measurement input to any one of the input terminals 39 and 40 from the output terminal 41 to the mixer 7.
 図4における他の構成要素については、図1と同じであるため、ここでは、説明を省略する。また、図4における位相振幅検波回路のハードウェア構成については、実施の形態1の位相振幅検波回路と同様で良いため、ここでは、説明を省略する。 The other components in FIG. 4 are the same as those in FIG. 1, and thus description thereof is omitted here. The hardware configuration of the phase / amplitude detection circuit in FIG. 4 may be the same as that of the phase / amplitude detection circuit according to the first embodiment, and thus the description thereof is omitted here.
 ここで、図4においては、スイッチ28,29,32、伝送線路30,31、及び、終端器4が、上記の第1の状態、上記の第2の状態、および、上記の第3の状態のうちのいずれか1つの状態を選択して動作する信号切替部を構成している。 Here, in FIG. 4, the switches 28, 29, 32, the transmission lines 30, 31, and the terminator 4 are in the first state, the second state, and the third state. A signal switching unit that operates by selecting one of the states is configured.
 次に、図4に示す位相振幅検波回路の動作について説明する。 Next, the operation of the phase amplitude detection circuit shown in FIG. 4 will be described.
 まずはじめに、被測定信号の位相を算出するための動作について説明する。ここでは、被測定信号の位相として、基準信号に対する被測定信号の相対位相θ、すなわち、基準信号と被測定信号との位相差を求める。 First, the operation for calculating the phase of the signal under measurement will be described. Here, as the phase of the signal under measurement, the relative phase θ of the signal under measurement with respect to the reference signal, that is, the phase difference between the reference signal and the signal under measurement is obtained.
 まず、上記の第1の状態の場合について説明する。スイッチ28の接続先は、出力端子34に選択される。入力端子11に入力された基準信号は、スイッチ28の入力端子33に入力され、スイッチ28の出力端子34からミクサ7に出力される。 First, the case of the first state will be described. The connection destination of the switch 28 is selected as the output terminal 34. The reference signal input to the input terminal 11 is input to the input terminal 33 of the switch 28 and output from the output terminal 34 of the switch 28 to the mixer 7.
 一方、スイッチ29の接続先は、出力端子37に選択される。 On the other hand, the connection destination of the switch 29 is selected to the output terminal 37.
 ここで、スイッチ29の接続先が、出力端子37に選択されると、スイッチ32の接続先は、入力端子39に選択される。 Here, when the connection destination of the switch 29 is selected as the output terminal 37, the connection destination of the switch 32 is selected as the input terminal 39.
 そのため、入力端子36に入力された被測定信号は、スイッチ29の出力端子37から出力され、伝送線路30を介して、スイッチ32の入力端子39に入力される。その後、被測定信号は、スイッチ32の出力端子41から出力され、ミクサ7に入力される。 Therefore, the signal under measurement input to the input terminal 36 is output from the output terminal 37 of the switch 29 and input to the input terminal 39 of the switch 32 via the transmission line 30. Thereafter, the signal under measurement is output from the output terminal 41 of the switch 32 and input to the mixer 7.
 これ以降の動作は、実施の形態1と同様である。すなわち、ミクサ7で基準信号と被測定信号とが混合され、その結果出力される混合波に含まれる直流成分の電圧がA/D変換器9で量子化され、信号処理回路10に入力され、メモリに記憶される。ここで得られる直流成分の電圧(I成分)には、基準信号と被測定信号との信号の位相差の情報が含まれる。 The subsequent operations are the same as those in the first embodiment. That is, the reference signal and the signal under measurement are mixed by the mixer 7, and the voltage of the DC component included in the mixed wave output as a result is quantized by the A / D converter 9 and input to the signal processing circuit 10. Stored in memory. The DC component voltage (I component) obtained here includes information on the phase difference between the reference signal and the signal under measurement.
 次に、上記の第2の状態の場合について説明する。スイッチ28の接続先は、出力端子34に選択される。入力端子11に入力された基準信号は、スイッチ28の入力端子33に入力され、スイッチ28の出力端子34からミクサ7に出力される。 Next, the case of the second state will be described. The connection destination of the switch 28 is selected as the output terminal 34. The reference signal input to the input terminal 11 is input to the input terminal 33 of the switch 28 and output from the output terminal 34 of the switch 28 to the mixer 7.
 このとき、スイッチ29の接続先が、出力端子38に選択されたとすると、スイッチ32の接続先は、入力端子40に選択される。入力端子12に入力された被測定信号は、スイッチ29の入力端子36に入力され、スイッチ29の出力端子38から伝送線路31へ出力される。伝送線路31は、被測定信号の位相を90°移相して、スイッチ32の入力端子40に出力する。スイッチ32の入力端子40に入力された被測定信号は、スイッチ32の出力端子41から出力され、ミクサ7に入力される。 At this time, if the connection destination of the switch 29 is selected as the output terminal 38, the connection destination of the switch 32 is selected as the input terminal 40. The signal under measurement input to the input terminal 12 is input to the input terminal 36 of the switch 29 and output from the output terminal 38 of the switch 29 to the transmission line 31. The transmission line 31 shifts the phase of the signal under measurement by 90 ° and outputs it to the input terminal 40 of the switch 32. The signal under measurement input to the input terminal 40 of the switch 32 is output from the output terminal 41 of the switch 32 and input to the mixer 7.
 これ以降の動作は、スイッチ29の接続先を出力端子37に選択した場合と同様である。すなわち、ミクサ7で基準信号と被測定信号とが混合され、その結果出力される混合波に含まれる直流成分の電圧がA/D変換器9で量子化され、信号処理回路10に入力され、メモリに記憶される。ここで得られる直流成分の電圧(Q成分)には、基準信号と被測定信号との位相差の情報が含まれる。 The subsequent operation is the same as when the connection destination of the switch 29 is selected as the output terminal 37. That is, the reference signal and the signal under measurement are mixed by the mixer 7, and the voltage of the DC component included in the mixed wave output as a result is quantized by the A / D converter 9 and input to the signal processing circuit 10. Stored in memory. The DC component voltage (Q component) obtained here includes information on the phase difference between the reference signal and the signal under measurement.
 そして、信号処理回路10において、I成分の電圧をVI、Q成分の電圧をVQ、基準信号に対する被測定信号の相対位相をθとして、θを、上述した式(1)で求める。 Then, in the signal processing circuit 10, θ is obtained by the above-described equation (1), where I is the voltage of I component, VQ is the voltage of Q component, V is the relative phase of the signal under measurement with respect to the reference signal,
 次に、被測定信号の振幅を算出するための動作について説明する。スイッチ28の接続先を、出力端子35に選択する。このとき、スイッチ28の入力端子33に入力された基準信号は、出力端子35から終端器4に入力され、ミクサ7には入力されない。この状態が、上記の第3の状態である。 Next, the operation for calculating the amplitude of the signal under measurement will be described. The connection destination of the switch 28 is selected as the output terminal 35. At this time, the reference signal input to the input terminal 33 of the switch 28 is input from the output terminal 35 to the terminator 4 and not input to the mixer 7. This state is the third state described above.
 スイッチ29の接続先は、出力端子37,38のいずれを選択しても良く、同様に、スイッチ32の接続先は、入力端子39,40のいずれを選択しても良い。但し、スイッチ29の接続先を出力端子37に選択した場合は、スイッチ32の接続先を入力端子39とし、スイッチ29の接続先を出力端子38に選択した場合は、スイッチ32の接続先を入力端子40とする。 The connection destination of the switch 29 may select any of the output terminals 37 and 38. Similarly, the connection destination of the switch 32 may select any of the input terminals 39 and 40. However, when the connection destination of the switch 29 is selected as the output terminal 37, the connection destination of the switch 32 is the input terminal 39, and when the connection destination of the switch 29 is selected as the output terminal 38, the connection destination of the switch 32 is input. Terminal 40 is used.
 これにより、ミクサ7には、被測定信号のみが入力される。ミクサ7に入力された被測定信号は、ミクサ7により検波され、被測定信号の振幅に応じた直流成分が出力される。つまり、ミクサ7が検波器として動作する。 Thus, only the signal under measurement is input to the mixer 7. The signal under measurement input to the mixer 7 is detected by the mixer 7 and a DC component corresponding to the amplitude of the signal under measurement is output. That is, the mixer 7 operates as a detector.
 ミクサ7からは、上記直流成分の他に、被測定信号の漏洩成分、被測定信号の高調波成分が出力される。 The mixer 7 outputs a leakage component of the signal under measurement and a harmonic component of the signal under measurement in addition to the DC component.
 LPF8は、上記直流成分を通過し、他の成分の通過を遮断する。LPF8から出力される直流成分の電圧はA/D変換器9で量子化され、ディジタル信号に変換される。当該ディジタル信号は、信号処理回路10に入力される。信号処理回路10は、当該ディジタル信号を被測定信号の振幅データとしてメモリに記憶する。 LPF 8 passes the direct current component and blocks the passage of other components. The DC component voltage output from the LPF 8 is quantized by the A / D converter 9 and converted into a digital signal. The digital signal is input to the signal processing circuit 10. The signal processing circuit 10 stores the digital signal in the memory as amplitude data of the signal under measurement.
 以上のように、本実施の形態においては、スイッチ28、スイッチ29、スイッチ32を順次切り替え、I成分、Q成分、振幅の3つのデータを取得し、信号処理回路10で演算を行うことにより、基準信号に対する被測定信号の相対位相θと被測定信号の振幅とを同じ回路で検出することができる効果がある。 As described above, in the present embodiment, the switch 28, the switch 29, and the switch 32 are sequentially switched to acquire three data of the I component, the Q component, and the amplitude, and the signal processing circuit 10 performs the calculation. There is an effect that the relative phase θ of the signal under measurement with respect to the reference signal and the amplitude of the signal under measurement can be detected by the same circuit.
 なお、図4では、伝送線路30と伝送線路31を用いて90°の位相差を有する回路について示したが、伝送線路30,31の代わりに、90°,3dBカップラを用いても同等の効果が得られる。90°,3dBカップラの構成及び動作については、上述の実施の形態1において図2を用いて説明した90°,3dBカップラ22と同じであるため、ここでは、その説明を省略する。 In FIG. 4, a circuit having a phase difference of 90 ° using the transmission line 30 and the transmission line 31 is shown. However, the same effect can be obtained by using a 90 °, 3 dB coupler instead of the transmission lines 30, 31. Is obtained. The configuration and operation of the 90 °, 3 dB coupler are the same as those of the 90 °, 3 dB coupler 22 described with reference to FIG. 2 in the first embodiment, and thus the description thereof is omitted here.
 また、図5に示すように、伝送線路30,31の代わりに、移相器57を用いて90°の位相差をもたせることもできる。この場合、スイッチ29およびスイッチ32を削除することができるため、位相振幅検波回路が小型になる効果がある。 Further, as shown in FIG. 5, a phase shift of 90 ° can be provided using a phase shifter 57 instead of the transmission lines 30 and 31. In this case, since the switch 29 and the switch 32 can be eliminated, there is an effect that the phase / amplitude detection circuit is reduced in size.
 なお、本実施の形態においては、スイッチ28,29,32の接続先の切り替えは、予め設定された周期で、例えば、第1の状態、第2の状態、第3の状態の順になるように、順次行われる。あるいは、外部からの制御信号に基づいてスイッチ28,29,32の接続先の切り替えを行うようにしてもよい。 In the present embodiment, the connection destinations of the switches 28, 29, and 32 are switched in a predetermined cycle, for example, in the order of the first state, the second state, and the third state. Are performed sequentially. Alternatively, the connection destinations of the switches 28, 29, and 32 may be switched based on an external control signal.
 以上のように、本実施の形態においても、上述の実施の形態1と同様に、スイッチ28,29,32の接続先を単に切り替えることにより、基準信号に対する被測定信号の相対位相θと被測定信号の振幅とを、同一の回路で検出することができる。その結果、位相振幅検波回路の回路規模を小さくすることができる。そのため、本実施の形態2の位相振幅検波回路を送信モジュール及びアレーアンテナに適用した場合、簡易な構成で、信号の位相と振幅を検出して校正することが可能になる。また、本実施の形態2の位相振幅検波回路を送信モジュール及びアレーアンテナに適用した場合、特許文献1にように2つの送信モジュールをケーブルで接続する必要もなく、1つの送信モジュールで、信号の位相と振幅とが検出可能であるため、送信モジュールの設置における自由度を確保することができる。 As described above, also in the present embodiment, as in the first embodiment, the relative phase θ of the signal under measurement with respect to the reference signal and the measurement target are simply switched by switching the connection destination of the switches 28, 29, and 32. The signal amplitude can be detected by the same circuit. As a result, the circuit scale of the phase amplitude detection circuit can be reduced. Therefore, when the phase amplitude detection circuit of the second embodiment is applied to the transmission module and the array antenna, it is possible to detect and calibrate the signal phase and amplitude with a simple configuration. Further, when the phase amplitude detection circuit of the second embodiment is applied to a transmission module and an array antenna, it is not necessary to connect two transmission modules with a cable as in Patent Document 1, and one transmission module can Since the phase and amplitude can be detected, a degree of freedom in installing the transmission module can be ensured.
 実施の形態3.
 この発明の実施の形態3では、実施の形態1あるいは実施の形態2に示した位相振幅検波回路を用いた送信モジュール及びアレーアンテナについて説明する。図6は、この発明に係る実施の形態3による送信モジュール及びアレーアンテナの構成図である。
Embodiment 3 FIG.
In the third embodiment of the present invention, a transmission module and an array antenna using the phase / amplitude detection circuit shown in the first or second embodiment will be described. FIG. 6 is a configuration diagram of a transmission module and an array antenna according to the third embodiment of the present invention.
 図6に示すように、アレーアンテナは、基準信号発生源42、同相分配器43、複数の送信モジュール44、複数の素子アンテナ45、および、制御回路46から構成される。図6においては、複数の送信モジュール44として、送信モジュール44aと送信モジュール44bとが示されている。送信モジュール44aと送信モジュール44bとは同じ構成を有している。送信モジュール44の個数は任意の個数でよい。また、図6においては、複数の素子アンテナ45として、素子アンテナ45aと素子アンテナ44bとが示されている。素子アンテナ45aは送信モジュール44aに接続され、素子アンテナ45bは送信モジュール44bに接続されている。このように、素子アンテナ45は、1つの送信モジュール44に対して、1つずつ設けられている。素子アンテナ45aと素子アンテナ45bとは同じ構成を有している。 6, the array antenna includes a reference signal generation source 42, an in-phase distributor 43, a plurality of transmission modules 44, a plurality of element antennas 45, and a control circuit 46. In FIG. 6, a transmission module 44 a and a transmission module 44 b are shown as the plurality of transmission modules 44. The transmission module 44a and the transmission module 44b have the same configuration. The number of transmission modules 44 may be an arbitrary number. In FIG. 6, an element antenna 45 a and an element antenna 44 b are shown as the plurality of element antennas 45. The element antenna 45a is connected to the transmission module 44a, and the element antenna 45b is connected to the transmission module 44b. Thus, one element antenna 45 is provided for each transmission module 44. The element antenna 45a and the element antenna 45b have the same configuration.
 なお、図6においては、複数個ずつ設けられている構成要素については、それらを区別できるように、符号の末尾に、「a」,「b」というアルファベットを付している。しかしながら、送信モジュール44aと送信モジュール44bとは同じ構成を有し、素子アンテナ45aと素子アンテナ45bとは同じ構成を有しているため、以下の説明においては、送信モジュール44aと送信モジュール44bとを区別せずに、単に「送信モジュール44」と呼び、同様に、素子アンテナ45aと素子アンテナ44bとを区別せずに、単に「素子アンテナ44」と呼ぶこととする。また、送信モジュール44内の各構成要素についても同様とする。 In addition, in FIG. 6, the alphabets “a” and “b” are added to the end of the reference numerals so as to distinguish between the components provided in plural. However, since the transmission module 44a and the transmission module 44b have the same configuration, and the element antenna 45a and the element antenna 45b have the same configuration, in the following description, the transmission module 44a and the transmission module 44b are The element antenna 45a and the element antenna 44b are simply referred to as the “element antenna 44” without being distinguished from each other. The same applies to each component in the transmission module 44.
 図6に示すように、送信モジュール44は、方向性結合器47、移相器48、可変減衰器49、増幅器50、方向性結合器51、および、位相振幅検波回路52から構成される。このように、本実施の形態においては、送信モジュール44内に、位相振幅検波回路52が搭載されている。位相振幅検波回路52は、基本的に、上述した実施の形態1及び実施の形態2で説明した図1~図5に示した位相振幅検波回路のいずれかと同じ構成及び機能を有している。但し、本実施の形態に係る位相振幅検波回路52は、さらに、移相器48に対する位相制御信号および可変減衰器49に対する振幅制御信号を生成して出力する。この点が、実施の形態1及び実施の形態2と異なる。位相振幅検波回路52の構成については、図7を用いて以下に説明する。 As shown in FIG. 6, the transmission module 44 includes a directional coupler 47, a phase shifter 48, a variable attenuator 49, an amplifier 50, a directional coupler 51, and a phase amplitude detection circuit 52. Thus, in the present embodiment, the phase amplitude detection circuit 52 is mounted in the transmission module 44. The phase amplitude detection circuit 52 basically has the same configuration and function as any of the phase amplitude detection circuits shown in FIGS. 1 to 5 described in the first and second embodiments. However, the phase amplitude detection circuit 52 according to the present embodiment further generates and outputs a phase control signal for the phase shifter 48 and an amplitude control signal for the variable attenuator 49. This point is different from the first and second embodiments. The configuration of the phase amplitude detection circuit 52 will be described below with reference to FIG.
 位相振幅検波回路52の構成例を図7に示す。位相振幅検波回路52の構成は、図1に示した位相振幅検波回路の構成とほぼ同一であるが、図7においては、図1の信号処理回路10の代わりに、信号処理回路56が設けられている。信号処理回路56と信号処理回路10との違いは、信号処理回路56が、移相器48に対する位相制御信号および可変減衰器49に対する振幅制御信号を生成して出力する点である。 A configuration example of the phase amplitude detection circuit 52 is shown in FIG. The configuration of the phase / amplitude detection circuit 52 is almost the same as the configuration of the phase / amplitude detection circuit shown in FIG. 1, but in FIG. 7, a signal processing circuit 56 is provided instead of the signal processing circuit 10 of FIG. ing. The difference between the signal processing circuit 56 and the signal processing circuit 10 is that the signal processing circuit 56 generates and outputs a phase control signal for the phase shifter 48 and an amplitude control signal for the variable attenuator 49.
 説明の便宜上、図6及び図7に示すように、端子に番号を割り振る。すなわち、基準信号の入力端子を11、被測定信号の入力端子を12、制御回路46から位相振幅検波回路52に入力する制御信号の入力端子を53、位相振幅検波回路52から移相器48に出力する制御信号の出力端子を54、位相振幅検波回路52から可変減衰器49に出力する制御信号の出力端子を55とする。なお、ここで、入力端子11及び入力端子12は、図1~図5に示したものと同じである。 For convenience of explanation, numbers are assigned to terminals as shown in FIGS. That is, the reference signal input terminal 11, the signal under measurement input terminal 12, the control signal input terminal 53 from the control circuit 46 to the phase amplitude detection circuit 52, and the phase amplitude detection circuit 52 to the phase shifter 48. The output terminal of the control signal to be output is 54, and the output terminal of the control signal output from the phase amplitude detection circuit 52 to the variable attenuator 49 is 55. Here, the input terminal 11 and the input terminal 12 are the same as those shown in FIGS.
 以下、図6及び図7を用いて、本実施の形態3に係るアレーアンテナおよび送信モジュールの各構成要素について説明する。 Hereinafter, each component of the array antenna and the transmission module according to the third embodiment will be described with reference to FIGS. 6 and 7.
 図6において、制御回路46は、素子アンテナ45に供給する信号の位相および振幅を、素子アンテナ45ごとに設定するための制御信号を、各送信モジュール44の位相振幅検波回路52に出力する。 6, the control circuit 46 outputs a control signal for setting the phase and amplitude of the signal supplied to the element antenna 45 for each element antenna 45 to the phase amplitude detection circuit 52 of each transmission module 44.
 基準信号発生源42は、基準信号を出力する。ここでは、基準信号として、例えば、CW(Continuous Wave)信号を用いる。 The reference signal generation source 42 outputs a reference signal. Here, for example, a CW (Continuous Wave) signal is used as the reference signal.
 同相分配器43は、基準信号発生源42が出力した基準信号を、各送信モジュール44に対して、同相で分配する。 The in-phase distributor 43 distributes the reference signal output from the reference signal generation source 42 to each transmission module 44 in the same phase.
 方向性結合器47は、同相分配器43から出力された基準信号の一部を、入力端子11に出力し、残りを移相器48に出力する。 The directional coupler 47 outputs a part of the reference signal output from the in-phase distributor 43 to the input terminal 11 and outputs the rest to the phase shifter 48.
 移相器48には、位相振幅検波回路52の出力端子54から、位相制御信号が入力される。移相器48は、方向性結合器47から入力された基準信号の位相を、位相制御信号に従って変化させる。 A phase control signal is input to the phase shifter 48 from the output terminal 54 of the phase amplitude detection circuit 52. The phase shifter 48 changes the phase of the reference signal input from the directional coupler 47 according to the phase control signal.
 可変減衰器49は、位相振幅検波回路52の出力端子55から振幅制御信号が入力される。可変減衰器49は、移相器48から出力される基準信号の振幅を、振幅制御信号に従って変化させる。 The variable attenuator 49 receives an amplitude control signal from the output terminal 55 of the phase amplitude detection circuit 52. The variable attenuator 49 changes the amplitude of the reference signal output from the phase shifter 48 according to the amplitude control signal.
 増幅器50は、可変減衰器49から出力される基準信号の振幅を増幅する。増幅器50から出力された基準信号は方向性結合器51に入力される。 The amplifier 50 amplifies the amplitude of the reference signal output from the variable attenuator 49. The reference signal output from the amplifier 50 is input to the directional coupler 51.
 方向性結合器51は、増幅器50から入力された基準信号の一部を入力端子12に入力し、残りの信号は素子アンテナ45に入力される。入力端子12に入力された「基準信号の一部」は、被測定信号として、位相振幅検波回路52に入力される。 The directional coupler 51 inputs a part of the reference signal input from the amplifier 50 to the input terminal 12, and the remaining signal is input to the element antenna 45. The “part of the reference signal” input to the input terminal 12 is input to the phase amplitude detection circuit 52 as a signal under measurement.
 素子アンテナ45は、方向性結合器51から入力された信号を、電波として放射する。 The element antenna 45 radiates the signal input from the directional coupler 51 as a radio wave.
 位相振幅検波回路52には、入力端子11から基準信号が入力され、入力端子12から被測定信号が入力され、入力端子53から制御信号が入力される。 The phase amplitude detection circuit 52 receives a reference signal from the input terminal 11, receives a signal under measurement from the input terminal 12, and receives a control signal from the input terminal 53.
 位相振幅検波回路52は、実施の形態1および実施の形態2で説明した動作と同じ動作を行って、基準信号に対する被測定信号の相対位相θと被測定信号の振幅とを検出する。さらに、本実施の形態においては、位相振幅検波回路52は、検出した相対位相θと制御回路46から入力される制御信号によって設定される位相の設定値とを比較し、相対位相θと設定値との差に相当する位相の補正値を求めて、当該補正値を加味した移相量の値を位相制御信号として生成して移相器48に出力する。また、同様に、位相振幅検波回路52は、検出した被測定信号の振幅と制御回路46から入力される制御信号によって設定される振幅の設定値とを比較し、検出した振幅と設定値との差に相当する振幅の補正値を求めて、当該補正値を加味した減衰量の値を振幅制御信号として生成して可変減衰器49に出力する。このように、本実施の形態においては、位相振幅検波回路52が、位相の補正値および振幅の補正値に基づいて位相制御信号および振幅制御信号を生成するための補正部を有している。 The phase amplitude detection circuit 52 performs the same operation as that described in the first and second embodiments, and detects the relative phase θ of the signal under measurement with respect to the reference signal and the amplitude of the signal under measurement. Further, in the present embodiment, the phase amplitude detection circuit 52 compares the detected relative phase θ with the set value of the phase set by the control signal input from the control circuit 46, and compares the relative phase θ with the set value. A phase correction value corresponding to the difference between the two is obtained, and a phase shift amount value including the correction value is generated as a phase control signal and output to the phase shifter 48. Similarly, the phase amplitude detection circuit 52 compares the detected amplitude of the signal under measurement with the set value of the amplitude set by the control signal input from the control circuit 46, and compares the detected amplitude with the set value. An amplitude correction value corresponding to the difference is obtained, and an attenuation value with the correction value taken into account is generated as an amplitude control signal and output to the variable attenuator 49. Thus, in the present embodiment, the phase / amplitude detection circuit 52 has a correction unit for generating the phase control signal and the amplitude control signal based on the phase correction value and the amplitude correction value.
 次に、図6に示すアレーアンテナの動作について説明する。
 基準信号発生源42から出力された基準信号は、同相分配器43により、各送信モジュール44に対して同相で分配される。各送信モジュール44に入力された信号の一部は、方向性結合器47によって、入力端子11に出力される。残りの信号は移相器48に入力される。移相器48は、当該信号の位相を、位相振幅検波回路52の出力端子54から移相器48に入力される位相制御信号に従った移相量だけ変化させる。移相器48から出力される信号は、可変減衰器49に入力される。可変減衰器49は、当該信号の振幅を、位相振幅検波回路52の出力端子55から出力される振幅制御信号に従った減衰量だけ変化させる。可変減衰器49から出力される信号は、増幅器50に入力される。増幅器50は、当該信号の振幅を増幅する。増幅器50から出力された信号の一部は、方向性結合器51により、入力端子12に出力され、残りの信号は素子アンテナ45から電波として放射される。
Next, the operation of the array antenna shown in FIG. 6 will be described.
The reference signal output from the reference signal generation source 42 is distributed in phase to each transmission module 44 by the in-phase distributor 43. A part of the signal input to each transmission module 44 is output to the input terminal 11 by the directional coupler 47. The remaining signal is input to the phase shifter 48. The phase shifter 48 changes the phase of the signal by the amount of phase shift according to the phase control signal input from the output terminal 54 of the phase amplitude detection circuit 52 to the phase shifter 48. A signal output from the phase shifter 48 is input to the variable attenuator 49. The variable attenuator 49 changes the amplitude of the signal by an attenuation amount according to the amplitude control signal output from the output terminal 55 of the phase amplitude detection circuit 52. A signal output from the variable attenuator 49 is input to the amplifier 50. The amplifier 50 amplifies the amplitude of the signal. A part of the signal output from the amplifier 50 is output to the input terminal 12 by the directional coupler 51, and the remaining signal is radiated as a radio wave from the element antenna 45.
 次に、位相振幅検波回路52の動作について説明する。
 図7において、入力端子11には、方向性結合器47により、送信モジュール44に入力された基準信号の一部が入力される。
Next, the operation of the phase amplitude detection circuit 52 will be described.
In FIG. 7, a part of the reference signal input to the transmission module 44 by the directional coupler 47 is input to the input terminal 11.
 入力端子12には、方向性結合器51により、増幅器50から出力された被測定信号の一部が入力される。 A part of the signal under measurement output from the amplifier 50 is input to the input terminal 12 by the directional coupler 51.
 入力端子53には、制御回路46より、素子アンテナ45に供給する信号の位相および振幅を設定するための制御信号が入力される。 A control signal for setting the phase and amplitude of the signal supplied to the element antenna 45 is input from the control circuit 46 to the input terminal 53.
 入力端子11に入力された基準信号と入力端子12に入力された被測定信号から、基準信号に対する被測定信号の相対位相θと被測定信号の振幅との情報が含まれたディジタル信号をA/D変換器9が出力するまでの動作については、実施の形態1および実施の形態2に示した通りであるため、ここでは、その説明を省略する。 From the reference signal input to the input terminal 11 and the signal under measurement input to the input terminal 12, a digital signal including information on the relative phase θ of the signal under measurement with respect to the reference signal and the amplitude of the signal under measurement is A / Since the operation until the D converter 9 outputs is as described in the first embodiment and the second embodiment, the description thereof is omitted here.
 A/D変換器9から出力されたI成分、Q成分、振幅の3つのディジタル信号は、信号処理回路56に入力され、メモリに記憶される。信号処理回路56は、I成分の電圧VI、Q成分の電圧VQから、基準信号に対する被測定信号の相対位相θを上述した式(1)で求める。また、信号処理回路56は、式(1)で求めたθの値と、入力端子53から入力された位相の設定値とを比較し、その差分に相当する位相の補正値を求め、当該補正値に基づいて新しい移相量を算出して、当該移相量を位相制御信号として出力端子54から出力する。また、信号処理回路56は、A/D変換器9から入力されたディジタル信号から、被測定信号の振幅を算出する。そうして、信号処理回路56は、算出した振幅の値と、入力端子53から入力された振幅の設定値とを比較し、その差分に相当する振幅の補正値を求め、当該補正値に基づいて新しい減衰量を算出して、当該減衰量を振幅制御信号として出力端子55から出力する。 The three digital signals of I component, Q component, and amplitude output from the A / D converter 9 are input to the signal processing circuit 56 and stored in the memory. The signal processing circuit 56 obtains the relative phase θ of the signal under measurement with respect to the reference signal from the voltage VI of the I component and the voltage VQ of the Q component by the above-described equation (1). Further, the signal processing circuit 56 compares the value of θ obtained by the equation (1) with the set value of the phase input from the input terminal 53, obtains a phase correction value corresponding to the difference, and performs the correction. A new phase shift amount is calculated based on the value, and the phase shift amount is output from the output terminal 54 as a phase control signal. The signal processing circuit 56 calculates the amplitude of the signal under measurement from the digital signal input from the A / D converter 9. Then, the signal processing circuit 56 compares the calculated amplitude value with the set amplitude value input from the input terminal 53 to obtain an amplitude correction value corresponding to the difference, and based on the correction value. The new attenuation amount is calculated, and the attenuation amount is output from the output terminal 55 as an amplitude control signal.
 再び、図6の説明に戻り、位相振幅検波回路52の出力端子54から出力された位相制御信号は移相器48に入力される。移相器48においては、位相制御信号に基づく移相量の分だけ、基準信号の位相を現在の値から変化させる。 Returning again to the description of FIG. 6, the phase control signal output from the output terminal 54 of the phase amplitude detection circuit 52 is input to the phase shifter 48. In the phase shifter 48, the phase of the reference signal is changed from the current value by the amount of phase shift based on the phase control signal.
 位相振幅検波回路52の出力端子55から出力された振幅制御信号は可変減衰器49に入力される。可変減衰器49は、振幅制御信号に基づく減衰量の分だけ、基準信号の振幅を現在の値から変化させる。 The amplitude control signal output from the output terminal 55 of the phase amplitude detection circuit 52 is input to the variable attenuator 49. The variable attenuator 49 changes the amplitude of the reference signal from the current value by the amount of attenuation based on the amplitude control signal.
 このようにして、増幅器50の個体間の特性ばらつき、および、温度による位相特性及び振幅特性の変動を補正することにより、各素子アンテナ45に供給する信号の位相および振幅を、制御回路46により設定された位相及び振幅の設定値にそれぞれ近づけることができる。 In this way, the control circuit 46 sets the phase and amplitude of the signal supplied to each element antenna 45 by correcting the characteristic variation among the individual amplifiers 50 and the variation in the phase characteristic and amplitude characteristic due to temperature. It is possible to approach the set values of the phase and the amplitude, respectively.
 以上のように、本実施の形態における信号処理回路56は、実施の形態1及び2で示した信号処理回路10の機能に加えて、位相および振幅の補正値を加味した位相制御信号および振幅制御信号を生成する補正回路の機能を有している。 As described above, the signal processing circuit 56 according to the present embodiment includes the phase control signal and the amplitude control in consideration of the phase and amplitude correction values in addition to the functions of the signal processing circuit 10 described in the first and second embodiments. It has a function of a correction circuit that generates a signal.
 図6に示したアレーアンテナは、被測定信号の位相の検出と振幅の検出を同じ回路で行っている。また、特許文献1のように隣接する送信モジュールの出力端子間をケーブルで接続する必要が無いため、送信モジュールの配置の柔軟性を高め、簡易な構成で信号の位相と振幅を校正できる効果がある。 The array antenna shown in FIG. 6 uses the same circuit to detect the phase and amplitude of the signal under measurement. Moreover, since it is not necessary to connect the output terminals of adjacent transmission modules with a cable as in Patent Document 1, it is possible to increase the flexibility of arrangement of the transmission modules and calibrate the phase and amplitude of the signal with a simple configuration. is there.
 なお、位相振幅検波回路52の構成例として図1の構成を基本とした図7の構成を示したが、図2~図5の構成を利用しても良い。 Although the configuration of FIG. 7 based on the configuration of FIG. 1 is shown as a configuration example of the phase amplitude detection circuit 52, the configurations of FIGS. 2 to 5 may be used.
 また、図6においては、送信モジュール44が2個設けられている例を示しているが、その場合に限らず、送信モジュール44は任意の個数だけ設けてよいものとする。また、その場合においても、同様の効果が得られる。 FIG. 6 shows an example in which two transmission modules 44 are provided. However, the present invention is not limited to this, and an arbitrary number of transmission modules 44 may be provided. In that case, the same effect can be obtained.
 以上のように、本実施の形態に係る送信モジュール44は、外部から基準信号、位相制御信号、および、振幅制御信号が入力され、位相制御信号に応じて基準信号の位相を変化させるとともに、振幅制御信号に応じて基準信号の振幅を変化させる位相振幅切替部としての移相器48及び可変減衰器49と、位相振幅切替部から出力される信号の振幅を増幅する増幅器50と、位相振幅切替部に入力された基準信号と、増幅器50の出力信号である被測定信号とが入力され、基準信号と被測定信号との位相差および被測定信号の振幅を算出する位相振幅検波回路52とを備えている。また、位相振幅検波回路52が、算出した位相差の値と外部から入力される位相の設定値とを比較し、それらの差に相当する位相の補正値を加味した移相量の情報を含む位相制御信号を出力するとともに、算出した振幅の値と外部から入力される振幅の設定値とを比較し、それらの差に相当する振幅の補正値を加味した減衰量の情報を含む振幅制御信号を出力する補正部としての補正回路を有している。そのため、上述の実施の形態1および2と同様に、1つの位相振幅検波回路で、送信信号の位相と振幅を検出することが可能になる。また、上記の特許文献1に記載のように2つの送信モジュールをケーブルで接続する必要もなく、1つの送信モジュールで、送信信号の位相と振幅とが検出可能である。その結果、送信モジュールの設置における自由度を確保することができる。 As described above, the transmission module 44 according to the present embodiment receives the reference signal, the phase control signal, and the amplitude control signal from the outside, changes the phase of the reference signal in accordance with the phase control signal, and changes the amplitude. A phase shifter 48 and a variable attenuator 49 that change the amplitude of the reference signal in accordance with the control signal, an amplifier 50 that amplifies the amplitude of the signal output from the phase amplitude switching unit, and a phase amplitude switching A phase amplitude detection circuit 52 that receives the reference signal input to the unit and the signal under measurement that is the output signal of the amplifier 50 and calculates the phase difference between the reference signal and the signal under measurement and the amplitude of the signal under measurement. I have. Also, the phase amplitude detection circuit 52 compares the calculated phase difference value with the phase setting value input from the outside, and includes information on the amount of phase shift that takes into account the phase correction value corresponding to the difference. An amplitude control signal that outputs a phase control signal, compares the calculated amplitude value with an externally input amplitude setting value, and includes attenuation information that takes into account the amplitude correction value corresponding to the difference between them Has a correction circuit as a correction unit for outputting. Therefore, similarly to the first and second embodiments described above, it is possible to detect the phase and amplitude of the transmission signal with one phase amplitude detection circuit. In addition, as described in Patent Document 1, it is not necessary to connect two transmission modules with a cable, and the phase and amplitude of a transmission signal can be detected with one transmission module. As a result, it is possible to ensure the degree of freedom in installing the transmission module.
 また、本実施の形態に係るアレーアンテナは、送信モジュール44を複数個配置し、各送信モジュール44の増幅器50から出力される信号を電波として放射する素子アンテナ45と、送信モジュールに対して同相の基準信号を入力する基準信号発生源42及び同相分配器43とを備えている。従って、アレーアンテナにおいて、各送信モジュールごとに、送信信号の位相と振幅とを検出して、簡易な構成で送信信号の位相と振幅を校正することが可能になる。そのため、アレーアンテナ内の送信モジュールの配置の自由度が確保され、アレーアンテナの設計作業が容易になるという効果がある。 In addition, the array antenna according to the present embodiment includes a plurality of transmission modules 44, and an element antenna 45 that radiates a signal output from the amplifier 50 of each transmission module 44 as a radio wave, and is in phase with the transmission module. A reference signal generation source 42 for inputting a reference signal and an in-phase distributor 43 are provided. Therefore, in the array antenna, the phase and amplitude of the transmission signal can be detected for each transmission module, and the phase and amplitude of the transmission signal can be calibrated with a simple configuration. Therefore, there is an effect that the degree of freedom of arrangement of the transmission modules in the array antenna is ensured, and the design work of the array antenna becomes easy.
 1 スイッチ、2 伝送線路、3 伝送線路、4 終端器、5 スイッチ、6 終端器、7 ミクサ、8 LPF、9 A/D変換器、10 信号処理回路、11,12,14,18,19,20,25,26,33,36,39,40 入力端子、13,15,16,17,21,27,34,35,37,38,41 出力端子、22 90°,3dBカップラ、23 スイッチ、24 終端器、28 スイッチ、29 スイッチ、30 伝送線路、31 伝送線路、32 スイッチ、42 基準信号発生源、43 同相分配器、44 送信モジュール、45 素子アンテナ、46 制御回路、47 方向性結合器、48 移相器、49 可変減衰器、50 増幅器、51 方向性結合器、52 位相振幅検波回路、56 信号処理回路、57 移相器、101 基準信号発生源、102 同相分配器、103 送信モジュール、104 素子アンテナ、105 移相器、106 可変減衰器、107 増幅器。 1 switch, 2 transmission line, 3 transmission line, 4 terminator, 5 switch, 6 terminator, 7 mixer, 8 LPF, 9 A / D converter, 10 signal processing circuit, 11, 12, 14, 18, 19, 20, 25, 26, 33, 36, 39, 40 input terminal, 13, 15, 16, 17, 21, 27, 34, 35, 37, 38, 41 output terminal, 22 90 °, 3 dB coupler, 23 switch, 24 terminator, 28 switch, 29 switch, 30 transmission line, 31 transmission line, 32 switch, 42 reference signal generation source, 43 in-phase distributor, 44 transmission module, 45 element antenna, 46 control circuit, 47 directional coupler, 48 phase shifters, 49 variable attenuators, 50 amplifiers, 51 directional couplers, 52 phase amplitude detection circuits, 56 signal processing times , 57 phase shifter, 101 a reference signal generating source, 102 phase splitter, 103 transmission module, 104 antenna elements, 105 phase shifter, 106 a variable attenuator, 107 amplifier.

Claims (7)

  1.  基準信号及び被測定信号が入力され、前記基準信号および前記被測定信号の位相を0°変化させて前記基準信号および前記被測定信号を出力する第1の状態、前記基準信号または前記被測定信号のいずれか一方の位相のみを90°変化させて前記基準信号および前記被測定信号を出力する第2の状態、および、前記基準信号の通過を遮断して前記被測定信号のみを出力する第3の状態の3つの状態を順に切り替えて動作する信号切替部と、
     前記信号切替部に接続され、前記信号切替部の状態が前記第1の状態または前記第2の状態の場合に前記基準信号と前記被測定信号とを混合させるとともに、前記信号切替部の状態が前記第3の状態の場合に前記被測定信号の振幅を検波する、ミクサと、
     前記ミクサから出力される信号から直流成分を抽出する低域通過フィルタと、
     前記低域通過フィルタから出力される前記直流成分の電圧をディジタル信号に変換するA/D変換器と、
     前記信号切替部が前記第1の状態及び前記第2の状態の場合に前記A/D変換器から出力される2つの前記ディジタル信号に基づいて前記基準信号と前記被測定信号との位相差を算出するとともに、前記信号切替部が前記第3の状態の場合に前記A/D変換器から出力される前記ディジタル信号に基づいて前記被測定信号の振幅を算出する信号処理回路と
     を備えた、位相振幅検波回路。
    A first state in which a reference signal and a signal under measurement are input, a phase of the reference signal and the signal under measurement is changed by 0 °, and the reference signal and the signal under measurement are output, the reference signal or the signal under measurement A second state in which only one of the phases is changed by 90 ° to output the reference signal and the signal under measurement, and a third state in which only the signal under measurement is output by blocking the passage of the reference signal A signal switching unit that operates by sequentially switching the three states of
    The reference signal and the signal under measurement are mixed when the state of the signal switching unit is connected to the signal switching unit and the state of the signal switching unit is the first state or the second state, and the state of the signal switching unit is A mixer for detecting the amplitude of the signal under measurement in the third state;
    A low-pass filter that extracts a DC component from the signal output from the mixer;
    An A / D converter that converts the voltage of the DC component output from the low-pass filter into a digital signal;
    When the signal switching unit is in the first state and the second state, the phase difference between the reference signal and the signal under measurement is calculated based on the two digital signals output from the A / D converter. And a signal processing circuit that calculates an amplitude of the signal under measurement based on the digital signal output from the A / D converter when the signal switching unit is in the third state. Phase amplitude detection circuit.
  2.  前記信号切替部は、
     前記基準信号または前記被測定信号の位相を0°及び90°変化させる移相部と、
     前記基準信号を終端させる終端器と、
     前記第1の状態および前記第2の状態の場合に前記移相部を選択し、前記第3の状態の場合に前記終端器を選択するスイッチと
     を有する、
     請求項1に記載の位相振幅検波回路。
    The signal switching unit is
    A phase shifter for changing the phase of the reference signal or the signal under measurement by 0 ° and 90 °;
    A terminator for terminating the reference signal;
    A switch for selecting the phase shifter in the case of the first state and the second state, and for selecting the terminator in the case of the third state,
    The phase amplitude detection circuit according to claim 1.
  3.  前記移相部は、電気長が互いに90°異なる2つの伝送線路から構成されている、
     請求項2に記載の位相振幅検波回路。
    The phase shift part is composed of two transmission lines whose electrical lengths are different from each other by 90 °.
    The phase amplitude detection circuit according to claim 2.
  4.  前記移相部は、90°,3dBカップラから構成されている、
     請求項2に記載の位相振幅検波回路。
    The phase shift unit is composed of a 90 °, 3 dB coupler,
    The phase amplitude detection circuit according to claim 2.
  5.  前記移相部は、移相器から構成されている、
     請求項2に記載の位相振幅検波回路。
    The phase shift unit is composed of a phase shifter.
    The phase amplitude detection circuit according to claim 2.
  6.  外部から基準信号、位相制御信号、および、振幅制御信号が入力され、前記位相制御信号に応じて前記基準信号の位相を変化させるとともに、前記振幅制御信号に応じて前記基準信号の振幅を変化させる位相振幅切替部と、
     前記位相振幅切替部から出力される信号の振幅を増幅する増幅器と、
     前記位相振幅切替部に入力された前記基準信号と、前記増幅器の出力信号である被測定信号とが入力され、前記基準信号と前記被測定信号との位相差および前記被測定信号の振幅を算出する、請求項1から5までのいずれか1項に記載の前記位相振幅検波回路と、
     前記位相振幅検波回路で算出された前記位相差の値と外部から入力される位相の設定値とを比較し、それらの差に相当する位相の補正値に基づいて生成した前記位相制御信号を前記位相振幅切替部に出力するとともに、前記位相振幅検波回路で算出された前記振幅の値と外部から入力される振幅の設定値とを比較し、それらの差に相当する振幅の補正値に基づいて生成した前記振幅制御信号を前記位相振幅切替部に出力する補正部と
     を備えた、
     送信モジュール。
    A reference signal, a phase control signal, and an amplitude control signal are input from the outside, and the phase of the reference signal is changed according to the phase control signal, and the amplitude of the reference signal is changed according to the amplitude control signal. A phase amplitude switching unit;
    An amplifier that amplifies the amplitude of the signal output from the phase amplitude switching unit;
    The reference signal input to the phase amplitude switching unit and the signal under measurement that is an output signal of the amplifier are input, and the phase difference between the reference signal and the signal under measurement and the amplitude of the signal under measurement are calculated. The phase amplitude detection circuit according to any one of claims 1 to 5,
    Comparing the phase difference value calculated by the phase amplitude detection circuit with a phase setting value input from the outside, and generating the phase control signal generated based on a phase correction value corresponding to the difference Based on the amplitude correction value corresponding to the difference between the amplitude value calculated by the phase amplitude detection circuit and the amplitude setting value input from the outside while being output to the phase amplitude switching unit A correction unit that outputs the generated amplitude control signal to the phase amplitude switching unit,
    Transmission module.
  7.  請求項6に記載の前記送信モジュールを複数個配置し、
     各前記送信モジュールの前記増幅器から出力される信号を電波として放射する素子アンテナと、
     各前記送信モジュールに対して同相の基準信号を入力する基準信号発生部と
     を備えた、
     アレーアンテナ。
    A plurality of the transmission modules according to claim 6 are arranged,
    An element antenna that radiates a signal output from the amplifier of each of the transmission modules as a radio wave;
    A reference signal generator for inputting a reference signal in phase to each of the transmission modules,
    Array antenna.
PCT/JP2016/087240 2016-12-14 2016-12-14 Phase and amplitude detection circuit, transmission module and array antenna WO2018109871A1 (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
PCT/JP2016/087240 WO2018109871A1 (en) 2016-12-14 2016-12-14 Phase and amplitude detection circuit, transmission module and array antenna
JP2018541229A JP6452915B2 (en) 2016-12-14 2016-12-14 Phase amplitude detection circuit, transmission module, and array antenna

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/JP2016/087240 WO2018109871A1 (en) 2016-12-14 2016-12-14 Phase and amplitude detection circuit, transmission module and array antenna

Publications (1)

Publication Number Publication Date
WO2018109871A1 true WO2018109871A1 (en) 2018-06-21

Family

ID=62559630

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/JP2016/087240 WO2018109871A1 (en) 2016-12-14 2016-12-14 Phase and amplitude detection circuit, transmission module and array antenna

Country Status (2)

Country Link
JP (1) JP6452915B2 (en)
WO (1) WO2018109871A1 (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2019221130A1 (en) * 2018-05-17 2019-11-21 日本電気株式会社 Array communication device and method for controlling same
CN113348371A (en) * 2019-01-22 2021-09-03 意法半导体有限公司 Method and apparatus for signal phase detection via hybrid coupler using reference phase
WO2022249426A1 (en) * 2021-05-28 2022-12-01 三菱電機株式会社 Phase detection circuit

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63118580U (en) * 1987-01-23 1988-08-01
JPH08186447A (en) * 1994-12-28 1996-07-16 Japan Radio Co Ltd Phase detecting circuit for rader receiver
WO2011108397A1 (en) * 2010-03-04 2011-09-09 三菱電機株式会社 Array antenna device
JP2013201556A (en) * 2012-03-23 2013-10-03 Panasonic Corp Phased-array transmitter

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2002246825A (en) * 2001-02-20 2002-08-30 Nippon Hoso Kyokai <Nhk> Array antenna system

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63118580U (en) * 1987-01-23 1988-08-01
JPH08186447A (en) * 1994-12-28 1996-07-16 Japan Radio Co Ltd Phase detecting circuit for rader receiver
WO2011108397A1 (en) * 2010-03-04 2011-09-09 三菱電機株式会社 Array antenna device
JP2013201556A (en) * 2012-03-23 2013-10-03 Panasonic Corp Phased-array transmitter

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2019221130A1 (en) * 2018-05-17 2019-11-21 日本電気株式会社 Array communication device and method for controlling same
US11621488B2 (en) 2018-05-17 2023-04-04 Nec Corporation Array communication device and method for controlling same
CN113348371A (en) * 2019-01-22 2021-09-03 意法半导体有限公司 Method and apparatus for signal phase detection via hybrid coupler using reference phase
WO2022249426A1 (en) * 2021-05-28 2022-12-01 三菱電機株式会社 Phase detection circuit
JPWO2022249426A1 (en) * 2021-05-28 2022-12-01
JP7412640B2 (en) 2021-05-28 2024-01-12 三菱電機株式会社 Phase shift detection circuit

Also Published As

Publication number Publication date
JPWO2018109871A1 (en) 2018-12-20
JP6452915B2 (en) 2019-01-16

Similar Documents

Publication Publication Date Title
US11411311B2 (en) System and method for measuring a plurality of RF signal paths
JP5736545B2 (en) Phased array antenna inter-branch correction device and phased array antenna inter-branch correction method
CN108234037B (en) Phase calibration method and circuit
JP6452915B2 (en) Phase amplitude detection circuit, transmission module, and array antenna
JP2018533266A (en) Serial interconnect calibration
KR20170010728A (en) System and method for a directional coupler
WO2017145257A1 (en) Array antenna device and calibration method therefor
JP7002257B2 (en) Receiver test
US7982663B2 (en) Digital signal processor
JP6701124B2 (en) Radar equipment
US10330775B2 (en) Transmitter, transmission method, phase adjustment device, and phase adjustment method
US20120294388A1 (en) Vector modulator
US9509346B2 (en) Circuit and method for a circuit
US11367953B2 (en) Antenna device and calibration method
JP5904804B2 (en) Calibration system for calibration path of phased array antenna
JP7012918B2 (en) Antenna device and calibration method
US9917660B2 (en) Wireless communication device and wireless communication system
JP2020098966A (en) Phase difference adjustment circuit
CN113243091A (en) Apparatus and method for automatic calibration of antenna arrays
KR102670400B1 (en) Phase shifter and method for phase shifter
JP2017005647A (en) Phase control device and array antenna system
KR101259605B1 (en) Phase shift process using for differential amplifier and hybrid coupler
JP2015106878A (en) Phased array antenna device and communication system
US11621488B2 (en) Array communication device and method for controlling same
WO2019127398A1 (en) Phase alignment method and circuit

Legal Events

Date Code Title Description
ENP Entry into the national phase

Ref document number: 2018541229

Country of ref document: JP

Kind code of ref document: A

121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 16923840

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 16923840

Country of ref document: EP

Kind code of ref document: A1