JPS63117170U - - Google Patents
Info
- Publication number
- JPS63117170U JPS63117170U JP715087U JP715087U JPS63117170U JP S63117170 U JPS63117170 U JP S63117170U JP 715087 U JP715087 U JP 715087U JP 715087 U JP715087 U JP 715087U JP S63117170 U JPS63117170 U JP S63117170U
- Authority
- JP
- Japan
- Prior art keywords
- video signal
- circuit
- signal receiving
- audio
- receiving circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000001514 detection method Methods 0.000 claims description 4
- 230000003321 amplification Effects 0.000 claims description 3
- 238000003199 nucleic acid amplification method Methods 0.000 claims description 3
- 230000005236 sound signal Effects 0.000 claims 1
- 238000010586 diagram Methods 0.000 description 4
- 238000000605 extraction Methods 0.000 description 1
- 230000001360 synchronised effect Effects 0.000 description 1
Landscapes
- Picture Signal Circuits (AREA)
Description
第１図は本考案に係る映像信号受信回路のブロ
ツク図、第２図は検波回路に装備されたトランジ
スターと可変抵抗器を示す回路図、第３図は本考
案に係る映像信号受信回路の他の実施例を示すブ
ロツク図、第４図はビート信号の変化を表わすグ
ラフ、第５図は従来回路のブロツク図である。
１……チユーナ、５……映像中間周波増幅回路
、６……疑似同期検波回路、６３……乗算回路、
６４……映像搬送波抽出回路、７……可変抵抗器
。
Fig. 1 is a block diagram of the video signal receiving circuit according to the present invention, Fig. 2 is a circuit diagram showing the transistors and variable resistors installed in the detection circuit, and Fig. 3 is a block diagram of the video signal receiving circuit according to the present invention. FIG. 4 is a graph showing changes in the beat signal, and FIG. 5 is a block diagram of a conventional circuit. 1... Tuner, 5... Video intermediate frequency amplification circuit, 6... Pseudo synchronous detection circuit, 63... Multiplier circuit,
64...Video carrier wave extraction circuit, 7...Variable resistor.
Claims (1)
幅回路５と、該増幅回路５から出力される音声信
号及び映像信号を検波する検波回路６とを装備し
た映像信号受信回路に於いて、検波回路６の出力
端には、該回路６に装備されたトランジスターの
バイアス抵抗となる可変抵抗器７を接続し、該可
変抵抗器７の抵抗値は、音声ビート妨害が許容値
以下となる様に調節されていることを特徴とする
映像信号受信回路。 音声ビート妨害は略９２０ＫＨｚのビート信
号によるものである実用新案登録請求の範囲第１
項に記載の映像信号受信回路。[Claims for Utility Model Registration] A video signal receiving circuit equipped with a video intermediate frequency amplification circuit 5 to which the output of the tuner 1 is connected, and a detection circuit 6 that detects the audio signal and video signal output from the amplification circuit 5. In this case, a variable resistor 7 is connected to the output terminal of the detection circuit 6, and the resistance value of the variable resistor 7 is set to a value that allows for audio beat disturbance. A video signal receiving circuit characterized by being adjusted as follows. The audio beat disturbance is caused by a beat signal of about 920 KHz. Utility model registration claim 1
The video signal receiving circuit described in .
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP715087U JPS63117170U (en) | 1987-01-20 | 1987-01-20 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP715087U JPS63117170U (en) | 1987-01-20 | 1987-01-20 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS63117170U true JPS63117170U (en) | 1988-07-28 |
Family
ID=30790338
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP715087U Pending JPS63117170U (en) | 1987-01-20 | 1987-01-20 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS63117170U (en) |
-
1987
- 1987-01-20 JP JP715087U patent/JPS63117170U/ja active Pending
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