JPS6221676U - - Google Patents
Info
- Publication number
- JPS6221676U JPS6221676U JP11186085U JP11186085U JPS6221676U JP S6221676 U JPS6221676 U JP S6221676U JP 11186085 U JP11186085 U JP 11186085U JP 11186085 U JP11186085 U JP 11186085U JP S6221676 U JPS6221676 U JP S6221676U
- Authority
- JP
- Japan
- Prior art keywords
- pll circuit
- tuner
- television receiver
- signal
- video
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 230000005236 sound signal Effects 0.000 claims 1
- 238000010586 diagram Methods 0.000 description 3
- 238000001514 detection method Methods 0.000 description 2
Landscapes
- Television Receiver Circuits (AREA)
Description
第１図は本考案の一実施例の構成を示すブロツ
ク図、第２図は従来例の構成を示すブロツク図、
第３図は映像中間周波フイルタの周波数特性を示
す線図である。
１……フロントエンド、４……映像中間周波信
号検波回路、１１……音声中間周波信号検波回路
、１２……ＶＣＯ、１３ａ……位相比較回路、１
４……映像キヤリア通過フイルタ。
FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention, FIG. 2 is a block diagram showing the configuration of a conventional example,
FIG. 3 is a diagram showing the frequency characteristics of the video intermediate frequency filter. 1...Front end, 4...Video intermediate frequency signal detection circuit, 11...Audio intermediate frequency signal detection circuit, 12...VCO, 13a...Phase comparison circuit, 1
4...Video carrier passing filter.
Claims (1)
映像信号、音声信号を夫々個別に同期検波するテ
レビジヨン受像機におけるチユーナにおいて、復
調されるべき主信号経路とは独立してフロントエ
ンドから出力された中間周波数信号を、映像キヤ
リア周波数近傍で平坦な周波数特性のフイルタを
介してＰＬＬ回路に供給し、このＰＬＬ回路によ
り発生させたキヤリアで前記同期検波することを
特徴とするテレビジヨン受像機におけるチユーナ
。 In a tuner in a television receiver that separately and synchronously detects video and audio signals using a carrier generated by a PLL circuit, an intermediate frequency output from the front end independently of the main signal path to be demodulated. A tuner for a television receiver, characterized in that a signal is supplied to a PLL circuit through a filter having a flat frequency characteristic near a video carrier frequency, and the signal is synchronously detected by a carrier generated by the PLL circuit.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP11186085U JPS6221676U (en) | 1985-07-23 | 1985-07-23 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP11186085U JPS6221676U (en) | 1985-07-23 | 1985-07-23 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6221676U true JPS6221676U (en) | 1987-02-09 |
Family
ID=30992178
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP11186085U Pending JPS6221676U (en) | 1985-07-23 | 1985-07-23 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6221676U (en) |
-
1985
- 1985-07-23 JP JP11186085U patent/JPS6221676U/ja active Pending
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