JPS63115301A - Chip resistor - Google Patents
Chip resistorInfo
- Publication number
- JPS63115301A JPS63115301A JP61261410A JP26141086A JPS63115301A JP S63115301 A JPS63115301 A JP S63115301A JP 61261410 A JP61261410 A JP 61261410A JP 26141086 A JP26141086 A JP 26141086A JP S63115301 A JPS63115301 A JP S63115301A
- Authority
- JP
- Japan
- Prior art keywords
- resistive film
- film
- substrate
- chip resistor
- electrode
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000000758 substrate Substances 0.000 claims description 17
- 239000011521 glass Substances 0.000 claims description 6
- 239000011248 coating agent Substances 0.000 claims description 4
- 238000000576 coating method Methods 0.000 claims description 4
- 238000009966 trimming Methods 0.000 description 6
- 239000000919 ceramic Substances 0.000 description 3
- 239000012212 insulator Substances 0.000 description 3
- 238000000034 method Methods 0.000 description 3
- 230000002950 deficient Effects 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000006073 displacement reaction Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 239000012528 membrane Substances 0.000 description 1
Landscapes
- Apparatuses And Processes For Manufacturing Resistors (AREA)
- Non-Adjustable Resistors (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Abstract] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は、セラミック等の絶縁体製の基板の表面に、抵
抗被膜を形成して成るチップ抵抗器の改良に関するもの
である。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an improvement in a chip resistor in which a resistive film is formed on the surface of a substrate made of an insulator such as ceramic.
この種のチップ抵抗器は、セラミック等の絶縁体製の基
板１の表面に、先づ第４図及び第５図に示すようにその
左右両端部に電極膜２ａ、２ｂを塗着し、次いで、該両
電極膜２ａ、２ｂ間の部分に抵抗膜３を両電極膜２ａ、
２ｂに跨るようにして塗着し、この抵抗膜３をガラス膜
４にて覆ったのち、ガラス膜４の上から前記抵抗膜３に
レーザートリミングにて切欠溝５を刻設するごとにより
、所定の抵抗値を得るようにしたものであり、所定の抵
抗値を得るための前記レーザートリミングによる切欠溝
５の加工は、自動機によって行なわれるものである。This type of chip resistor is manufactured by coating the surface of a substrate 1 made of an insulator such as ceramic with electrode films 2a and 2b on both left and right ends, as shown in FIGS. 4 and 5. , a resistive film 3 is placed between the two electrode films 2a and 2b, and the two electrode films 2a,
2b, and after covering this resistive film 3 with a glass film 4, a predetermined cut groove 5 is carved by laser trimming into the resistive film 3 from above the glass film 4. In order to obtain a predetermined resistance value, the cutting groove 5 is formed by laser trimming using an automatic machine.
しかし、基板１に対する抵抗膜３の塗着は、印刷によっ
て行なわれ、基板１に対する抵抗膜３の塗着位置には、
常にずれが存在するものであるから、前記レーザートリ
ミングにて切欠溝５を刻設する位置を、基板の側面を基
準として、この側面からの寸法によって求める方法では
、抵抗膜３に対して所定寸法の切欠溝５を刻設すること
ができず、抵抗値にハラ付きが発生することになる。However, the coating of the resistive film 3 on the substrate 1 is performed by printing, and the coating position of the resistive film 3 on the substrate 1 is
Since there is always a misalignment, the method of determining the position at which the notch groove 5 is carved by laser trimming based on the dimension from the side surface of the substrate with the side surface of the substrate as a reference is based on the method of determining the position at which the notch groove 5 is carved in the laser trimming by using the dimension from this side surface as a reference. It is not possible to form the cutout grooves 5, and the resistance value becomes uneven.
そこで、先行技術としての特開昭５８−１４５０２号公
報は、抵抗膜３の色と基板１の表面の色との間に明度の
差があることに鑑み、基板の表面に抵抗膜３を塗着する
とき同時に、第４図に示すように当該抵抗膜３と同じ材
料で認識マーク６を塗着しておき、この認識マーク６を
光学的に明度の差によって読み取り、この認識マーク６
の位置を基準として、切欠溝を刻設することを提案して
いる。Therefore, in consideration of the difference in brightness between the color of the resistive film 3 and the color of the surface of the substrate 1, Japanese Patent Application Laid-Open No. 58-14502 discloses that the resistive film 3 is coated on the surface of the substrate. At the same time, as shown in FIG. 4, a recognition mark 6 is coated with the same material as the resistive film 3, and this recognition mark 6 is optically read based on the difference in brightness.
It is proposed to carve a notch groove based on the position of .
しかし、基板１の表面の両端部における電極膜２ａ、
２ｂも、前記抵抗膜３と同様に印刷によって塗着され
るものであり、この両電極膜２ａ、２ｂの基板１に対す
る塗着位置にも、ずれが存在するものであるから、抵抗
膜３に切欠溝５を刻設する位置を、前記先行技術のよう
に抵抗膜３と同時に塗着した認識マーク６によって求め
る方法では、第６図に示すように、両電極膜２ａ、２ｂ
のうち一方の電極膜２ａが他方の電極膜２ｂよりも長く
なるようにずれると共に、抵抗膜３が前記一方の電極膜
２ａ側にずれている場合には、抵抗膜３と同時に塗着し
た認識マーク６を基準として刻設される切欠溝５は、そ
の一部が、前記一方の電極膜２ａにかかって終う不良品
が発生する点に問題があった。However, the electrode film 2a at both ends of the surface of the substrate 1,
2b is also applied by printing in the same manner as the resistive film 3, and since there is a misalignment in the application position of both electrode films 2a and 2b with respect to the substrate 1, the resistive film 3 In the method of determining the position where the cutout groove 5 is to be carved using the recognition mark 6 applied at the same time as the resistive film 3 as in the prior art, as shown in FIG.
If one of the electrode films 2a is shifted so that it is longer than the other electrode film 2b, and the resistive film 3 is shifted toward the one electrode film 2a, it is recognized that the resistive film 3 was coated at the same time. The notch groove 5 carved with the mark 6 as a reference has a problem in that a portion thereof ends up covering the one electrode film 2a, resulting in defective products.
本発明は、この問題を解消することを目的とするもので
ある。The present invention aims to solve this problem.
この目的を達成するために本発明は、絶縁体製の基板の
表面に、その両端部に電極膜を、該両電極膜に跨って抵
抗膜を、そして前記抵抗膜を覆うガラス膜を各々塗着し
て成るチップ抵抗器において、前記抵抗膜の両端部分に
、幅方向への突出部を一体的に設けた構成にしたもので
ある。In order to achieve this object, the present invention coats the surface of an insulating substrate with an electrode film on both ends thereof, a resistive film spanning both electrode films, and a glass film covering the resistive film. In this chip resistor, protrusions in the width direction are integrally provided at both end portions of the resistive film.
以下本発明の実施例を図面について説明すると、第１図
及び第２図において符号１はセラミック等の絶縁体製の
基板、符号２ａ、２ｂは前記基板１の表面における両端
部分に塗着した電極膜、符号３は前記基板１の表面にお
いて前記両電極膜２ａ。Embodiments of the present invention will be described below with reference to the drawings. In FIGS. 1 and 2, numeral 1 is a substrate made of an insulator such as ceramic, and numerals 2a and 2b are electrodes coated on both ends of the surface of the substrate 1. A film, reference numeral 3, is the both electrode films 2a on the surface of the substrate 1.
２ｂ間の部分に両電極膜２ａ、２ｂに跨るように塗着し
た抵抗膜、符号４は前記抵抗膜３を覆うように塗着した
ガラス膜を各々示す。2b, a resistive film is applied so as to straddle both electrode films 2a and 2b, and reference numeral 4 indicates a glass film applied to cover the resistive film 3.
そして、前記抵抗膜３の両端部分には、幅方向への突出
部３ａ、３ｂを一体的に形成する。この幅方向への突出
部３ａ、３ｂは、抵抗膜３の左右両側面に設けても良く
、また、第３図に示すように、抵抗膜３の両端部を幅広
にした形態にしても良い。Projections 3a and 3b extending in the width direction are integrally formed at both end portions of the resistive film 3. These protrusions 3a and 3b in the width direction may be provided on both left and right side surfaces of the resistive film 3, or, as shown in FIG. 3, both ends of the resistive film 3 may be made wider. .
このように構成すると、抵抗膜３に、自動レーザートリ
ミングにて切欠溝５を刻設することによって抵抗値を所
定値にするに際して、光学的に、前記抵抗膜３における
長手側面３Ｃ及び両突出部３ａ、３ｂを検出し、この長
手側面３Ｃ及び両突出部３ａ、３ｂを基準として、切欠
溝５の位置を設定することにより、長手側面３Ｃから幅
方向への切欠溝５の切込み深さＳを、所定寸法に正確に
規定することができると共に、切欠溝５を、前記両当該
突出部３ａ、３ｂ間の寸法りの範囲内に位置することが
確実にできるのである。With this configuration, when setting the resistance value to a predetermined value by carving the notch groove 5 in the resistive film 3 by automatic laser trimming, the longitudinal side surface 3C and both protrusions of the resistive film 3 are optically removed. 3a and 3b, and set the position of the notch groove 5 with reference to the longitudinal side surface 3C and both protrusions 3a and 3b, thereby determining the cutting depth S of the notch groove 5 in the width direction from the longitudinal side surface 3C. , it is possible to accurately define the predetermined dimensions, and it is also possible to reliably position the cutout groove 5 within the range of the dimensions between the two protrusions 3a and 3b.
以上の通り本発明によると、抵抗膜の両端部分に、幅方
向への突出部を設けたことにより、自動レーザートリミ
ングによる切欠溝の抵抗膜に対する幅方向への切込み深
さを正確に所定寸法にできるのであり、しかも、抵抗膜
に対する切欠溝を、前記両突出部の範囲内に位置するこ
とが確実にできるから、基板に対する抵抗膜の位置のず
れにより前記先行技術のように切欠溝が、一方の電極膜
にかかるようなことが少なくなり、不良品の発生を確実
に低減できる効果を有する。As described above, according to the present invention, by providing protrusions in the width direction at both ends of the resistive film, the cutting depth of the notched groove in the width direction of the resistive film by automatic laser trimming can be accurately set to a predetermined dimension. Moreover, since the notch groove for the resistive film can be reliably located within the range of both of the protrusions, the notch groove can be positioned on one side as in the prior art due to the displacement of the resistive film with respect to the substrate. This has the effect of reliably reducing the occurrence of defective products.
第１図は本発明の第１実施例チップ抵抗器の平面図、第
２図は第１図のｎ−ｎ視拡大断面図、第３図は本発明第
２実施例チップ抵抗器の平面図、第４図は従来のチップ
抵抗器の平面図、第５図は第４図のＶ−Ｖ視拡大断面図
、第６図は従来のチップ抵抗器において電極膜及び抵抗
膜がずれた場合の平面図である。
１・・・・基板、２ａ、 ２ｂ・・・・電極膜、３・
・・・抵抗膜、３ａ、３ｂ・・・・突出部、４・・・・
ガラス膜。
６一FIG. 1 is a plan view of a chip resistor according to a first embodiment of the present invention, FIG. 2 is an enlarged sectional view taken along the line nn of FIG. 1, and FIG. 3 is a plan view of a chip resistor according to a second embodiment of the present invention. , FIG. 4 is a plan view of a conventional chip resistor, FIG. 5 is an enlarged cross-sectional view taken along the line V-V in FIG. 4, and FIG. FIG. 1... Substrate, 2a, 2b... Electrode film, 3...
...Resistive film, 3a, 3b...Protrusion, 4...
glass membrane. 61
Claims (1)
を、該両電極膜に跨って抵抗膜を、そして前記抵抗膜を
覆うガラス膜を各々塗着して成るチップ抵抗器において
、前記抵抗膜の両端部分に、幅方向への突出部を一体的
に設けたことを特徴とするチップ抵抗器。(1) A chip resistor made by coating the surface of an insulating substrate with an electrode film on both ends thereof, a resistive film spanning both electrode films, and a glass film covering the resistive film. 2. A chip resistor according to claim 1, wherein a protrusion in the width direction is integrally provided at both end portions of the resistive film.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61261410A JPH0758641B2 (en) | 1986-10-31 | 1986-10-31 | Chip resistor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61261410A JPH0758641B2 (en) | 1986-10-31 | 1986-10-31 | Chip resistor |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS63115301A true JPS63115301A (en) | 1988-05-19 |
| JPH0758641B2 JPH0758641B2 (en) | 1995-06-21 |
Family
ID=17361482
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP61261410A Expired - Lifetime JPH0758641B2 (en) | 1986-10-31 | 1986-10-31 | Chip resistor |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0758641B2 (en) |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5979603A (en) * | 1982-10-28 | 1984-05-08 | Sony Corp | Antenna |
| JPS6071102U (en) * | 1983-10-20 | 1985-05-20 | 三洋電機株式会社 | thick film resistor |
-
1986
- 1986-10-31 JP JP61261410A patent/JPH0758641B2/en not_active Expired - Lifetime
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5979603A (en) * | 1982-10-28 | 1984-05-08 | Sony Corp | Antenna |
| JPS6071102U (en) * | 1983-10-20 | 1985-05-20 | 三洋電機株式会社 | thick film resistor |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0758641B2 (en) | 1995-06-21 |
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