JPS63115269A - Input control system for hierarchical logic - Google Patents

Abstract

PURPOSE:To facilitate correspondence between higher hierarchical logic and lower hierarchical logic in case of development to higher hierarchical logic and lower hierarchical logic by storing the display size of the lower hierarchy in the information storage area of a logic block of the higher hierarchy. CONSTITUTION:A lower hierarchical logic display area size 26 of each logic block is provided in the library of logic elements G1-G3. Thus, respective lower hierarchical display sizes of elements G1-G3 are taken out in a minimum time in case of addition of the element G2 to a higher hierarchical logic diagram 21. In case the element G2 is built in the logic diagram 21, duplications between elements G1 and G2, elements G1 and G3, and elements G2 and G3 including display areas of wirings are checked to complete display positions of elements G1-G3 shown in a higher hierarchical logic diagram 22. Elements G1-G3 are developed to lower hierarchical logics to facilitate to correspond respective parts of the higher hierarchical logic diagram 22 and those of the lower hierarchical logic diagram 27 each other.

Description

DETAILED DESCRIPTION OF THE INVENTION A. Field of Industrial Application The present invention relates to an input control method for hierarchically structured logic.

Conventionally, hierarchically structured logic constructed by combining logical blocks having a single logical element having a specific logical function or a combination of multiple logical elements in the following hierarchical structure is input to an arbitrary processing device. In this case, there is known an input method for hierarchically structured logic in which a combination of logic elements in the logic block is input as a lower layer, and a combination of the logic blocks is input as an upper layer (for example, Japanese Patent Laid-Open No. 60-33666 Publication No.).

In such a hierarchical structure type logic input control system, as shown in FIG.
, first input the logic diagram 16 of the logic element OA, 08 as the lower hierarchy, then input the upper hierarchy logic block G as the upper hierarchy logic diagram 8, and A method is adopted in which the concatenated information of G, OA, and GEI is stored. At that time, G, OA.

The display size for displaying G, OA, , CB in each CB library was stored in storage area 11.12.15 (note that 9.10.13. in the figure).
14 indicates each display area). However, with such a library configuration, in a control method that inputs logic having a logical structure, the display size of a logic block input as an upper layer may be smaller than that required for displaying a lower layer of the logic block. There are many cases where the size is smaller than the displayed size. Therefore, if you try to expand the logic of the upper hierarchy to the logic of the lower hierarchy, the display position of the lower hierarchy logic of each logic block existing in the upper hierarchy will be different from the display position of the logic block in the upper hierarchy.
There was a problem in that it became difficult to associate the upper layer logic with the lower layer logic. This problem can be temporarily solved by calculating the lower layer display size of each logic block when inputting the upper layer logic and ensuring that there is no display overlap between logical elements at the lower layer logic level. However, just calculating the lower layer OA of G shown in Fig. 5 and the display size of day G,
After reading the library of OA and checking the existence of QB, reading the library of OA and 0 days, OA and GEI
It is necessary to take the display size of OA and further calculate the wiring display area between OA and 08. For this reason, from the viewpoint of responsiveness, it is difficult to input upper layer logic while checking the interval between logical blocks in the upper layer based on the display size of the lower layer.

C0 Purpose of the Invention An object of the present invention is to set the display position of each logical block when the upper layer logic of a hierarchical structure type logic having a logic block composed of a single or multiple logic elements is developed into a lower layer logic. The object is to display the lower hierarchical logic of the logical block and facilitate the correspondence between the upper hierarchical logic and the lower hierarchical logic.

20 Structure of the Invention That is, in the present invention, when inputting a hierarchical structure amount logic constructed by combining logic blocks having a single logic element or a combination thereof as a lower hierarchical structure, the logic in the logic block is By inputting a combination of elements as a lower layer and storing the display size for displaying the lower layer of the logic block in the information storage area that displays the logic block, each logic when inputting the logic block is stored. The present invention relates to an input control method for hierarchically structured logic, characterized in that an interval between blocks is checked based on the display size when displaying a lower hierarchy of each logic block.

E, Example Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

FIG. 1 shows an example in which the present invention is applied to an input control method when inputting a circuit logic diagram having a hierarchical structure.

In this example, the upper floor N logic diagram 21 is composed of two logic blocks G1 and G3, and now consider the case where a logic block G2 is added to the upper floor N logic diagram 21.

The display area of the lower hierarchy logic diagram of logic blocks G1, G2, 'G3 is as shown in 23.24.25, and in the upper hierarchy logic diagram 21, the lower hierarchy display area 23.24.25 is carefully considered and G2 is displayed. If you have added it to the G2 installation position of the upper layer logic diagram 21, 01 in the upper layer logic diagram
, G2, G3 to the lower hierarchy, G1, G2,
01, G due to the relationship of the display area size of each lower layer of G3.
2. The display position of the lower hierarchy logic of G3 is different from that of the upper hierarchy logic diagram, and there is a problem that it becomes difficult to associate each part of the upper hierarchy M logic diagram with the lower hierarchy logic diagram. Therefore, in this example, by providing the lower layer logical display area size 26 of each logical block in the library of G1, G2, and G3, when adding 02 to the upper layer logical diagram 21, G1, The display size of each upper layer of G2 and G3 can be retrieved in the minimum time, and the upper layer logic diagram 2
When incorporating 02 into 1, check the overlap between G1 and G2, G1 and G3, and G2 and G3, including the wiring display area, and complete the display arrangement of G1, G2, and G3 shown in the upper layer logic diagram 22. By expanding (, 1, 02, G3 into the lower hierarchy logic), the correspondence between each part of the upper hierarchy Fit! 191 logic diagram 22 and the lower hierarchy logic diagram 27 is facilitated.

Here, to confirm the conventional input control method again with reference to Figure 5, in the conventional input method, first input the logic diagram of OA, 08, create the OA library and the 0-day library, and at the same time Register the size of display area 13.14 of OA and QB in size 12.15, then input the logic diagram of G, create G library, and display size of G display area 9.
A method was adopted in which the size of the image was stored in the size 11. Here, since the display size 11 does not have the size of the display area 10 when displaying OA and CB, as shown in FIG.
2, the circuit diagram of logic diagram 19 is obtained,
As shown in the upper layer logic diagram 22 of FIG. 2, Gl, 02,
Since overlap occurs between the lower layer display areas 23, 24, and 25 of G3, it becomes difficult to associate each part between the upper layer 1'ii logic diagram 22 and the lower layer logic diagram 27. This problem occurs when adding a new logical block when creating an upper-level logical diagram. In the conventional library system shown in Figure 5, the troublesome processing procedure can be solved by changing the display position of the logical block and creating an empty area to add new logical blocks. This was difficult to achieve in terms of responsiveness.

FIG. 7 shows a processing procedure for checking the lower layer display area size of each logical block when adding a new logical block when creating an upper layer logical diagram. When adding a new logical block, first check whether there is a logical block already displayed, and if there is no displayed logical block, add it to an arbitrary position, but if there is a displayed logical block reads the library of the logical block to be added, extracts the number of logical elements that constitute the lower level TrI logic of the logical block, and if there is no lower level, that is, the logical block is composed of a single logical element,
A method is used in which the display size of the logic block is extracted as the lower layer logic display size and a new logic block is added without duplication in the logic diagram displaying the wiring. If the newly added logic block has a lower hierarchy, it is necessary to read all the libraries that display the logical elements of the lower hierarchy in order to display all applicable logical elements, and to display all of those logical elements. Add a new logic block by extracting the display area, moving the displayed logic block according to the area size required to display the wiring, and creating an empty area for the lower layer display area of the additional logic block. . If displayed logical blocks exist, before performing the above processing, read the libraries of all displayed logical blocks and read the libraries of all logical elements that constitute the lower layer logic of each logical block. The process reads the data and extracts the display size of each logical element.

According to this embodiment, in order to extract the display size of the lower hierarchy of the logical block in the minimum time, as shown in FIG.
The inside of the library of 0AS08 is 12.15.
The size of the display areas 13 and 14 of A and CB is stored, and at the same time, the display area size of G, which is composed of OA and QB, is determined from the calculated value of the wiring area 20, and when creating the upper layer logic diagram 8. When adding G, the size of the lower layer display area 10 of G is stored in the display size 11 of the G library.

As a result, as shown in Figure 4, when creating an upper layer logic diagram, the display size of the lower layer logic can be retrieved simply by reading the library of logic blocks in the upper layer, and the interval between each logical block can be adjusted. Checking the display size of lower layer logic can be realized in the minimum amount of time.

In the above, when inputting a hierarchical structure type logic diagram to any processing device, when inputting an upper hierarchy logic diagram, the check based on the display size of the lower hierarchy logic between each logic block is omitted, and the upper hierarchy N is freely input. Even when developing a logic diagram into a lower-level logic diagram, the display size when a logic block is expanded into a lower-level logic diagram can be easily derived.
The expansion process can be sped up.

Although the present invention has been illustrated above, the above-mentioned example can be further modified based on the technical idea of the present invention.

6. Effects of the Invention As described above, the present invention stores the display size of the lower hierarchy in the information storage area of the upper hierarchy logical block and checks the interval between the upper hierarchy logic blocks, so the additional The lower hierarchy display size of the logic can be placed in a predetermined position in a short time and developed into N lower logics, and the correspondence between the upper and lower hierarchy logics can be facilitated.

[Brief explanation of the drawing]

The drawings are for explaining the present invention, and FIG. 1 is a block diagram showing an input control method of hierarchically structured logic according to an embodiment, and FIG. 2 is a block diagram of the upper and lower floors Ii! A block diagram showing logical relationships. Figure 3 is a processing chart when creating a logic diagram. Figure 4 is a
5 is a block diagram showing a conventional hierarchical structure logic input control method, FIG. 6 is a schematic diagram when upper N logic blocks are added, and FIG. 7 is a flow diagram thereof. In addition, in the symbols shown in the drawings, 8.21.22... Upper layer logic diagram 11
．． 12.15...Display size 13.14
．． 23.24.25 ・・・・・・Lower hierarchy logical display area 16.27
......Lower hierarchy logic diagram 26...
・Lower layer display area size G1, G2, G3, OA
, 0 days......It is a logical element.

Claims (1)

[Claims] 1. When inputting a hierarchical structure type logic constructed by combining logic blocks having a single logic element or a combination thereof as a lower hierarchy, input the combination of logic elements in the logic block as a lower hierarchy. , and in an input control method for hierarchically structured logic in which a combination of the logical blocks is input as an upper layer, a display size for displaying a lower layer of the logic block in an information storage area for displaying the logic block of the upper layer is set. An input control method for hierarchically structured logic, characterized in that the interval between each logical block at the time of inputting the logical block is checked based on the display size at the time of displaying a lower hierarchy of each logical block.