JPS63114403A - Frequency synthesizer - Google Patents

Abstract

PURPOSE:To obtain a low frequency signal for a long period also at the time of reception by adopting return marks so as to read out waveform data written in a memory repeatedly. CONSTITUTION:Waveform data stored in memories B16, C17 are read out and outputted from respective start address positions by a reading clock. The lower 3 bits of the address are obtained by switching an address counted by an 8-bit data line of a memory D18 by a sequential multiplexer 19, the upper 15 bits are adopted as the address of the memory D18 and a return mark is retrieved by both the lower 3 bits and the upper 15 bits. The return mark is formed on a position preceded by one address from the start of the repeat of the waveform data, and at the time of detecting the return mark, address return command signal is inputted to an address controller 15 and the controller 15 returns all addresses in the memories B16-D18 to the start address. Thus, the continuous frequency waveform can be obtained by repeating said operation and reading out the same waveform in the same memory.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a frequency synthesizer having means for modulating a high frequency signal based on a low frequency signal written in advance in a memory to obtain a high frequency signal with desired sideband waves. .

(Prior art) MRI equipment (magnetic resonance equipment) uses a linear magnetic field gradient in the static magnetic field to give a magnetic field with different strength depending on the position, and the Larmor frequency of the system changes depending on the strength of raij!1. Tomographic images at different positions are obtained by changing a certain resonance frequency. Therefore, many high-frequency signals with different frequencies are required, and a frequency synthesizer is used as a high-frequency power source.

The following specifications are required for frequency synthesizers used in MRI apparatuses.

(1) Oscillate the frequency stably and variable within a certain range.

(2) Amplitude modulation can be performed to obtain an excitation signal.

(3) The relative phase of temporally oscillating signals can be controlled.

A frequency synthesizer shown in FIG. 6 is a device that satisfies the above requirements. In the figure, 1 is a frequency synthesizer for transmission to apply a high-frequency magnetic field to the subject, and it outputs the center frequency of a high-frequency signal.
``In the phase shifter 2, it is separated into sinωt and COSωt. 3 is a waveform memory (A) that stores the waveform of low frequency A (t) sin pt in the form of a digital signal.
, 4 is a waveform memory (B
), the output of waveform memory (A) 3 is A (t ) Si
n Dt is stored in the waveform memory (B) 4 in the DA converter 5.
A(t) cos pt of the output is converted into an analog signal in the DA converter 6, respectively. sinωt of the output of the 90” phase shifter 2 is equal to A(t
) sinpt in the multiplier 7, and similarly, the output of the 90° phase shifter 2, COSωt, is modulated in the multiplier 8 by the output of the DA converter 6, A(t)CO3pt. The outputs of multiplier 7 and multiplier 8 are added by adder 9 to output a lower sideband (LSB) signal as shown in the following equation.

sin ωt −A (t )'sin pt+cos
ωt −, A(t)cos pt÷A(t)co
s(ω-p)t Since MRI equipment requires many high-frequency signals with different frequencies, a waveform memory (RAM) is required.
A > 3 and the waveform memory (B) 4 contains A that is sent from the upper control unit (not shown) every time the MRI apparatus scans.
(t) sin pt and A (t) cos p
A waveform called t is downloaded.

(Problems to be Solved by the Invention) However, the device described above is designed to be used only when transmitting MRI. 90° pulse or 180° when transmitting
Since it is only necessary to transmit pulses of a limited length such as pulses, a waveform of a length that meets the requirements is downloaded from the CPU to the waveform memory (A) 3 and waveform memory (B) 4 for each scan. are doing. Therefore, it cannot be used when receiving signals that require a long time. For this reason, the frequency synthesizer used for signal demodulation during reception requires a separately expensive purchased product to be incorporated into the frequency synthesizer, which is uneconomical.

The present invention has been made in view of the above points, and its purpose is to generate high-frequency signals for demodulation by using signals in a waveform memory when receiving MHI, without using an independent and expensive frequency synthesizer. The object of this invention is to realize a frequency synthesizer that can be used as a power source.

(Means for Solving the Problems) The present invention solves the above problems in a frequency synthesizer having means for modulating a high frequency signal with a low frequency signal written in a memory to obtain a high frequency signal with a desired sideband. , at least one storage means in which the minimum mother waveform data of each frequency of the low frequency signal of the required frequency type is written in advance; and the storage means for generating a readout signal according to a frequency setting signal. means for reading out waveform data from the waveform data; means for counting the addresses of the waveform data of each frequency to generate an address return mark at the end of the waveform; and means for reading out the waveform data of each frequency from the start address using the address return mark. The apparatus is characterized in that it includes repeating means and outputs a continuous waveform high frequency signal.

(Operation) A start address corresponding to the frequency of the waveform written in the memory is output in response to the frequency setting signal, and the waveform data in the memory is read out from the position of the start address by the reading means. At the end of the address length of the waveform data determined by the frequency, the address detection means detects the end position and generates an address return mark, returns the readout position of the waveform data in the memory to the start address position, and continues the readout. outputs a low-frequency waveform, modulates the high-frequency signal, and outputs a sideband signal.

(Example) Hereinafter, an example of the present invention will be described in detail with reference to the drawings.

FIG. 1 is a block diagram of an embodiment of the present invention. In the figure, the same parts as in FIG. 6 are given the same reference numerals. 11 is a register (A) into which the value of the necessary transmission frequency is written by a frequency setting signal; 12 is a μPU (microprocessor unit) which outputs a table reference signal to memory (A) 13 in accordance with the frequency setting signal of the register (A>);
The memory (A) 13 is a program table in which the start address of each frequency, which is written in a waveform memory to be described later, is written in correspondence with the frequency. 14 is memory (A
) is the register (B
), an interrupt is generated to the address controller 15 at the same time. The address controller 15 has an 18-bit internal counter and sets the start address.

16 is the low frequency sin pt waveform from 200H2 to 2
Memory written up to 40KHz every 00Hz (
B), 17 is the low frequency (7) COS pt waveform of 200
Memory (C), 18 is memory (8) '16. where data is written from Hz to 40KH2 every 2゜OHz. memory(
C) Memory (D) in which the address return mark of the waveform data of each frequency written in 17 is written.
It is. The output of memory (D) 18 is sent to multiplexer 19
is selected, outputs a return mark, and inputs the return mark to the address controller 5. 20 and 21 are the sin pt of the output of memory (B) 16 and memory (C)
22 is a signal source for amplitude modulating the SOB output from the adder 9; MRI with amplitude modulation of SSB signal
Provides an RF signal to the device.

Next, the operation of the embodiment configured as described above will be explained.

First, the purpose and principle of this circuit will be explained.

As an example, it is assumed that the frequency synthesizer according to this embodiment is configured with the following requirements. That is, the output frequency is ω ±40kHz2 (however, ω is the center □ high frequency frequency)
, frequency interval 200Hz, memory (B) 16. memory(
C) The read interval of 17 is 2.5 μs. Since it is also used as a receiving synthesizer, the output is kept at a for a relatively long time.
Also, to save memory,
The waveform data written for each frequency (200 types up to 40 kHz every 200 Hz) is up to one point before the repetition point of the waveform for each frequency. The bond outputs a continuous wave by repeating the same waveform.

The configuration of the waveform data written in the memory (B) 16 is as explained below.
Records low frequency signal of 0kHz, readout is 2.5μs
This is done every time. Prepare the waveform data until you reach the repetition point.

The number of data (address length) for each frequency is as shown in FIG. In the figure, when the low frequency signal is 200 Hz, the period is 5 ms and the clock is 2.
Since it is 5 μs, the repeat time is 5 ms, which is the least common multiple, and the address length is 5 ms/2.5 μ5=2000. In this way, the address length is determined. Therefore, as shown in the figure, for example, 200Hz, 400Hz, 40kHz
is 1 period, 600Hz4; t3 period, 39.8k
For Hz, 199 cycles of data are input and output. The resolution of each data is 8 bits, and the address is 18 bits.

The data (with 8-bit deep resolution) is a function of sin and COS as shown in FIG. The data output to the memory is expressed as polarity with the most significant bit as +” as 1 and ’- as the polarity.
” is O, so the data is expressed in 7 bits,
These are numbers in the form of -128 to +127. This data is obtained using the following formula.

sin [(360 degrees You just need to repeat it. For this reason, a return mark is provided one address before the start address of each frequency plus the address length, and after the return mark, the waveform is repeated from the start address and continues. For example, in FIG. 3, when the frequency is 200 Hz, the start address is O, and the return mark is 1999. When the frequency is 400 Hz, the start address is 20001 and the return mark is 2999. Since the address return mark can be represented by 1-bit data, the following measures are taken to save memory space.

FIG. 4(A) is a diagram showing the location where the address return mark (D>18) is written in the memory, and FIG. 4(B) is a connection diagram of the multiplexer 19.The memory (D) 18 used for the address return mark is shown in FIG. uses the same 8-bit memory as memory (B) 16 and memory (C) 17.The data depth of the memory is 8 bits, so as shown in the figure (a), the lower 3 bits of the address are used as the data depth. It is assigned to each position of 8 bits, and together with the remaining 15 bits, it becomes an address, and the data is updated with 15 bits.In other words, when it advances from 0 to 7, 1 of 15 bits advances, and (a) the horizontal axis of the figure The eight data in (B) are connected to the multiplexer 19 in the figure.-
Input to 8 data lines of 08. multiplexer 19
is a switch that has 8 input terminals D to D8 and one output terminal, and sequentially switches with the input of the lower 3 bits, and when an address return mark is input to the input terminal, an address return mark is input to the output terminal. Output.

Memory (B) configured as above 16. Memory (C
)17. The operation of this embodiment having the memory (D) 18 will be explained. A frequency setting signal is written into the register (A) 11 by input from the outside. At the same time, an interrupt occurs in μPC12. This interrupt also occurs for a setting signal that is the same as a frequency setting signal that has already been written, and initializes the phase of the generated frequency signal. μ that received an interrupt
The PC 12 refers to the program table in the memory (A) 13 for the frequency of the setting signal, and writes the start address determined for that frequency into the register (8) 14. At the same time, an interrupt is generated in the address controller 15.

The address controller 15 reads the start address from the register (B) 14 and sets it in the internal counter,
Memory (B) 16. Memory <C> 17, memory (D) 1
8 as an address. The sine data shown in FIG. 3 is written in the memory (B) 16, and the COS data shown in FIG. 3 is written in the memory (C) 17. The internal counter of the address controller 15 operates at a constant cycle (2.5μ
It starts updating at S) and outputs a read clock with a cycle of 2.5 μs. The memory (B) 16 and the memory (C) 17 read out the stored waveform data from the start address position in response to the read clock and output it. As mentioned above, the lower 3 bits of the address are stored in the memory (D) 18.
The addresses counted in the 8-bit data line are sequentially switched by the multiplexer 19, and the upper 15 bits are used as the address of the memory (D) 18 to search for the return mark. The return mark is provided one address before the repetition of waveform data starts, and when this is detected, it is input to the address controller 15 as an address return command signal, and the address controller 15 sends the memory (B) 16. Memory (C)17. Memory (D) 1
Return all 8 addresses to the start address. By repeating this and reading out the same waveform from the same memory, a continuous frequency waveform is obtained.

Memory (B) 16. Frequency data is written into the memory (C) 17 for the number of cycles determined by the address read cycle. This state is expressed in analog form as shown in FIG. In the figure, addresses 0 to 2000 are 2
00Hz waveform, addresses 2000-3000 are 400
The Hz waveform, 3000 to 5000 is the 600)-IZ waveform.

The waveforms synthesized in this way are input to the data selector 20.21 as sin pt from the memory (B) 16 and cos pt from the memory (C) 17. Data selector 20.21 is μ PtJ1 based on the frequency setting signal.
The output sides of sin pt and cos pt are determined based on the signals from 2, and the outputs are input to DA converters 5 and 6. The operation from the DA converter 5.6 to the adder 9 is as follows.
Since it is the same as the figure, it is omitted. The SSB signal output from the adder 9 is converted into the signal A from the amplitude modulation signal source 22 in the multiplier 23.
(t), and A(t)cos(ω(,-
p) t or A(t ) sin (ωo +l)
) output to the MRIB as t.

As explained above, since the method uses a return mark to repeatedly read out the waveform data written in the memory, it has the following advantages.

(1) It can continuously generate the same frequency for a long time, and can be used for reception that needs to last about 10 times as long as transmission, and only one high-frequency power source outputs the center frequency.
Just a stand.

(2) Conventionally, amplitude information is also written in the waveform memory, and different information is required for each scan, which requires time to set up before scanning, but in this example, the amplitude is modulated with an analog signal. This eliminates the need for setup as a synthesizer.

(3) In order to achieve the same purpose, the data to be written to the memory should be only one cycle of the low frequency signal, and the readout cycle should be made variable, or the output data may be searched by itself without using a return mark (for example, the same One possible method is to detect a state in which data continues) to find a repetition point and return the address, but compared to these methods, this method can be implemented with a relatively small hardware configuration.

Note that the present invention is not limited to the above embodiments.

For example, the memory into which waveform data is written may be 1 gA. In that case, a data selector and an adder,
A 90° phase shifter is no longer necessary, and only one OA converter 9 multiplier is required, but a filter for separating LJSB and 188 is required. Also, memory (B) 16. Memory (C) 17
．． The memory (CD) 18 may be either ROM or RAM.

(Effects of the Invention) As explained in detail above, according to the present invention, it is possible to obtain a long-time low frequency signal even during reception, and one synthesizer (fixed frequency high frequency power supply) is used for both transmission and reception. It is now possible to operate economically, which has great practical effects.

[Brief explanation of the drawing]

Fig. 1 is a block diagram of an II configuration according to an embodiment of the present invention. Fig. 2 is a diagram showing the address length of a low frequency signal written in memory. Fig. 3 is a diagram showing memory (B) 16° memory (C). 17
4 is an explanatory diagram of the return mark, (a) is a diagram of the return mark written in the memory (D) 18, (b) is an explanatory diagram of the operation of the multiplexer, and FIG. 5 is an explanatory diagram showing an analog representation of the sin pt waveform data written in the memory <8) 16, and FIG. 6 is a diagram of a conventional frequency synthesizer. 1... High frequency power supply 2... 90° phase shifter 3.
... Waveform memory <A) 4... Waveform memory (B) 5.
6... OA converter 7,8.23... Multiplier 9.
... Adder 11 ... Register (A) 12
...μPU 13...Memory (A) (program table) 14.
...Register (B) 15...Address controller 16...Memory (B) (waveform data) 17...Memory (C) (waveform data) 18...Memory (D) (address return mark) 19 ...Multiplexer 20.21...Data selector 22...Amplitude modulation signal source Patent applicant Yokogawa Medical Systems Co., Ltd. Fig. 2 Fig. 3 Fig. 6

Claims (1)

[Claims] In a frequency synthesizer having means for modulating a high frequency signal with a low frequency signal written in a memory to obtain a high frequency signal with a desired sideband, a minimum amount of each frequency of the low frequency signal of a required frequency type in advance. at least one storage means in which waveform data of each frequency is written; means for generating a readout signal based on a frequency setting signal to read out the waveform data from the storage means; A frequency signal which outputs a continuous waveform high-frequency signal, comprising means for generating an address return mark at the end, and means for repeating reading from the start address of the waveform data of each frequency using the address return mark. synthesizer.