JPS63114305A - Frequency multiplier - Google Patents

Abstract

PURPOSE:To prevent multiplication efficiency from being lowered even with a small input power by connecting a drain of a GaAs field effect transistor (TR) FET to ground and adjusting the size, shape of the input circuit provided to a gate size and the arrangement of a fundamental wave trap provided to the source. CONSTITUTION:A fundamental wave trap 13 reflecting entirely the fundamental wave is connected to the source S of the FET 12 and it is arranged at a position maximizing the input reflection coefficient, the size and shape of the input circuit 11 are adjusted so as not to oscillate the FET 12, part of the reflected power is reflected in the gate in the input circuit 11 to increase the input power. Thus, even with a small input power, the multiplier whose multiplication efficiency is not decreased is obtained.

Description

[Detailed Description of the Invention] [Summary] In a frequency multiplier, the drain of a GaAs FET is grounded, and the dimensions and shape of the input circuit provided on the gate side and the placement position of the fundamental wave trap provided on the source side are adjusted. Therefore, the fundamental wave component appearing on the output side is fed back to the input end and multiplied again, thereby preventing the multiplication efficiency from decreasing even when the input power is small.

[Industrial application field]

The present invention relates to an improvement of a frequency multiplier used in a microwave band using a frequency multiplier 5 such as a GaAs FET.

Diodes have conventionally been used as nonlinear elements in frequency multipliers used in microwave bands with frequencies of about 3 to 12 GHz. However, diodes have drawbacks such as poor operation stability and multiplication efficiency, so recently GaAs FE
Although the above drawbacks have been improved by using T (hereinafter abbreviated as FET), it is desired that the multiplication efficiency does not decrease even when the input power is low.

[Conventional technology]

FIG. 5 is a block diagram of a conventional example, and the dotted line portion in FIG. 4 shows a multiplication characteristic diagram. The operation will be explained below using a doubler as an example.

First, a fundamental wave of frequency Br is applied via an input matching circuit composed of a circulator 1, a stub 2, and a transmission line 3 to a FET 4 whose source is grounded and whose gate bias voltage is set to Ov or near the pinch-off voltage.

Therefore, the fundamental wave component and the harmonic component are obtained on the output side depending on the nonlinear component of the FET, but the fundamental wave component and the harmonic wave component are generated by the fundamental wave L and the lamp, which are composed of the stub 6 with a length of λg/4 and the transmission line 5. The component is returned to the drain side and doubled again, and only the doubled wave component is extracted and outputted by an output matching circuit composed of a transmission line 7 and a stub 8.

The input matching circuit performs conjugate matching between the input side of the FET and the signal source at frequency f, and the output matching circuit performs conjugate matching at frequency 2f.
The output side of the FET and the load are conjugate matched. Further, 9 and 10 are a gate bias power supply and a drain power supply.

[Problem that the invention seeks to solve]

In the case of a common source, the necessary harmonic components are extracted from the distortion components of the flowing FET drain current by adding the fundamental wave, so when the fundamental wave power decreases, the FET becomes close to linear operation and doubles. The wave power becomes smaller.

In other words, efficient multiplication cannot be performed unless the input power is increased to a certain extent, and as the input power becomes smaller, as shown by the dotted line in Figure 4, the multiplication efficiency (2i! harmonic power/fundamental zero wave power) decreases. There is a problem.

[Means for solving problems]

The above-mentioned problems are solved by the frequency multiplier circuit shown in the block diagram of the principle of the present invention shown in FIG.

11 is a field effect transistor 1 whose drain D is grounded.
2 is an input circuit connected to the gate G, and 13 is a fundamental wave trap connected to the source S that totally reflects the fundamental wave.

The fundamental wave trap was placed at a position where the input reflection coefficient was maximized, and the dimensions and shape of the input circuit were adjusted so that the field effect transistor would not oscillate.

[Effect]

In the present invention, the reflected power P2 of the fundamental wave can be made larger than the input power P1 by grounding the drain of the FET 12 and adjusting the distance between the source and the fundamental wave trap 13. Therefore, a part of this reflected power P2 is transferred to the input circuit 1.
1 to increase the input power by reflecting it to the gate side. A more detailed explanation of this is provided below.

As is well known, in the case of a FET with a grounded drain, the Smith chart of the output reflection coefficient rL and the locus of l' in where the absolute value of the input reflection coefficient r' in is 1 (referred to as a stability circle) are As shown in the figure (bl), the two circles intersect.

On the other hand, when the source is grounded, the Smith chart circle and the stable circle may or may not intersect depending on the characteristics of the FET.

Therefore, if the latter is required, it is necessary to select an FET.

Incidentally, on the circumference of the Smith chart, lr Ll = 1.

On the circumference of the stable circle, l[' 1nl= 1, inside the circle, lr
inl> 1, outer circle lr'inl< i te,
The reflection coefficient r is Pz/P+t? As shown, FLl
rln is the reflection coefficient at a point as shown in FIG. 2(a).

Now, in the case of a multiplication operation, considering the fundamental frequency, it is totally reflected by the fundamental wave trap, so it becomes lr'tl-t (on the circumference of the Smith chart).

However, as mentioned above, since FLl is 1, tri is placed at circumferential part A of the Smith chart, which is inside the stability circle.
There are places where the nr maximum value is the maximum value.

Next, since the input circuit consists of a stub with a length of 11 and a transmission line with a length of l□, if the reflection coefficient when looking from the gate to the signal source side is F, then the oscillation condition is lr wing r'in%-1
... (1) LF3 +, 4r' i n = 2
nπ...(2) Here, n=0. ±1. ±2·, i8. Otr'in indicates the phase of rS+Fln.

Now, lr tnl> 1, so ll+1! , depending on how you choose 2, there is a possibility that equations (11 and (2) will be satisfied), but to avoid this, either use 11 to avoid satisfying condition (1), or use 12 to satisfy equation (2). All you have to do is make sure that the conditions are not satisfied.

However, if r is too small, the input power p will be small and the improvement in multiplication efficiency will be small, so the actual r's(
That is, l and 22) are determined experimentally based on the balance between the multiplication efficiency and stability of the multiplier.

That is, since the drain of the FET is grounded to utilize the nonlinearity of the FET and the input circuit and fundamental wave trap are adjusted to increase the actual input power, the multiplication efficiency does not decrease even when the input power is small.

〔Example〕

FIG. 3 shows a block diagram of an embodiment of the present invention. Note that the same reference numerals refer to the same objects throughout the plan. below.

This will be explained as a doubler with reference to FIG.

The input circuit, output matching circuit, and fundamental wave trap are composed of microstrip lines, and in particular, the fundamental wave trap 13 is realized by an open stub 132 of λg/4.
For the double wave, it is λg/2 and there is no effect of the open stub.

In addition, 112.131. 7 is a transmission path, 111.8 is a stub, and l is a circulator. Also, since both package type and chip type FETs have a structure in which the source is grounded, the drain cannot be grounded as it is, so a negative voltage is applied to the bias power supply 14 and 15 to operate it as a reverse channel type drain grounded. There is.

Next, the solid line in FIG. 4 shows the multiplication characteristics of the present invention, and the multiplication efficiency is improved in the portion where the input power is small.

〔Effect of the invention〕

As described in detail above, according to the present invention, there is an advantage that a multiplier can be obtained in which the multiplication efficiency does not decrease even when the input power is small.

[Brief explanation of the drawing]

Figure 1 is a block diagram of the principle of the present invention. Figure 2 is an explanatory diagram of the operation of Figure 1. Figure 3 is a configuration diagram of an embodiment of the present invention. Figure 4 is a multiplication characteristic diagram. Figure 5 is a diagram of the conventional example. A configuration diagram is shown. In the figure, 11 is an input circuit, 12 is a field effect transistor, and 13 is a fundamental wave trap. The present invention's 潴,'(ripro-nof diagram Figure 1: : r''s mouth II The movement of Figure 1 'F', B Figure Figure 2 Figure N'nucleus μL and 2. n゛ha detour 11, one talented job tC-IO-
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Claims (1)

[Claims] Field effect transistor (12) whose drain D is grounded
The input circuit (11) is connected to the gate G of . A frequency multiplier, characterized in that the size and shape of the input circuit are such that the field effect transistor does not oscillate.