JPS63113962U - - Google Patents
Info
- Publication number
- JPS63113962U JPS63113962U JP1987005392U JP539287U JPS63113962U JP S63113962 U JPS63113962 U JP S63113962U JP 1987005392 U JP1987005392 U JP 1987005392U JP 539287 U JP539287 U JP 539287U JP S63113962 U JPS63113962 U JP S63113962U
- Authority
- JP
- Japan
- Prior art keywords
- board
- hole
- check terminal
- utility
- registration request
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 230000009191 jumping Effects 0.000 claims 1
- 239000000758 substrate Substances 0.000 description 1
Description
第１図は本考案の一実施例の電子回路のチエツ
ク端子を設けた実装基板の斜視図、第２図は従来
のチエツク端子を設けた実装基板の斜視図である
。 ５……基板、７……孔、８……ジヤンパーリー
ド。
ク端子を設けた実装基板の斜視図、第２図は従来
のチエツク端子を設けた実装基板の斜視図である
。 ５……基板、７……孔、８……ジヤンパーリー
ド。
Claims (1)
- 電子部品を配設する基板に設けた孔と、この孔
の上方を飛越して略コ字形状に前記基板に配設し
たジヤンパーリードとからなる電子回路のチエツ
ク端子。
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1987005392U JPS63113962U (ja) | 1987-01-16 | 1987-01-16 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1987005392U JPS63113962U (ja) | 1987-01-16 | 1987-01-16 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS63113962U true JPS63113962U (ja) | 1988-07-22 |
Family
ID=30786935
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1987005392U Pending JPS63113962U (ja) | 1987-01-16 | 1987-01-16 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS63113962U (ja) |
-
1987
- 1987-01-16 JP JP1987005392U patent/JPS63113962U/ja active Pending