JPS63111636A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To improve a good product yield thereby to reduce a manufacturing cost of a semiconductor device by providing the step of removing an improper part by a performance inspection after at least one step of first, second or third connecting and securing steps in the semiconductor of the device. CONSTITUTION:The function of an LSI chip 1 electrically connected by 'connecting and securing steps (C)', and a first circuit substrate 3 is simultaneously secured to the chip 1. Then, since a subsystem can be removed from a salient electrode 4b formed on the substrate 3, if a probe 10 connected to an electric characteristic measuring unit is connected to the electrode 4b in 'performance inspecting and improper LSI chip removing steps (D)', the measuring unit can inspect the performance of the subsystem. If the result of the inspection is allowed, it is advanced to next step. If the performance of the subsystem does not satisfy the allowed reference, the chip 1 due to the cause is identified and removed. Thus, the performance is inspected after at least one step of the connecting and securing steps to remove the improper part generated in the midway step by the midway step to be recovered, thereby improving the good product yield.

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial Application Field] The present invention relates to a method of manufacturing a semiconductor device using a so-called three-dimensional mounting multi-chip packaging technique in which a large number of semiconductor chips are assembled into one package.

[Conventional technology]

Conventionally, semiconductor devices have been assembled by plane-mounting semiconductor chips (hereinafter referred to as LSI chips) on a first wiring board, stacking them on a second wiring board using connectors, and mounting them in a package. Ta.

Figure 3 is a schematic diagram showing the manufacturing process flow of a method for manufacturing a semiconductor device using conventional three-dimensional mounting multi-chip packaging technology, and Figures 4 (a) to (h) show the manufacturing process shown in Figure 3. It is a figure for concretely explaining.

In Fig. 3, (AA) has performance elements consisting of PN junctions and wiring connecting these active elements, and electrodes are placed on the main surface of an LSI chip as a plurality of semiconductor chips with active and passive functions. In the electrode formation step (BB), the LSI chip is formed on the main surface of the first wiring board on which the LSI chip is mounted.
The wiring/electrode formation process (CC) involves forming wiring and electrodes that connect, combine, and transmit the functions of the chip.
The SI chip is electrically and mechanically connected to the first wiring board.

The first connection/fixing step (00) is a process of connecting, combining, and transmitting the functions of the first wiring boards to the main surface of the second wiring board on which a plurality of first wiring boards are mounted. The wiring/electrode forming step for forming electrodes (EE) involves bonding the electrodes of the first wiring board and the electrodes of the second wiring board, and electrically and mechanically connecting the first wiring board to the second wiring board. Second connection/fixing process to fix, (FF) is LSI chip, 1st I\! The second wiring board on which the wire board is mounted is fixed to the insulating board.

The third connection/fixing process (GG) for arranging and connecting the functions of the second wiring board is a performance inspection process for the insulating board on which the second wiring board is mounted. It is characterized by seven types of processes.

In addition, in FIGS. 4(a) to (h), 1 is a large number of L
An SI chip, 2a is an electrode formed on the main surface of the LSI chip 1, 3 is a first wiring board, 4a and 4b are protruding electrodes formed on the main surface of the first wiring board 3, and the protruding electrode 4a
, 4b are arranged on the same main surface! ! (not shown) and are electrically connected to each other. 5 is a second wiring board, 6a,
6b is a protruding electrode formed on the main surface of the second wiring board 5, and the protruding electrodes 6a and 6b are electrically connected to each other by wiring (not shown) formed on the same main surface. 6C is an electrode formed by joining the protruding electrode 4b and the protruding electrode 6a. 7 is the LSI chip 1. Said first wiring board 3. an insulating substrate 8a that accommodates the second wiring board 5;
, 8b are electrodes formed on the insulating substrate 7, and the electrodes 8b serve as external bins for extracting the functions of this semiconductor device to the outside. The electrodes 8a and 8b are electrically connected to each other through wiring (not shown) formed on the insulating substrate 7. 9 electrically connects the protruding electrode 6b and the electrode 8a, for example, Au.
wire.

Next, the manufacturing process will be explained.

The PN junctions formed on the main surface of the LSI chip 1 are interconnected by wiring (not shown), and the electrical function of the PN junction can be taken out from any position on the same plane as the main surface. Therefore, as shown in FIG. 4(a), if an electrode 2a is formed in the r-electrode forming step (AA)J, the electrical function of the LSI chip 1 can be extracted to the outside through the electrode 2a.

Next, as shown in FIG.
B) By forming the protruding electrodes 4a and 4b using J, electrodes and wiring for connecting, combining, and transmitting the electrical functions of a plurality of LSI chips 1 can be formed.

Next, as shown in FIG. 4(C), the F connection fist fixing step (
When heat treatment is performed by arranging the main surface of the first wiring board 3 and the main surface of the LSI chip 1 parallel to each other using GC)j, the electrode 2a located in the gap and the protruding electrode 4a are bonded and the LS
The functions of the I-chip 1 can be electrically connected, and at the same time, the LSI chip 1 can be fixed to the first wiring board 3. The individual functions of the LSI chips 1 mounted thereon are connected and combined with each other by wiring (not shown) formed on the main surface of the first wiring board 3, so that the functions ( subsystems) can be configured.

Next, a fourth wiring board is mounted on the second wiring board 5 on which the first wiring board 3 is mounted.
As shown in figure (d), r wiring/electrode formation process (DD)
By forming the protruding electrodes 6a and 6b with J, the electrical functions of the plurality of first wiring boards 3 can be connected, combined,
Transmitting electrodes and wiring can be formed.

Next, as shown in FIG. 4(e), the r connection and fixing process (
EE) When the main surface of the first wiring board 3 and the main surface of the second wiring board 5 are arranged perpendicularly by J, the protruding electrodes 4b and the protruding electrodes 6a come into contact with each other.
b and 6a are joined to form an electrode 6C. And electrode 6
C allows the first wiring board 3 and the second wiring board 5 to be electrically connected and mechanically fixed. Then, the second wiring board 5
Since the individual functions (subsystems) of the first wiring boards 3 mounted thereon are connected and combined by wiring (not shown) formed on the main surface of the Functions are configured. In this way, all the subsystems of the first wiring board 3, that is, all the individual functions of the LSI chip 1 housed in this semiconductor device, are mounted on the second wiring board 5 and configured in a combined manner.

Next, as shown in FIG. 4(f), the r-connected fist fixing step (
FF) to attach the second wiring board 5 to the insulating board 7 using adhesive (
(not shown), the protruding electrode 6b formed on the second wiring board 5 and the electrode 8 formed on the insulating substrate 7
A is electrically connected with an Au wire 9. Since the electrode 8a is connected to the electrode 8b, which is an external bin for extracting the functions of this semiconductor device to the outside, all the functions of the second wiring board 5 can be extracted from the electrode 8b. In the end, LSI chip 1. First wiring board 3. Second wiring board5. Au wire9. All functional connections of the semiconductor device are completed through the electrode 8b.

Finally, as shown in Figure 4(g), the r performance inspection step (
CG) Conduct performance inspections (electrical, mechanical performance, etc.) of semiconductor devices after all functions of the semiconductor device have been connected at J. Since the inspection selects devices whose performance exceeds a certain standard, semiconductor devices with the intended functions and performance can be obtained at the same time as they are completed.

In addition, LSI chip 1 is installed in r connection/fixing process (FF) J.
．． First wiring board 3. Second wiring board5. This feature is not damaged during normal handling, since the process includes attaching a lid (not shown) that physically and chemically protects the Au wire 9.

[Problem that the invention seeks to solve]

In the conventional semiconductor device manufacturing method as described above, the performance of the semiconductor device is checked almost at the final stage of the entire manufacturing process, just before completion, so even if a phenomenon that causes performance failure occurs in the previous process, ( For example, poor bonding between electrodes as shown in FIG. 4(h)) and poor performance could not be recognized, so the manufacturing work had to be continued. In this case, the material costs and processing costs spent on manufacturing semiconductor devices with poor performance (defective products) are added to the price of semiconductor devices with good performance (defective products), so the rate of occurrence of defective products in the manufacturing process is high. The lower the yield of good products, the higher the price. Therefore, in order to manufacture low-cost semiconductor devices, it is necessary to increase the yield of non-defective products, but in conventional manufacturing methods, performance inspection is performed immediately before the completion of manufacturing, so the performance Because it was not possible to detect defects and increase the yield of good products,
There was a problem in that it was not possible to manufacture low-cost semiconductor devices.

The present invention has been made to solve these problems, and an object of the present invention is to provide a method for manufacturing a semiconductor device that can reduce manufacturing costs by improving the yield of non-defective products.

[Means for solving problems]

The method for manufacturing a semiconductor device according to the present invention includes a performance test φ defective parts removal step in which a performance test is performed and defective parts are removed after at least one of the first, second, or third connection/fixing steps. It is something that

[Effect]

In this invention, defective parts are removed in the performance inspection/defective parts removal process.

〔Example〕

FIG. 1 is a schematic diagram showing the flow of the manufacturing process of the semiconductor device manufacturing method of the present invention, and FIGS. 2(a) to (i) are diagrams specifically explaining the manufacturing process shown in FIG. 1. It is.

In FIG. 1, (A) is an electrode formation process in which electrodes are formed on the main surfaces of a plurality of LSI chips having active and passive functions, which have active elements made of PN junctions and wiring connecting these active elements. , (B) connects the functions of the LSI chips to the main surface of the first wiring board on which the LSI chips are mounted,
Wiring/electrode forming process to form composite and transmitting wiring and electrodes, (C) is to join the electrodes of the LSI chip and the electrodes of the first wiring board, and to connect the LSI chip to the first wiring board electrically and mechanically. a first connection/fixation step of connecting and fixing;
(D) performs a performance test on the first wiring board on which an LSI chip is mounted, and as a result, removes the defective LSI chip found from the first wiring board.Performance test as a defective parts removal process. This is a chip removal process. (E) connects, combines, and connects the functions of the first wiring boards to the main surface of the second wiring board on which a plurality of first wiring boards are mounted;
(F) is a wiring electrode forming step for forming transmission wiring and protruding electrodes, in which the electrodes of the first wiring board and the electrodes of the second wiring board are joined, and the first wiring board is electrically connected to the second wiring board. A second connection/fixation process of mechanically connecting and fixing (
G) performs a performance test on the second wiring board on which the first wiring board is mounted, and as a result, removes the defective first wiring board found from the second wiring board as a performance test/defective parts removal process. φ defective first wiring board removal process, (H)
(I) is a third connection/fixing process in which the second wiring board on which the LSI chip and the first wiring board are mounted is fixed and arranged on an insulating board and the functions of the second wiring board are connected; A performance test is performed on the mounted insulating board, and as a result, a defective second wiring board found as a result is removed from the insulating board.Performance test as a defective parts removal process.A defective second wiring board removal process. The semiconductor device manufacturing method of the invention is characterized by nine types of steps.

In Figures 2(L) to (i), Figures 4(a) to (h)
The same reference numerals indicate the same parts, and 10 is a probe connected to an electrical property measuring device (not shown).

Next, the manufacturing process will be explained.

The PN junctions formed on the main surface of the LSI chip 1 are interconnected by wiring (not shown), and the electrical function of the PN junction can be taken out from any position on the same plane as the main surface. Therefore, as shown in FIG. 2(a), if an electrode 2a is formed in the r-electrode forming step (A)J, the electrical function of the LSI chip 1 can be extracted to the outside through the electrode 2a.

Next, as shown in FIG. 2(b), the first wiring board 3 on which the LSI chip 1 is mounted is subjected to a wiring/electrode forming step (B).
By forming the protruding electrodes 4a and 4b with J, the electrical functions of the plurality of LSI chips 1 can be connected, combined,
Transmitting electrodes and wiring can be formed.

Next, as shown in Figure 2 (C), the “connection/fixing process (
C)" between the main surface of the first wiring board 3 and the LSI chip 1.
When the main surfaces of the LSI chip 1 are arranged parallel to each other and heat treated, the electrode 2a located in the gap and the protruding electrode 4a are bonded and the functions of the LSI chip 1 are electrically connected, and at the same time, the LSI chip 1
can be fixed to the first wiring board 3. The individual functions of the LSI chips 1 mounted thereon are connected to each other by wiring (not shown) formed on the main surface of the first wiring board 3.
Since they are combined, it is possible to configure as many functions (subsystems) as there are LSI chips 1 mounted on them.

Next, since the subsystem can be taken out from the protruding electrode 4b formed on the first wiring board 3, as shown in FIG. By connecting the probe 1o connected to the electrical property measuring device, the performance of the subsystem can be inspected with the electrical property measuring device.If the result of this test is passed, the next step will proceed, but if the performance of the subsystem is When the LSI chip 1 does not meet the acceptance criteria, as shown in FIG. 2(e), the LSI chip 1 causing the problem is identified and removed.

Then, return to the r connection fist fixing process (C)J again, and place a good LSI chip 1 in the part where the defective LSI chip 1 was removed.
join. By repeating this process, a subsystem that satisfies the acceptance criteria can be configured on the first wiring board 3. In this way, defects that occurred before the performance inspection/defective LSI chip removal step (D)J can be detected and removed in this step.

Next, as shown in FIG. 2(f), the second wiring board 5 on which the first wiring board 3 is mounted is subjected to a wiring/electrode forming step (E).
By forming the protruding electrodes 6a and 6b using j, the electrical functions of the plurality of first wiring boards 3 can be connected, combined,
Transmitting electrodes and wiring can be formed.

Next, as shown in Figure 2 (g), the “connection/fixing process (
F) The main surface of the first wiring board 3 and the second wiring board 5 by J
When the main surfaces of are arranged vertically, the protruding electrode 4b and the protruding electrode 6
Since the two protruding electrodes 4 are in contact with each other, both protruding electrodes 4 are heated by heat treatment.
b and 6a are joined to form an electrode 6C. The first wiring board 3 and the second wiring board 5 can be electrically connected and mechanically fixed by this electrode 6C. The wiring (not shown) formed on the main surface of the second wiring board 5 connects and combines the individual subsystems of the first wiring board 3 mounted thereon. It is possible to configure as many functions as there are. In this way, all of the subsystems of the first wiring board 3, that is, all the individual functions of the LSI chip 1 housed in this semiconductor device, can be mounted on the second wiring board 5'2 and configured in a combined manner.

Next, since all the functions of the LSI chip 1 housed in this semiconductor device can be taken out from the protruding electrodes 6b formed on the second wiring board 5, the protruding electrodes 6b By connecting a probe 10 (not shown) connected to an electrical property measuring device, the performance can be inspected with the electrical property measuring device. If the inspection result passes, the next process will proceed. However, if the performance does not meet the acceptance criteria, the first wiring board 3 that is the cause is identified, as shown in Figure 2 (h). get rid of it. and,
Returning again to 1 connection/fixing step (F)J, a good first wiring board 3 is bonded to the portion from which the defective first wiring board 3 was removed. By repeating this process, it is possible to configure the second wiring board 5 with a function that satisfies the acceptance criteria. In this way, r
Performance Inspection φ Defective First Wiring Board Removal Step (G) Any defects that occurred before j can be detected and removed in this step.

Next, as shown in FIG. 2(i), the r connection dispute fixing step (
H) Apply adhesive (
After mechanically fixing the protruding electrode 6b formed on the second wiring board 5 for taking out a function and the electrode 8a formed on the insulating substrate 7, an Au wire 9 is used to electrically connect the protruding electrode 6b formed on the second wiring board 5. Since the electrode 8a is connected to the electrode 8b, which is an external bin for extracting the functions of this semiconductor device to the outside, all the functions of the second wiring board 5 can be extracted from the electrode 8b.

In the end, LSI chip 1. First wiring board 3, second wiring board 5. Au wire9. All functions of the semiconductor device are connected through the electrode 8b.

Next, since all the functions of the LSI chip 1 housed in this semiconductor device can be taken out from the electrodes 8b formed on the insulating substrate 7, the performance inspection/defective second wiring board removal step (I)J
If a probe 10 (not shown) connected to an electrical property measuring device is connected to the electrode 8b, the performance can be inspected with the electrical property measuring device. If the inspection result is passed, the process is completed, but if the performance does not meet the acceptance criteria, remove the second wiring board 5 that is causing the problem and repeat the process.
Return to the connection/fixing process (H)
Connect and fix. By repeating this process, it is possible to configure the insulating substrate 7 with a function that satisfies the acceptance criteria. In this way, the r performance inspection/defective second wiring board removal process (
G) Any defects that occurred before J can be detected and removed in this process. In this way, a semiconductor device having the intended function and performance can be obtained at the same time as it is completed.

Note that the LSI chip 1.
First wiring board 3. Second wiring board5. Since this includes the process of attaching a lid (not shown) that physically and chemically protects the Au wire 9 and the like, this function will not be damaged during normal handling.

Furthermore, if the result of the performance test in the performance test/defective parts removal step 1 is "pass", the subsequent removal process is of course unnecessary.

Furthermore, performance testing is not limited to electrical items, but also includes all mechanical and chemical items, including ``burn-in,'' which involves applying thermal and electrical stress prior to performance testing.

In addition, it is not necessary to carry out all of the above as the performance inspection/defective parts removal process J, but it is necessary to carry out all of the above for the non-defective LSI chip 1. Even if an rLSI chip performance inspection process J, an "insulation substrate performance inspection process", etc. are incorporated in order to supply the insulating substrate 7, the gist of the present invention will not be impaired.

〔Effect of the invention〕

As explained above, this invention has the following features: 1. 2nd or 3rd
The performance inspection Φ includes a defective parts removal process in which a performance test is performed after at least one process of the connection-fixing process and defective parts are removed, so that defective parts that occur during an intermediate process can be removed and repaired during the process. Since it is not necessary to send defective products to the next process and the yield of good products can be improved, there is an effect that the price of semiconductor devices can be reduced.

[Brief explanation of the drawing]

FIG. 1 is a schematic diagram showing the flow of the manufacturing process of the semiconductor device manufacturing method of the present invention, and FIGS. 2(a) to (i) are diagrams specifically explaining the manufacturing process shown in FIG. 1. , FIG. 3 is a schematic diagram showing the flow of the manufacturing process of a conventional semiconductor device manufacturing method, and FIGS. 4(a) to (h) are diagrams specifically explaining the manufacturing process shown in FIG. 3. It is. In the figure, 1 is an LSI chip, 2a and 6c. 8a and 8b are electrodes, 3 is a first wiring board, and 4a. 4b, 6a, and 6b are protruding electrodes, 5 is a second wiring board, 7 is an insulating substrate, 9 is an Au wire, and 1o is a probe. Note that the same reference numerals in each figure indicate the same or corresponding parts. Agent Masuo Oiwa (2 others) Figure 2 Figure 3 Figure 4 Procedural amendment (voluntary) Mr. Commissioner of the Japan Patent Office - Ayu 1,
Description of the case Japanese Patent Application No. 81-259021 2, Title of the invention: Method for manufacturing a semiconductor device 3, Person making the amendment 5, Detailed description of the invention and drawings 6 in the specification subject to the amendment, Contents of the amendment (1) ) "Performance element" on page 3, lines 7-8 of the specification is replaced with "
"active element". (2) Correct Fig. 4(C) as shown in the attached sheet. that's all

Claims (1)

[Claims] an electrode forming step of forming electrodes on the main surfaces of a plurality of semiconductor chips having active elements consisting of PN junctions and wiring connecting these active elements and having active and passive functions, and a plurality of said semiconductor chips; a wiring/electrode forming step of forming electrodes and wiring for mutually connecting, combining, and transmitting the functions of the semiconductor chip on the main surface of the first wiring board on which the semiconductor chip is mounted; a first connection/fixing step of bonding electrodes and electrically and mechanically connecting and fixing the semiconductor chip to the first wiring board;
a wiring/electrode forming step of forming electrodes and wiring for mutually connecting, combining, and transmitting functions of the first wiring boards on the main surface of a second wiring board on which a plurality of the first wiring boards are mounted; a second connection/fixing step of joining the electrodes of the first wiring board and the electrodes of the second wiring board, and electrically and mechanically connecting and fixing the first wiring board to the second wiring board; A method for manufacturing a semiconductor device comprising a third connecting/fixing step of mechanically and electrically fixing and arranging the second wiring board on which the semiconductor chip and the first wiring board are mounted on an insulating substrate, . A method for manufacturing a semiconductor device, comprising a performance test and a defective parts removal step in which a performance test is performed and defective parts are removed after at least one of the second or third connection/fixing steps.