JPS631114A - Configurable logic element - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Detailed Description of the Invention] <Industrial Application Field> The present invention relates to a configurable logic element (CLE).
igurable・logic-element
), and in particular to a configurable logic element having a configurable combinational logic element, a configurable storage element, and a configurable output selection logic circuit. The output signal of the configurable storage element becomes the input signal to both the configurable combinational logic circuit and the output selection logic circuit. The output signal of the output selection logic circuit is selected from the output signal of the combinational logic element and the output signal of the storage element. The configurable logic elements disclosed herein are suitable for application in microprocessors, and are intended to be easily interfaced with microprocessors without utilizing other features of the configurable logic elements. with additional circuitry.

1, ν, a configurable logic element suitable for being applied to a microprocessor according to the invention has a configurable logic element for storing data from the microprocessor and for providing signals representative of the data stored in the configurable logic element. a second storage circuit, means for enabling a microprocessor to read the state of selected ones of the output signals of the configurable logic element, a configurable storage element, and a storage circuit.

<Prior Art> Japanese Patent Application No. 121357/1987 filed by the same applicant states that even when the same integrated circuit is assembled into a system, multiple logical functions may sometimes be performed. A structure is disclosed in which the state (conf i (111ration)) of the final manufactured integrated circuit can be changed (conf i gura blc) to implement any arbitrary one. This is achieved by providing elements, each configurable logic element being able to change its state to implement any of a plurality of logic functions depending on the required purpose.

Configurable logic elements are multiple logic elements that can be electrically interconnected by switches activated in response to control bits stored on or transmitted to the chip to implement any of multiple logic functions. means a combination of devices. The configurable logic elements disclosed in the patent application are, for example, AND
To provide one or more functions such as those provided by gates, flip-flops, inverters, NOR gates, exclusive OR gates, and combinations of these basic functions to achieve more complex functions. Equipped with all necessary circuit elements. The particular function to be accomplished by the configurable logic element is determined by control signals provided to the configurable logic element from the control logic circuit. In response to this control signal, the configurable logic element changes its physical structure to an A N D gate, an OR gate, a NOR gate, a NAND gate, an exclusive OR gate, or any of a number of other logic functions. This can be achieved without causing any problems.

Structures are formed on the chip that can implement any of these functions to be implemented by the configurable logic elements. This is made possible by providing control logic circuitry that stores and generates control signals that control the state of the configurable logic elements.

In some embodiments, the control signals are stored and transmitted by control logic that is integrally formed as part of an integrated circuit chip that includes configurable logic elements. However, if desired, the control signals may be stored and/or generated external to the integrated circuit in which the configurable logic element is formed, and transmitted to the pins of the configurable logic element. You can also do that.

-ffi, a particular set of control signals as control bits are transmitted from the control logic circuit to the configurable logic element to control the state of the configurable logic element. The contents of the actual set of control bits to be provided to the configurable logic elements on the integrated circuit chip depend on the functions to be implemented by the configurable logic elements on the chip.

<Problems to be Solved by the Invention> U.S. Patent Application No. 706.429 (Japanese Unexamined Patent Publication No. 61-224520) assigned to the present applicant discloses a configurable combinational logic element and a configurable storage element. A highly versatile configurable logic element having a configurable output selection logic circuit and a configurable output selection logic circuit is disclosed. The output signals of the configurable storage elements provide input signals for both the configurable combinational logic and the output selection logic. However, when data signals from a microprocessor are stored in a configurable logic element, problems arise such as the configurable storage element becoming unavailable to receive other output signals from the configurable combinational logic element. , the problem is that this configurable logic element cannot easily communicate with a microprocessor. Moreover, communication between such an array of configurable logic elements and a microprocessor requires the use of a comprehensive interconnect structure for the array of configurable logic elements, which reduces the versatility of the array. Is required.

SUMMARY OF THE INVENTION A configurable logic element according to the present invention suitable for application in a microprocessor is described in U.S. Patent Application No. 706,429 in selecting its possible functions. The disclosed configurable logic elements provide a high degree of versatility.

A configurable logic element according to the invention suitable for application in a microprocessor has a first storage element, each stateable by a control bit, an output selection logic circuit, and a combinatorial logic element. The selected feedback signal from the storage element and the selection input signal provided to the configurable logic element become input signals to the combinatorial logic element. The output signal of the combinational logic element and the input signal to the configurable logic element become the input signal of the stateable storage element l\. The output selection logic circuit provides an output signal selected from the output signals of the combinational logic element and the storage element.

A configurable logic element according to the present invention has additional circuitry to allow easy interfacing to a microprocessor without utilizing other functions of the configurable logic element. In particular, a configurable logic element according to the invention stores a bidirectional data bus and data written by a microprocessor, and selects a stored signal from a combinational logic element and an output signal of the combinational logic element. a second storage circuit for providing a means for making the status of the item readable by the microprocessor, and a stateable storage element.

<Embodiments> Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.

FIG. 1 shows the logic functions that can be realized by configurable logic elements. The 28 functions shown in FIG. 1 are listed for illustrative purposes only and may be listed as desired. It is also possible to realize functions that do not exist using configurable logic elements.

(Left below) Table 1 16 TLU LJ I ANDNO gate 2 NAND gate 3 AND gate 184 with inverted input NAND gate 5 with inverted input 0R gate 19 6 NOR gate 1 Exclusive OR gate 208 Exclusive NOR gate 9 3 person AND gate
2110 3-man powered NAND gate 2211 3-man powered OR gate 23 12 3-man powered NOR gate 13 Has one input with AND gate
24 OR game 1 ~ 2514
NO with one input with AND gate
R gate 2615 0R
AND gate with one input with gate
27 NAND gate with 1 input with OR gate 3-man AND gate with 1 inverting input 3-man power NAND gate with 1 inverting input 3-man power NAND gate with 1 inverting input 3-man power OR gate with 1 inverting input NOR Gate Two-way Power Multiplexer Two-Way Inverting Input Multiplexer “D” Flip-Flop Set with Reset Reset Latch with Reset and Inverting Output “D” Flip-Flop Reset and Set with Inverting Output Reset with Latch Set II D I + flip flop 28
D Puff Flip-Flop with Set and Invert Outputs (Hereafter in the margin) The diagram shows the internal logic layout of one embodiment that can implement all useful basic functions for the two variables A and B. This function uses control leads C05CO1C2, C211
State control signal Co,770,C2,C applied to 0,
2119, is selected. In this embodiment, all control leads are connected to the gate of an N-channel enhancement mode pass transistor. To realize the function of an AND gate with the structure shown in FIG. 2, a high level signal is applied to the state control leads C1 and CO connected to the gates of N-channel N enhancement mode pass transistors 29c and 29d. makes the pass transistors 29c and 29d conductive, and connects the input leads labeled A and B to the inverters 21 and 2.
Shunt across the front and rear ends of 2.

A low level signal is applied to the state control leads 'GO and C1, causing the output signals of inverters 21 and 22 to
Shut off from gate 25. Additionally, a high level signal on lead C5 is applied to the ANDNO gate, enabling AND gate 25.

In this way, the three-man powered AND gate 25 comes to function as a two-man powered AND gate for the signals A and B. The output signal of the AND gate 25 is the output signal of the NOR gate 2
6 input signals are provided. A second input signal applied to NOR gate 26 is derived from the output signals of A N D gates 1-24. The output signal of AND gate 24 is set to logic 0 by applying a logic 0 signal to state control lead C4.
held in state. Control signals C2 and C3 can be at any level, and whether these signals are high or low does not affect the output signal of AND gate 24. AND gate 25, AND gate 24, and NOR gate 26 cooperate with each other to control the input signals It will be easily understood that it functions as one NAND gate for B. Since the three-state control signal applied to NOR gate 27 is a logic 0 (except during reset), NOR gate 27 provides a
It functions as an inverter for the output signal of 6. NO
The output signal of R gate 26 is applied to the gate of N-channel 1-transistor 29A. This transistor 29
A's source is grounded and its drain is connected to output lead 28.
It is connected to the.

The output signal of NOR gate 26 is then applied to the gate of N-channel transistor 29b.

The source of transistor 29b is connected to the power supply, and the drain of this transistor is connected to output lead 28 and the drain of N-channel transistor 29a. Therefore, transistors 29a and 29b function as inverters for the output signal of NOR gate 26. Thus, the structure of FIG. 2 formed in the above-described state functions as an AND gate for signals A and B. In this way, the state control leads CO to C
Other logic functions can be realized by applying appropriate control signals to 5 to activate the appropriate pass transistors and gates within the structure.

Figure 3A shows a 16-bit RA that can generate an output signal for any of 16 combinations of input signals.
Indicates M. Input signals A and B select any of the four columns within the 16-bit RAM by controlling the X decoder. Input signals C and D control the X decoder and select any one of the four rows of the 16-bit RAM. In this manner, the 16-bit RAM produces an output signal corresponding to the bit at the intersection of the selected row and column. There are 16 such intersections, so 1
Six types of bits can be generated. There are 2**16 (216) possible combinations of functions represented by 16 bits. Therefore, if a NOR gate is simulated with 16 bits in R and AM, the Karnot map for RAM will be as shown in FIG.

In Figure 3C, all bits except the bit at the intersection of the first row (representing A-0 and B-0) and the first column (not showing C=0 and D=0) It is 0. If you want to implement a very rarely used function with a 16-bit RAM (for example, to obtain an input signal "1" for A=1, B=O1, C=O and D=O), the second row and 1
A binary "1" is stored at the intersection of the columns. A=O
1 When B=0, C-0 and D=O and A=1, B=O1
Binary “1” exists both when C=0 and D=O.
'', a binary ``1'' is stored at the intersection of the first row and the second row of the first column. A logic circuit corresponding to such a RAM storage state is shown in FIG. 3D. Thus, the RAM of FIG. 3A can effectively and simply represent any of 2**16 logical functions.

FIG. 3B shows another JVI structure that can generate any of the 16 select picks. Registers O-15 in the left vertical column labeled "16 Select Bits" each have a selected signal consisting of a binary "1" or "0". By selecting the appropriate combination of AyB, C and D, the bits stored in any of the 16 positions of the 16 select bit register are transmitted to the output leads. For example, when transmitting the bit of the "1" register to the output lead, the signals A, B
, C and D are added to the reads labeled as such. When transmitting a signal labeled "15" of the 16 locations of a 16 select 1-bit register to an output lead, signals A, B, C1 and D are applied to the appropriate column.

In this way, any of the 2**''L6 logic functions can be implemented using this m-routing.

FIG. 4A shows a configurable logic array (CLA) having nine configurable logic elements. 4th A
As shown, each of the nine configurable logic elements 40-1 to 40-9 has multiple input leads and one or more output leads. Each input lead has a plurality of access junctions connecting selected general interconnect leads to the input lead. 4th A
In the figure, the access junctions of input leads 2 of configurable logic elements 40-7 are labeled A1-A4. Access junctions for other input leads are only shown and are not specifically labeled to avoid cluttering the drawing. Similarly, each output lead of each configurable logic element is
It has a plurality of access junctions connecting the output leads to corresponding ones of the general interconnect leads. Fourth
In Figure A, these access junctions are illustrated for each output lead of each configurable logic element. Access junctions for output reading of configurable logic element 40-7 are labeled 81-B5. The leads shown in Figure 4A that are neither input leads nor output leads are -
A fourth interconnection lead that is not an access junction for input and output leads is called a general interconnect lead.
The junction shown in Figure A is what is called a general interconnect junction.

As shown in FIG. 4A, there is a block diagram 9 with general interconnect connections having pull access junctions and programmable general interconnect leads and programmable general interconnect junctions connecting various leads to other leads. Logic elements are integrated on an integrated circuit chip. The general interconnect structure has a set of general interconnect leads and a programmable junction, the programmable junction having a specific general interconnect portion for each general interconnect lead within the general interconnect structure. Interconnecting general interconnect leads having such characteristics that there is a program governing the general interconnect junction that connects to one or more leads within the general interconnect structure.

Further, for any particular output lead of any configurable logic element within the configurable logic array, and for any particular input lead of any configurable logic element within the configurable logic array, the particular output lead described above may be There is a program that governs this junction such that it is connected to the input lead of. A conductive path from a particular output lead to a particular input lead always includes two access junctions and at least a portion of the general interconnect lead. For example, the conductive path from the output lead of configurable logic element 40-8 to the second input lead of configurable logic element 40-7 includes access junctions A7 and B7 and a portion P of the general interconnect lead.

- Generally, the conductive path from the output lead of one configurable logic element to the input lead of another configurable logic element further includes one or more general interconnection junctions.

Each of the logic elements 40-1 to 40-9 can assume a state as shown in FIG. 2 such that it can implement a circuit as shown in FIG. 2 or any of a plurality of logic functions. Consists of a collection of circuits with similar structures. To program this circuit (to program both the configurable interconnect switch and the configurable logic element), the selected signal is applied to the input lead identified as the configurable control input lead. , each of the logic elements realizes a desired logic function, and the logic elements are interconnected as desired. In FIG. 4A, the leads are not specifically identified as input leads for the state control signals.

However, any I10 pad can be used as this lead.

State control bits are input to the configurable logic array in series or parallel depending on various design conditions, which are typically stored in programmable registers as shown in FIG. Alternatively, the state control pins may be stored in the on-chip memory.

Additionally, a separate I10 pad may be used for input clock signals, particularly those used to transmit state control signals to programming registers.

When the state of the configurable logic array shown in FIG. 4A is defined, selected output signals of logic elements 40-1 through 40-9 are applied to selected I10 pads.

FIG. 4B shows the meaning of the junction symbols used in FIG. 4A.

Configurable logic arrays such as those described above are relatively inefficient in terms of effective utilization of on-chip area compared to fixed-state circuits that perform the same function. The advantage of this configurable logic array circuit is that it is user programmable and can be reprogrammed if desired.

All you need to do is keep one type of chip in stock. If an error is discovered in the program, the chip can be reprogrammed relatively easily by the user.

With conventional chips, if an error was discovered in the program, the chip had to be discarded.

Delays in development and manufacturing cycles caused by chip manufacturers incorporating programs into chips can be prevented. The chip can be manufactured as a versatile standard product that can be configured after sale to meet the needs of the user.

In order to determine the state of a logic element such as logic element 40-1 (FIG. 4A), a number of bits must be provided that constitute a state control lead, such as leads CO-C as shown in FIG. Must be. For this purpose, for example, a shift register is used as part of each configurable logic element. FIG. 5 shows a shift register that can be used for this purpose. The shift register of FIG. 5A has two basic storage cells. Each storage cell has one
Bit information can be stored. Of course, an actual shift register may have as many storage cells as necessary to define the states of the logic elements of which it is a part. During actual operation, an input signal is applied to input lead 58.

As shown in FIG. 6D, this input signal is used to determine the state of a configurable logic element to implement a desired logic function, an access junction, or a general interconnect junction between general interconnect leads as described below. Control bit: Contains a bit string to be supplied to the shift register as an I bit. In this way, the input lead 58
The series of pulses applied to the shift register generates state control bits which, when stored in the storage cells of the shift register, achieve the desired function and/or interconnection state in an appropriate manner. For example, when determining the state of the circuit of FIG. 2 to form an AND gate, pulses C01C1, C
2, C3, C4 and C5 are represented by 1.1, X, X, 0 and 1.

The pulse train applied to input lead 58 consists of clock pulses Φ1 and Φ applied to leads 57 and 59, respectively.
It is synchronized with 2. Thus, in the initial stages of operation, clock pulse Φ1 goes high (FIG. 6A), clock pulse Φ2 goes low (FIG. 6B), and the hold signal (FIG. 6C) goes low during the shift. The flow of data through the storage cells 5-1, 5-2, etc. of the serially connected shift registers is facilitated.

When shifting pattern ro1010J into the shift 1 register, the following operations are performed. That is, the input signal on lead 58 is low during approximately the first half period of clock period t1. The output signal 01 of the inverter 51-1 enables the pass transistor 50-1 in response to the input signal becoming low level and Φ1 becoming high level.

When the time period corresponding to the first clock period t1 has elapsed, the clock signal Φ1 becomes low (FIG. 6A), and the clock signal Φ
2 then goes high (Figure 6B), enabling pass transistor 55-1. In this manner, high level output signal 01 is transmitted to the input lead of inverter 52-1 through enabled pass transistor 55-1, producing a low level output signal Q1 on the output lead of inverter 52-1. let

In this way, at the final stage of the period t1, the output signal Qll from the inverter 52-1 (FIG. 6F) becomes low level. Output signals 02 and Q2 from inverters 51-2 and 52-2 in the second cell are transmitted to the second storage cell 5-2 as known signals for changing the signals of these inverters to a known state. As it has not been done yet, it is still in a state of uncertainty.

At the beginning of the second period (indicated by t2 in Figure 6A), Φ1 goes high (Figure 6A) and Φ2
is low because it was already low before the end of period t1 (FIG. 6B). Input signal (6th
In Fig. D, the signal has risen to a high level representing a binary "1", and therefore the output signal 01 of the inverter 51-1 has become a low level. Output signal Q of inverter 52-1
1 is Φ when the pass transistor 55-1 is at low level
Since it is blocked by the 2 signal, it is still in the low state. After a certain period of time in the second period, first Φ1
goes low and after a short time Φ2 goes high. At this time, the output signal 01 is transmitted to the inverter 52-1 via the pass transistor 55-1, pushing the output signal Q1 from the inverter 52-1 to a high level.

When Ql is at a high level and enables the pass transistor 53-2, the previous low level signal of Ql pushes the output signal 02 of the inverter 51-2 to a high level, enabling the pass transistor 55-2. As Φ2 changes from low level to high level in the second half of period t2, output signal Q2 from inverter 52-2 is pushed down to low level. In this manner, the input signal on lead 58 (FIG. 6D) is transmitted to each storage cell 5-1.5-2.5-3, etc. within the shift register.

Once the desired information has been transferred to the shift register, the hold signal (FIG. 6C) is enabled (i.e., pulled high) and the feedback leads 50-1.50-2.50 from the output leads of inverter 52 are -3 etc. are connected to the input lead of the inverter 51, and the information is semi-permanently held in each cell. In actual operation, the signals stored in a particular cell, e.g. 5-1, are connected to state control circuits or interconnect path devices.

Shift register output word Ql, '01. Q2.02
etc. are directly connected to (state) control inputs of logic elements or to path devices of general interconnect junctions.

When Φ1 is low, the data can be held semi-permanently by pushing Φ1 and the hold signal high. Φ1
and Φ2 high and hold low, the entire shift register can be set or cleared by setting or clearing the input of the shift I register. This signal spans the entire shift register and requires a certain set/reset time to clear each register. Of course, this time depends on the overall length of the shift register.

In its dynamic process, the shift register has shift I~
The information is sent to the shift register inverters 51-1.
52-1.51-2.52-2, etc. (not shown in FIG. 5, but known in the art). These inverters are of known type and detailed description thereof will be omitted. The dynamic shift register uses 6 transistors and therefore requires a small image quality.
It makes sense to use a register for dynamic shift 1. Dynamic shift registers are changed to static latches by simply adding one 1~ register. Therefore, a dynamic shift register (static latch) can be easily manufactured as part of a configurable logic element without significantly complicating the circuit or requiring a large amount of semiconductor area.

Dynamic shift registers can be static latches because of the presence of the hold signal and because holding the shift register automatically refreshes the data.

A separate refresh circuit is therefore unnecessary.

From the above, it can be seen that the dynamic shift 1 register (static latch) does not need to be refreshed once it is latched into the hold state. this is,
This can be achieved, for example, by using a feedback circuit including lead 50-1 and pass transistor 54-1 of memory cell 5-1.

FIG. 7 is a block diagram illustrating nine configurable logic elements according to the present invention, including configurable combinational logic 100, configurable storage 120, and configurable output select logic 140. The combinational logic circuit 100 includes N binary input signals applied to nine configurable logic elements and a storage circuit 12.
M binary feedback signals from 0 are received.

The combinational logic circuit 100 is defined in a plurality of shapes (Con
f i gure). Each state may implement one or more selected combinational logic functions as one or more selected subsets of the input signals to the combinational logic circuit. Since the state of the combinational logic circuit 100 is changeable, it can be used to implement a plurality of different functions. Furthermore, it is possible to realize two or more functions at the same time and combine them into 10 configurable logic elements.
0 can appear on different output leads.

Specifically, the combinational logic port ff4100 selects (K≦M + N) binary input signals from M+N binary input signals. The combinational logic circuit 100 is
The combinational logic circuit 100 implements a plurality of sets of values and a second set of functions of the first set of control signals including at least the first set of values such that the combinational logic circuit 100 implements the first set of functions. in response to a plurality of sets of values of the first set of control signals including at least a second set of values such as . and each function is a function of a subset of the aforementioned binary signals, and each function is a function of a subset of the aforementioned binary signals,
The set of functions is not equal to the second set of functions.

In an embodiment, the combinational logic circuit 100 calculates 2** (2*·kK) as a function of I binary signals.
a first state such as selecting one of the <22> binary values and a first state of the K selected binary input signals;
2** as a function of the selected one input signal of
[2** (K-1>] (i.e. (K-1) 2 ) values and select the second one selected from the selected binary input signals. and a second state such as selecting one of the 2** [2**(K-1>] binary values as a function of the input signal of the second set). (The signal does not necessarily have to be different from the first signal.) The operation of such a combinational logic circuit 100 can be explained by referring to the embodiment shown in FIG. 8, which will be described later. It will be easier to understand.

The memory circuit 120 can also change its state, and depending on the state, for example, a transparent latch circuit with set and reset, a D flip-flop with set and reset, a tube circuit, an edge detection circuit, or one of the shift registers. It can be programmed to implement one or more storage elements, which can be stages, one stage of a counter, etc. Configurable memory circuit 120
receives an output signal from combinational logic circuit 100 on bus 161 and a selected signal from the N input signals of the combinational logic circuit on input bus 160 and a clock signal. The output selection logic circuit 140 is configured to provide an output signal that is selected from the output signals of the combinational logic elements and storage circuits.

FIG. 8 shows one embodiment of the configurable logic element shown in FIG. In FIG. 8, the four input signals of nine configurable logic elements are shown as A, B, C, and D (ie, N=4).

Since circuit 120 only supplies one feedback signal Q to switch 107, M=1.

In FIG. 8, since the signals A, B, C and D or Q are selected from the five signals A, B, C, D and Q, K=
It is 4. The combinational logic circuit element 100 includes configurable switches 101-107.113.114.8-bit RAM 108 and 109.1-8 selection logic circuits 110.
111, multiplexer 112, and state control leads 115 to switches 113 and 114. As described above, the state of each configurable switch is determined by a control bit from a program register (not shown) on the lead (leads other than lead 115 are not shown). The switch 101 can be set in its state to provide signal A as its output signal or to provide signal B as its output signal.

Similarly, switches 102-107 can be configured to provide a selected one of their two input signals as their output signal.

Thus, for example, when making a selection as a state control bit, switch 107 provides a signal such that the binary signals A, C and D are set to 1-8 selection logic 4B 110 and 1-8.
Switches 101 to 103 for 8 selection logic circuit 111
．． 104-107. binary signal A
, C, and D, selection logic 110 selects a different storage element within RAM 108 and outputs the bit stored in the selected location. The 1-8 selection logic circuit B111 is an 8-bit RAM
A similar operation is performed for 109. Multiplexer 11
2 supplies an output signal from the jx selection logic circuit 110 or an output signal from the selection logic circuit 111 depending on the state of the signal B. In this condition, a control bit applied to lead 115 causes switches 113 and 114 to combine the output signals from multiplexer 112 into combinational logic element 1.
00 output leads F1 and F2 at the same time. The two 8-bit RAMs 108 and 109 are programmable to 2**16 different states by binary bits. Depending on the state programmed into the 8-bit RAM, one of 2**16=2** (2**4) possible logic functions can be performed for the four binary variables A, B, C and D. Configurable logic element 10
This can be realized by setting 0. =4 in this case, and the logic function consists of a function of binary variables with binary values.

If another combination of state control bits is selected, switch 107 causes feedback signal 9 from storage circuit 120 to be activated.
and switches 101 to 103 and 104 to 107
．． The status of 113 and 114 is the same as above. The configurable logic element 100 includes two 8-bit RAiV1
For each program state 108 and 109, realize one of 2**16=2*(2**4) possible logical functions in the four binary variables A, B, C, and Q. . Also in this case, =4.

If you select a different state control bit, switch 1
01-103 provide signals A, C and Q, switches 104-106 provide signals B, C and Q, and leads 1
The control signal applied to switch 15 causes switches 113 and 11 to
4, the output signal of the selection circuit 110 is supplied to the lead F2, and the output signal of the selection circuit 111 is supplied to the lead F1. In this way, 2**8=2**(2**
3) 2**8=2** for the three binary variables A, C and Q for each of the program states.
It realizes one of the (2**3) logic functions and creates three binary variables B, C on lead F2 for each of the 2**8 program states of RAM M2O3.
and Q's 2* * 3 = 2 * * (2 * *
3) Realize any of the following logical functions.

Generally, three variables from the four variables A, B, C and D/Q are selected as first selection and 1. and select four variables A, B, C
and D/Q as the second selection, the three variables selected as the first selection are placed on lead F2 for each of the 2**8 possible program states of the 8-bit RAM 108. 2** (2
**3) 2**<2 of the three variables that implement the 2** logic functions and are selected as the second selection on output lead F1 for each of the 2**8 possible program states of RAM 109. **3) Each state of the configurable logic element 100 exists such that it realizes any of the following logic functions.

In another embodiment not shown, any four binary functions for two variables chosen from variables A, B, C and D/Q can be implemented on four additional output leads of the configurable logic element. If possible, add two 1-4 selection logic circuits to each 8-bit RAM.
I am trying to re-divide M. Similarly, in another embodiment not shown, a 32-bit RAM, signal A,
B, C and D, and feedback signal Q are all 3
2 bits corresponding to each program state of the 2-bit RAM.
It is used to enable a state that realizes any one of **(2**5) binary functions. (
In this case, N=4, M=1 and M=5). In another situation not shown, N=4, M=1 and M=5, a first binary function for variables A, B and C, a second binary function for variables B, C and D. binary function F
2, and a third binary function F3 for variables B, C, D and Q is realized. The important thing here is that KM K2- K3- K2 +2
+2 = 2 (however, Ki- is i=1.
2.3 is the number of variables of the function Fi. ) is established.

Referring again to FIG. 8, it is important to note that configurable switches 101, 102 and 103 select a subset of these input signals and route the subset of input signals to circuit 11.
0 selected input leads with a one-to-one correspondence. For example, in response to one value set of state control signals, configurable switches 101, 102 and 1
02 provides signal A to lead 110-3, signal B to lead 110-2, and signal C to lead 110-1.

The output signals on leads F1 and F2 are input signals to configurable storage circuit 120.

Signals A, C, and D are also input signals to the storage circuit 120. The configurable storage circuit 120 includes programmable switches 122, 123, 126 to 128, exclusive OR gates 124, 129 and 130, AND
Gates 125, 131 and 132, and storage element 121
has. Storage element 121 has reset, data and clock input leads to cellar 1 designated S, R, D and Ck, respectively, and output lead Ql''F.
and QLA.

The states of the switches 123, 126-128 are determined so that any one of the respective input signals is selected as the output signal. a set of storage elements 121, a set corresponding to clock and reset input leads;
Clock and reset functions are all in high state
Exclusive OR gate 12 for each logic 1 signal
4.129 and 130 INVS, INVC and I,N
Switch 123.127 by adding to VR lead
and 129 output signals. Logic 0 signal leads INVS,INVC
and when added to INVR, exclusive OR
The polarity of the output signal of gates 124, 129 and 130 is equal to the polarity of the input signal.

When a logic 1 signal is applied to the INVS, INVC and INVR leads, exclusive OR gate 124.1
The output signals 29 and 130 are inverted signals of the input signals.

A N D cables 1-125, 131 and 132 are enabled by applying logic 1 signals to the ENS, ENC and ENR leads. A logic 0 signal applied to these leads disables these gates. When a logic 0 signal is applied to any one of the major circuits 1-ENs, ENC, or ENR, the output of the AND gate becomes a logic 0 level, and the corresponding function of the memory circuit 121 changes to the state of the corresponding OR gate. Disabled regardless. The QFF generates a flip-flop output signal and the QLA provides a latch output signal as described above with respect to FIG. Configurable switch 122
selects one of the binary signals of leads QFF and QLA, and the output signal Q of switch 122 becomes an input signal of output selection logic circuit 140 and configurable combinational logic circuit 100.

FIG. 9 shows one embodiment of the memory circuit 121. Memory element 1
21 has two D latches LAI and LA2 connected in series to form a flip-flop. Latch LAI has N-channel pass transistors L1 and P2 and NOR gates G1 and G2. The gates of pass transistors P1 and P2 are controlled by signals Ck and 'Qk. Similarly, latch LA2 connects N-channel pass transistors P3 and P4 and NOR gate G
3 and G4. The gates of transistors P3 and P4 are controlled by signals Ck and Ck. The D input lead is the data input lead for latch LAI. S
The input leads function as the set input lead for latch LAI and the reset input lead for latch LA2. The R input lead serves as the reset input lead for latch LAI and the set input lead for latch LA2.

The output signal GLA of NOR gate G1 is connected to the data input lead of latch LA2. Output 'J-toQ
LAc is connected to the output lead of the latch LA1 (7) NOR gate G2, and the output lead QFF is connected to the output lead of the NOR gate G3 of the latch LA2.

The configurable input/output circuit 120 (FIG. 8) functions as a transparent latch with set and reset l- by setting the switch 122 in a state that connects the output lead Q and the output lead Q[A]. do. While clock signal Ck is low, the output signal of lead QLA follows the input signal. When clock signal Ck goes high, the output signal of QLA is held, cutting off pass transistor P1 and making pass transistor P2 conductive.

The storage circuit 20 can be configured to function as a D flip-flop circuit with a set and a reset. In this state, switch 126
is established to select the signal on lead F1, and gates 125, 131 and 132 are enabled by applying logic 1 signals to leads ENS, ENC and ENR. Finally, the state of switch 122 is established to control the output signal of the lead QFF of storage element 121. Storage element 120 reads a logic 0 signal E
By changing the above state by adding to NS and ENR, its state can be defined as a D flip-flop circuit without cell l- and reset.

The configurable storage circuit 120 is configured such that the AN input signal is generated at the Ck input lead of the storage element 121.
By enabling D gates 125 and 132 and disabling AND gate 131, the state can be established to be an R slatch. Lead C
A logic 0 signal on k turns off pass transistor P3 and makes pass transistor P4 conductive. Switch 122 is then set in its state to select the output signal on the QFF.

Finally, storage circuit 120 can be configured to function as an edge detection circuit. For example, to define the state of storage element 120 as a rising edge detection circuit, AND gate 125 is disabled by applying a logic 0 signal to input lead S, AND gate 131 is enabled, and the clock signal is so that it is transmitted to input lead Ck, switch 1
26 is defined such that a logic one signal is applied to input lead D to select input lead 126a. ANDNO gate G32 is enabled. A logic 1 reset signal forces the output signal on the QFF to a logic 0 signal. If the clock signal is low, pass transistors P2 and F3 are cut off and pass transistor P1 conducts.

As a result, NOR gate G1 inverts the logic 1 signal on lead D and produces a logic O signal on note ULA. When the clock signal is pulled high, transistors P1 and F4 shut off, transistors P2 and F3 conduct, and a logic 0 signal on node QLA is driven to the NOR gate 23.
is inverted, producing a logic 1 signal on the output lead QFF, resulting in the detection of a rising edge. The reset input is then used to reset the QFF to O, and the edge detection circuit is ready to detect the next rising edge. When the clock signal is pressed down, transistors P2 and F3 are turned off, transistor P4 conducts, and the signal on QFF remains in a logic 0 state and does not change state until the next rising edge.

Similarly, the state of the memory circuit Fl@120 is changed to the logic 1 signal by exclusive OR go 1-. 129 INVCs
By adding it to the lead, it can be defined as a falling edge detection circuit. Similarly, the uniqueness circuit 120 can function as a shift register or one stage of a counter.

Output jx selection logic circuit 140 is a configurable switch such that its state can be defined to select one signal from the output signals obtained from combinational logic circuit 100 and appearing on leads F1 and F2 and the output signal of storage element 120. 141 and 142.

The nine configurable logic circuits shown in FIG. 8 are not suitable for communicating with a microprocessor. For example, if it is desired to write data from a microprocessor to store data in storage element 121, storage element 121 is not available to receive other output signals from combinational logic element 100. Furthermore, communicating between a microprocessor and a configurable logic element array consisting of a plurality of configurable logic elements, each corresponding to configurable logic element 99, may result in an overall failure that reduces the diversity of the logic array. Requires interconnect structure.

FIG. 10 shows a configurable logic element 210 according to the present invention, which is made by modifying the nine configurable logic elements shown in FIG. 8 to be suitable for application in a microprocessor. The configurable logic element 210 is
It includes all of the circuitry shown in FIG. 8 plus a latch 205, programmable switches 201-204, 206, and a three-state buffer 208.

Lead WRY connected to input lead G of latch 205
Information is stored in latch 205 by applying a write signal to , and the signal to be stored is transmitted to input lead D via sending direction data lead DBX. latch 2
Change the state of the Q output lead of 05 appropriately as desired (
A state changeable switch 20 for performing a program)
1 to 204 can be connected to any of the input leads A to D. These connections can be accomplished using pass transistors or other well-known switching elements as shown in FIG. For example, switch 202
can be configured to connect the output sword Q to the input lead C.

Generally, the switches 201-204 are set by control pins of a programmable register (not shown) connected to the settable switches by leads (not shown).

Similarly, switch 206 is set by a control pin l- of a programmable register (not shown) which is also connected to settable switch 206 by a lead (not shown). The switch 206 has a lead 206a
206d may be configured to connect to output lead 207. In this way, the switch 206 outputs either the signal stored in the latch 205, the output signal of the state-configurable combinational logic circuit 100, or the signal stored in the storage circuit 121 to the lead 207. supply Sui...Ichi 206
The user decides which of these three types of signals to supply.

When a read signal is provided on lead RDY, tri-state buffer 208 is enabled. When enabled, tristate buffer 208 provides the signal on its input lead 207 to bidirectional data lead DBX. When not enabled, the output of tristate buffer 208 is in a high impedance state. The state of tri-state buffer 208 is controlled by the level of the signal on RDY in well known manner. In this manner, by establishing the state of latch 206 and enabling tri-state buffer 208,
The user can determine the status of selected important internal signals of the configurable logic element 210, for example, the status of any of the output signals of the combinational logic circuit 100, the storage circuit 1
The status of the output signal of 21 or the status of the signal stored in latch 205 can be checked (read).

FIG. 11 shows the configurable logic element 21 of FIG.
Configurable logic element CLE (x, y
＞(x, y=0. ・ ・ ・ , 7) 8×8
A chip 30 comprising a configurable logic element array of
Indicates 0. (In another embodiment not shown, the eleventh
Some of the configurable logic elements in the array shown in the figure are identical to configurable logic element 210, and other configurable logic elements are identical to the configurable logic elements shown in FIG. has been done. ) Microprocessor interface structure 180 generates read/write signals to operate registers RO-R7. Register RY has eight state-settable logic elements, namely configurable logic elements CLE (x, y
) (x=O, --., 7). Each configurable logic element is identical to configurable logic element 210, and each configurable logic element is configurable to provide a different output signal on leads 143.1114 shown in FIG. The output leads and overall interconnect structure of the configurable logic elements are omitted from illustration in FIG.

The configurable logic element array adapted to the microprocessor shown in FIG. The interconnect structure of the configurable logic element array 300 (11th
It has a high degree of flexibility in that the storage element 121 can remain available without using any of the storage elements (not shown).

In addition, the microprocessor interface logic circuit 1
In implementing 80, there is no need to utilize any of the logic functions implemented by the configurable logic elements in the array.

Microprocessor interface logic 180 has three types of input buses. That is, a bus 310a for receiving address signals, a bus 310b for receiving chip enable signals, and a bus 310 for receiving control signals.
It has C. The output signal of microprocessor interface logic 180 becomes a read/write signal on bus 301 whose dimensions depend on the number of registers used. In this case, bus 301 has 8 read/reads and 8 write/reads.

Blocks 1900-1907 with bidirectional buffers for each data line DBO-DB7 and microprocessor interface logic 180 are shown in more detail in FIG. In this embodiment, address bus 310a provides a 3-bit address to microprocessor interface logic 180, which determines the specific register R to be read or written in FIG.
A signal for selecting V is generated. Portion 310b includes microprocessor interface logic 180.
The chip enable signal is supplied to the chip enable signal. Control bus 310C
is a read RD having a read read RD and a write read W shown in FIG.
An input-output signal is generated on lead I10 that determines the state of 97. For the first selection signal generated on lead I10, the signal is provided from microprocessor 310 through buffers 190AO-A7 to data leads DBO-DB7 shown in FIG. 2nd lead I/U
Regarding the selection signal, the data signal is connected to the bus DBO~DB.
7 to the microprocessor 310 via buffers 190Bo to 190B7.

13 and 14 are timing charts showing the read cycle and write cycle of the chip 300.

FIG. 15 shows a system using the configurable logic element array chip 300 for microprocessors shown in FIG. The portions of the system shown in FIG. 15 include a microprocessor 310, a RAM/ROM memory 312, a decoder 305, a printer 315, and a configurable logic element array 300. In this embodiment, a configurable logic element array 300 is used to interface a microprocessor 310 to a printer 315. The configurable logic element array in such a system is based on conventionally used small scale integrated circuits (SSI), medium scale integrated circuits (M
SI) or large prefectural bond circuit (LSI). Microprocessor is ROM/RA
The program stored in the M memory 312 is executed. Configurable logic element array 300 receives commands from microprocessor 310 obtained on the data bus, generates appropriate printer control signals, and transfers the signals to fourth
I10 pin (first
1 and 15)) to the lead 31.
5a. Configurable logic element array 30
0 receives data to be printed from microprocessor 310 on the data bus, adapts the data format to the printer as necessary, and provides the data to printer 314 via lead 315B.

The status 1 word from printer 314 is provided to lead 315C of configurable logic element array 300. The states of the three status signals are transferred to microprocessor 310 via the data bus when microprocessor 310 reads the appropriate registers within configurable logic element array 300.

Although the preferred embodiments of the present invention have been described above, those skilled in the art can implement the present invention with various modifications and changes without departing from the concept of the present invention.

In the claims, reference is made to means having various states, which means means capable of determining their state in response to a set of values selected from a set of control signals that perform a particular function. means.

[Brief explanation of the drawing]

FIG. 1 illustrates some of the various logic functions that may be implemented by configurable logic elements within a configurable logic array. Figure 2 shows two variations v1. 2 shows the internal logical structure of one possible embodiment of a configurable logic element that can implement a useful number of functions for A, B; FIG. 3A shows a 16-bit RAM that can specify any of 16 input states and implement 2 to the 16th power. FIG. 3B shows a selection 4'74 structure for selecting any one of the 16 bits to be transmitted to an external terminal such that 2 to the 16th power of functions can be implemented. FIG. 3C shows one possible Karnaugh map for the structure of FIG. 3A. FIG. 3D shows a logic gate when a binary 0 is placed at the intersection of the first and second rows and the first column in the Karnaugh map of FIG. 3C. FIG. 4A shows an integrated circuit chip with programmable interconnect lines formed between selected leads and selected input/output pads and lead interconnect lines between logic elements to achieve the desired logic function. 3 illustrates a plurality of configurable logic elements consisting of nine logic elements formed above. FIG. 4B is a key representing the connection state of the leads that intersect in FIG. 4B. FIG. 5 shows a portion of a novel combinational static and dynamic shift register circuit that can be used with configurable logic elements according to the present invention. 6A to 6H are waveform charts showing the operation of the structure of FIG. 5. FIG. 7 shows a configurable logic element according to the present invention. FIG. 8 shows one embodiment of the configurable logic element of FIG. FIG. 9 shows one embodiment of storage element 121 of FIG. FIG. 10 shows one embodiment of a configurable logic element suitable for application in a microprocessor according to the invention. FIG. 11 shows a chip using the array of configurable logic elements shown in FIG. FIG. 12 is a circuit diagram schematically illustrating a microprocessor interface logic circuit 180 for the array of configurable logic elements shown in FIG. FIG. 13 is a timing chart showing the timing of the read cycle for the cycle E@300 shown in FIG. FIG. 14 is a timing chart showing the timing of write cycles for circuit 300 shown in FIG. FIG. 15 is a circuit diagram illustrating a system using the chip shown in FIG. 11 with a microprocessor and storage elements. 21.22... Inverter 25... AND gate 26... NOR gate 29
... To transistor 201 204.206 ... Programmable switch 205 ... Latch 208 ... Three-state buffer 180 ... Microprocessor interface logic circuit 210 ... Configurable logic element 300 ... Configurable logic Element array 310...Microprocessor 315...Printer Patent applicant: Jilinx Incorporated Representative Patent attorney: Yo Oshima - Two-sided engraving (
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13 Atrocities CL 8p: Part h Part 0.14 Procedural amendment (method) July 10, 1988 Patent application No. 075742 2, Title of invention Configurable logical element 3, Person making the amendment Case and Relationship Patent applicant name Zirinx Incorporated 4
, agent

Claims (11)

[Claims] (1) A configurable logic element, comprising N first
means for receiving binary input signals; means for receiving M second binary feedback signals; and means for receiving M second binary feedback signals;
configurable combinational logic means capable of assuming a plurality of states for generating a selected binary output signal and receiving said K binary signals from said selection means; capable of assuming a plurality of states and receiving a selected one of said binary output signals of said configurable combinational logic means and a selected one of said N first binary input signals; a first configurable storage circuit for generating M second binary feedback signals; and a first configurable storage circuit for generating M second binary feedback signals; a configurable selection logic circuit comprising means for receiving a feedback signal and means for selecting an output signal from the signals received by the means; and said binary output signal of said configurable combinational logic means and said M second binary and means for reading the status of one signal selected from among the feedback signals. (2) a second storage circuit that stores a data signal and supplies an output signal corresponding to the stored signal; and receives an output signal of the second storage circuit and outputs the output signal.
configurable means for receiving N first binary input signals, the output signal of the second storage circuit being any of the N first binary input signals; Configurable logic element according to claim 1, characterized in that: (3) The configurable logic element according to claim 2, wherein the means for reading the status comprises means for reading the status of the output signal of the second memory circuit. (4) the means for reading a status is capable of assuming a plurality of states, receives the binary output signal of the configurable combinational logic means and the M binary feedback signals, and is in each of the states; switch means for providing a signal representing a different one of the signals received by the device; and receiving a signal from the configurable storage circuit and generating an output signal representative of the signal received by the device when the device is enabled. 3. The configurable logic element of claim 1, further comprising a 3-state buffer. (5) A configurable logic element, the N first
means for receiving binary input signals; means for receiving M second binary feedback signals; and means for receiving M second binary feedback signals;
configurable combinational logic means capable of assuming a plurality of states for generating a selected binary output signal and receiving said K binary signals from said selection means; capable of assuming a plurality of states and receiving a selected one of said binary output signals of said configurable combinational logic means and a selected one of said N first binary input signals; a first configurable storage circuit for generating M second binary feedback signals; and a first configurable storage circuit for generating M second binary feedback signals; a configurable selection logic circuit comprising means for receiving a feedback signal and means for selecting an output signal from the signals received by the means; a second circuit for storing a data signal and providing an output signal corresponding to the stored signal; a configurable storage circuit; and configurable means for supplying an output signal of the second storage circuit to the means for receiving the first N binary input signals. Rubble logic element. (6) means for receiving N first binary input signals;
means for receiving M second binary feedback signals; and means for receiving M second binary feedback signals;
≦N+M); and configurable combinatorial logic means capable of assuming a plurality of states for generating a selected binary output signal and receiving said K binary signals from said selection means. , capable of assuming a plurality of states and receiving a selected one of said binary output signals of said configurable combinational logic means and a selected one of said N first binary input signals; a first configurable storage circuit that generates the M second binary feedback signals; a first configurable storage circuit that generates the M second binary feedback signals of the configurable combinational logic means; a configurable selection logic circuit comprising means for receiving a binary feedback signal and means for selecting an output signal from the signals received by the means; and a circuit for storing a data signal and providing an output signal corresponding to the stored signal. 2 configurable memory circuit;
a plurality of configurable logic sub-elements each having configurable means for providing an output signal of the second storage circuit to the means for receiving the first N binary input signals from a data bus; a configurable logic element, comprising: means for selectively communicating a data signal to the second storage circuit. (7) said means for selectively communicating data signals receives address signals and control signals from a microprocessor and determines which of said second storage circuits should store the data signals; 7. Configurable logic element according to claim 6, characterized in that it has a microprocessor interface circuit for generating signals. (8) The configurable logic element according to claim 7, wherein the configurable logic sub-elements are arranged as a rectangular matrix. (9) means for receiving N first binary input signals;
means for receiving M second binary feedback signals; and means for receiving M second binary feedback signals;
≦N+M); and configurable combinatorial logic means capable of assuming a plurality of states for generating a selected binary output signal and receiving said K binary signals from said selection means. , capable of assuming a plurality of states and receiving a selected one of said binary output signals of said configurable combinational logic means and a selected one of said N first binary input signals; a first configurable storage circuit that generates the M second binary feedback signals; a first configurable storage circuit that generates the M second binary feedback signals of the configurable combinational logic means; a configurable selection logic circuit comprising means for receiving a binary feedback signal and means for selecting an output signal from the signals received by the means; a configurable logic sub-element comprising: means for reading a status of a selected one of the binary feedback signals; selecting a particular one of said means for reading a status; and said reading means; and means for supplying a signal read by said particular one to a data bus. (10) The configurable logic element according to claim 9, wherein the selection means includes a computer interface circuit. (11) A configurable logic element, comprising means for receiving N first binary input signals, means for receiving M second binary feedback signals, and K signals from among the M+N binary signals. (However, K≦N
configurable combinational logic means capable of assuming a plurality of states for generating a selected binary output signal and receiving said K binary signals from said selection means; capable of assuming a plurality of states and receiving a selected one of said binary output signals of said configurable combinational logic means and a selected one of said N first binary input signals; a first configurable storage circuit for generating M second binary feedback signals; and a first configurable storage circuit for generating M second binary feedback signals; a configurable selection logic circuit comprising means for receiving a feedback signal and means for selecting an output signal from the signals received by the means; and said binary output signal of said configurable combinational logic means and said M second binary means for reading the status of a selected one of the feedback signals; a second storage circuit for storing a data signal and providing an output signal corresponding to the stored signal; and said second storage circuit. receives the output signal, and converts the output signal into
configurable means for receiving N first binary input signals, the output signal of the second storage circuit being any of the N first binary input signals; A configurable logic element characterized by: