JPS63111417A - Dividing circuit for measuring instrument - Google Patents

Abstract

PURPOSE:To decrease the number of comparators and to constitute a dividing circuit which suits to IC-implementation by connecting nodes of a resistance chain to comparators which are less than the nodes analog switches. CONSTITUTION:Plural primary signals which are out of phase with one another are supplied to the resistance chain 16 through buffer amplifiers 20A, 20B, and 22. Voltages at nodes (a)-(h) of the resistance chain 16 are selected successively by the analog switches 40A-40H and inputted to one common comparator 42. A counting signal synchronized with the output clock CP of an oscillator 32 is obtained by a direction inverting circuit 44, a direction discriminating circuit 46, AND gates 48A and 48B, and a latch circuit 48C according to whether the output comparison signal J1 of the comparator 42 is high or low. Further, this counting signal is fed back to an octal ring counter 50 to switch selections of said analog switches 40A-40H.

Description

[Detailed description of the invention]

[Industrial use of bones! I! F1 The present invention relates to a dividing circuit for a measuring device, and is particularly suitable for use in a measuring device that electrically measures the amount of relative displacement by converting linear displacement or angular displacement into an electrical signal using a detector.
Multi-phase primary signals with mutually different phases are applied to different nodes of a resistance chain to generate phase-shifted secondary signals at other nodes, and these nodes of the resistance chain are connected to corresponding comparators. , relates to an improvement in a dividing circuit of a measuring device that outputs a count signal whose pitch is finer than that of the primary signal by comparing the primary signal or the secondary signal with a reference level. [Prior Art] In a wide range of fields such as machine tools, measuring instruments, and portable electronic measuring instruments, for example, a linear displacement measuring instrument shown in FIG.
Outputs the phase detection signal (primary signal), processes the signal, generates a count signal including forward/backward information, and outputs the counter 1.
Measuring devices that can digitally measure the amount of relative displacement by inputting the information into 4 are in widespread use. In this measuring device, since the resolution is usually coarse in the pitch of the primary signal, the dividing circuit 12 is used to obtain count signals of finely divided pitches.
is used. As the dividing circuit 12, for example, Swiss Patent No. 4075
Divider circuits using resistive chains are well known, as shown in US Pat. In principle, this dividing circuit, as shown in FIG. 8, sends primary signals such as A sin θ, A CO3 to nodes at both ends of a resistance chain 16 consisting of resistors R1 and R2.
When a signal approximated by θ(=A 5irl(θ+90°)) is applied, A' 5in(
It takes advantage of the fact that a signal approximated by θ+α) is generated. Here, the amplitude A' and phase difference α of the synthesized secondary signal are expressed by the following equations. A' =Aff+R22/ (R1+R2)...
...(1) α=arctan(R1/R2) =12) That is,
By selecting the resistance values R1 and R2, the phase difference α can be changed from 0° to 90°.
Can be set to any value up to °, A sinθ
A signal having an arbitrary phase between and A COS θ is obtained. Therefore, by outputting a count signal when this signal crosses the zero level, a count signal of subdivided pitches can be obtained. Note that if the detection signal is not a sine wave,
By changing the resistance value accordingly, a signal with an arbitrary phase can be obtained. FIG. 9 shows an example of a conventional resistance divider circuit that can divide the pitch of the primary signal into 16.
is a buffer amplifier for the primary signal A sin θ, 20B is a buffer amplifier for the primary signal A CO3θ, and 22 is a signal −A sin obtained by inverting the output of the buffer amplifier 2OA.
an inverting amplifier for applying θ to the nodes of the resistance chain 16;
24A to 24H are a total of eight comparators corresponding to each node of the resistance chain ff116, and 26 is
28A to 28F are exclusive OR gates for synthesizing the outputs of the comparators 24A to 24H; 30 is a direction discrimination circuit; 32 is an oscillator. In this dividing circuit 12, resistors R1, R2, R3,
The values of R4 are 1:0.707:0.707:1, respectively.
Since 180° is divided into 8 parts, 360° is divided into 16 parts. This resistor divider circuit is disclosed in Swiss Patent No. 40756.
Since it is disclosed in detail in the specification of No. 9, detailed explanation will be omitted.

[Problems to be solved by the invention]

However, in the conventional resistance divider circuit shown in FIG. 9, the resistance 3! ! Each node of chain 16 and comparator 24
Since A to 24H are connected in a 1=1 manner, generally when dividing the pitch of the primary signal by 2N, N comparators are required, and the number of comparators increases in proportion to the number of divisions. Therefore, the entire circuit including the comparator is @product circuit (IC
), the characteristics of the comparator, such as the potential difference between the comparison input signal and the reference level when the output of the comparator is inverted, tend to vary, and the response speed deteriorates. Furthermore, since it is necessary to add a hysteresis setting resistor to each comparator to prevent and stop oscillation, even if it is integrated, it will be larger compared to other circuits, so especially if the number of divisions becomes large, the I
This had problems such as the overall size of C. In addition to IC implementation, circuits in which many comparators are arranged in parallel also have the problem of poor response speed, such as erroneous counting when the primary signal changes instantaneously.

[Purpose of the invention]

The present invention has been made to solve the above-mentioned conventional problems, and is suitable for IC implementation by reducing the number of comparators, and has an improved response speed that can follow instantaneous changes in the primary signal. The purpose is to provide a dividing circuit for a measuring device.

[Means to solve the problem]

The present invention applies multi-phase primary signals with mutually different phases to different nodes of a resistor chain 11 to generate phase-shifted secondary signals at other nodes, and to connect these nodes of the resistor chain to corresponding nodes. In the dividing circuit of the measuring device, which outputs a count signal whose pitch is finer than that of the primary signal by comparing the primary signal or the secondary signal with a reference level by connecting to a comparator, each of the resistance chains A node is connected to a smaller number of comparators than the node through an analog switch, and a count signal synchronized with a clock pulse is obtained according to the delay of the output of the comparator, and the count signal is fed back to the analog switch. The above object is achieved by providing a servo circuit for switching selection. In addition, Mr. R, who implements the present invention, uses 1 as the comparator.
These comparators are shared.

[Effect]

In the dividing circuit of the measuring device, each node of the resistance chain is connected to a smaller number of comparators than the nodes through an analog switch, and depending on the delay of the output of the comparator, a count signal synchronized with a clock pulse is generated. In addition to obtaining
A servo circuit is provided that feeds back the counting signal to switch the selection of the analog switch. Therefore, the number of comparators is reduced, making it suitable for IC implementation. Also, 1
Even if the next signal changes instantaneously, it can be tracked and response accuracy is improved. Further, when one comparator is shared as the comparator, the number of comparators can be minimized.

【Example】

Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. The first embodiment of the present invention is one in which the present invention is applied to a 16-division dividing circuit similar to the conventional example, and as shown in FIG. In the circuit 12 that includes an amplifier 22, a resistor chain 16, a reference voltage setter 26, and an oscillator 32, the resistor 3! ! Each node a to h of the chain 16 is connected to one shared comparator 42 via the corresponding analog switch 40A to 40H, and depending on the comparison signal J1 of the output of the comparator 42, Direction reversal circuit 44, direction discrimination circuit 46, and AND gate 48
A, 48B and the latch circuit 48C, the oscillator 3
A counting signal (UP
count pulse and DOWN count pulse), and feed back the count signal to the analog switch 4.
An octal ring counter 50 is provided as a servo circuit for switching the selection of 0A to 40H. The detection signal (primary signal) input from the detector is:
Although there may be a signal similar to a triangular wave or a trapezoidal wave, the explanation will be made assuming that it is approximated by a sine wave for convenience and that the phase difference is also 90°. Therefore, from the detector, A sin θ, As1n(
θ+90") = A It is assumed that the primary signal of CO3θ is output to the dividing circuit 12. Here, θ is the phase corresponding to the displacement. The primary signal input from the detector is A sinθ, AcO3
θ is input via buffer amplifiers 20A and 20B, respectively, and from A sin θ, an inverting amplifier 22 outputs a primary signal A 5in (θ+180
°)=-A sin θ is generated. The resistance chain 16 is composed of a total of 89 resistors, and 1
The following signals are applied to nodes a, e, and i, respectively. The resistance values of resistors R1, R2, R3, and R4 have a ratio of 1:
0.707:0.707:1, and as a result, the phase of the secondary signals generated at other nodes b - h is 180'/8 = 22.5 degrees from node a. It is set to shift gradually. The signals at each node at this time are shown in FIG. 2. When the primary signal changes as shown in the figure in accordance with the displacement of the object to be measured, the secondary signal changes with a phase shift accordingly. In this first embodiment, the phase difference of 180° is divided into 8 equal parts, so as will be described later, 3
Divided into 16 equal parts at 60°, 16 divisions are achieved. Note that if the detection signal is not a sine wave, this can be handled by adjusting the resistance value. Each node a to h of the resistance chain 16 is connected to one node through a total of eight analog switches 40A to 40H provided correspondingly.
The reference voltage Vr, in this case O■, is applied to the other input of the comparator 42. The analog switches 40A to 40H are, for example, MO3
Each type of FETE has a function in which the resistance is almost zero in the selected state, and high resistance in the non-selected state, so that the connection is considered disconnected. Selection of the analog switches 40A to 40H is performed by the output of a reversible octal ring counter 50 used as a servo circuit.The ring counter 50 has an output "1" that moves according to the input. Only one of the eight analog switches 40A to 40H is always selected. The numbers on the right side of FIG. 2 indicate the numbers of the output terminals of the ring counter 50 for selecting the nodes on the left. When a certain node and the comparator 42 are electrically connected, when the signal level of the node is higher than the zero level, the comparison signal J1 becomes "1", and when the signal level is lower than the zero level, the comparison signal J1 becomes "1". It becomes "0". Output 1 and output 8 of the octal ring counter 50 are also input to the direction inversion circuit 44. As will be described later, when switching from output 1 to output 8 or vice versa, the comparison signal J of comparator 42
Since J1 is inverted, the inversion signal K is generated in such a way that even if J1 is inverted, the forward/backward determination is not inverted. The direction reversal circuit 44 is connected to the octal ring counter 50.
a pulse expander 44A to which the output 1 of the octal ring counter 50 is input; a pulse expander 44B to which the output 8 of the octal ring counter 50 is input; an AND gate 44C which outputs the AND of the pulse expanders 44A and 44B; The AND gate 44C
The T flip-flop 44D generates an inverted signal K when the output of the octal ring counter 50 switches from 1 to 8 or vice versa based on the output of the octal ring counter 44D. Therefore, when the output of the octal ring counter 50 switches from 1 to 8 or vice versa, the direction reversing circuit 44 outputs
An inverted signal K is output for identifying this. The direction discrimination circuit 46 includes an AND gate 46 that outputs the logical product of the comparison signal J1 inputted from the comparator 42 and the inverted signal inputted from the direction inversion circuit 44.
A, an AND gate 46B that outputs the AND of the negation of the comparison signal J1 and the negation of the inverted signal;
An OR gate 46C that outputs the logical sum of gates 46A and 46B as an addition signal L1, and an inverter 46 that inverts the output of the OR gate 46C and outputs it as a subtraction signal L2.
It is composed of D. Therefore, this direction discrimination circuit 4
6, from the comparison signal J1 and the inverted signal K,
An addition signal L1 and a subtraction signal L2 are created. The truth table of this direction discrimination circuit 46 is shown in Table 1 below. On the other hand, from the oscillator 32, for example, 7 in 500 or 4
A clock pulse CP of M) tz is supplied. Therefore, when the addition signal L1 is "1", an UPP number pulse is output, and when the subtraction signal L2 is "1", a DOWN count pulse is output. This UPP number pulse and DOWN counting pulse constitute a counting signal. In the octal ring counter 50, the tJP counting pulse and the DOWN counting pulse are inputted to the DN terminal and the UP terminal in reverse, respectively, so when the UP counting pulse is large input, the output of the ring counter 0 becomes 8→ It rotates in the order of 7→...→1→8, while when inputting the DOWN counting pulse, 8
The output of the forward ring counter 50 is 1→2→...→8→1
Rotate like. The operation of the first embodiment will be described below with reference to FIGS. 2 and 3. FIG. 3 shows a time chart of the signals of each part of the dividing circuit 12 when the primary signal changes as shown in FIG. In state A, the ring counter 50 has terminal 3 as "1" and the inverted signal as "1". In this case, as shown in FIG. 2, the nodal signal is less than zero, so the comparison signal J1 is "0". ,
From the truth table, the addition signal L1 is "0" and the subtraction signal L2 is "
1”. After this, in the process of A → mouth, the node signal becomes greater than zero as shown in FIG. 2, and the comparison signal J1 becomes "1", so the addition signal L1 and subtraction signal L2 are inverted as shown in FIG. 3. When the clock pulse CP is input here, the UP counting pulse is output. This is input to the DN terminal of the ring counter 50, so the output of the ring counter 50 is that terminal 2 is "1".
As shown in Figure 2, since the node signal is less than zero, the addition signal L1 becomes "0" and the subtraction signal L2 becomes "1", but when the displacement reaches the mouth, the addition signal L1 and subtraction signal L2 are inverted again. Therefore, up'tF number pulses are output, and the output of the ring counter 50 rotates to terminal 1. On the contrary, when the displacement is from mouth to a, a DOWN counting pulse is output, and the head of the ring counter 50 rotates from 1 to 2-3. Next, when stopped at A, the comparison signal L1 becomes "0" because the node signal crosses zero as shown in Fig. 2A every time the output of the ring counter 50 switches between terminals 3 and 4. "1
'' is repeated, and it can be seen that the UP counting pulse and the DOWN counting pulse are output alternately. The pulses in section A of FIG. 3 indicate alternating pulses at the time of stop. Since these pulses are not integrated in the counter, the counting error is less than one pitch of the counting pulse. After this, when the primary signal changes from A to C, a DOWN counting pulse is output in the same way (an UP counting pulse may be output depending on the timing), and the output of the ring counter 50 is also output from the terminal. Rotates 3-4→...-8. Here, when the DOWN counting pulse is further output and the output of the ring counter 50 rotates from terminal 8 to terminal 1, the direction reversal circuit 44 shown in FIG.
As shown by 1 in the figure, the signal level becomes "0". At this position, as shown in Fig. 2, the node signal is greater than zero and the comparison signal J1 is "1", but the inverted signal K is "0". Therefore, from the truth table, the addition signal L1 is "0" and the subtraction signal L2 is "1".
Then, a DOWN counting pulse is output by inputting the clock pulse CP. Therefore, when there is no inversion signal K, the ring counter 5
It can be seen that when the output of 0 rotates from 8 to 1, an UP counting pulse is output, resulting in erroneous counting. This is the same when the output of the ring counter 5o rotates from terminal 1 to terminal 8 due to the input of the UP counting pulse, and the inverted signal K
can be seen to play an important role. Furthermore, since one counting pulse is output every time the phase changes by 180'/8, it can be seen that the counting pulse is divided into 16 in total. Next, consider a case where the digit 40 of the primary signal instantaneously changes by about 90 degrees. In this case, a counting pulse is output every time the clock pulse CP is input, and the ring counter 50
It can be seen that the counting can be followed by simply rotating the output of the comparator 42 and continuing until the output of the comparator 42 is inverted. However, if the instantaneous change exceeds 180°, it will not be possible to follow it. Furthermore, it can be seen that the response speed is permissible up to the frequency of the clock pulse CP. In this first embodiment, the comparator 42 has a minimum a
Since there is only one piece, it is particularly suitable for IC implementation. Also, analog switches 40A to 40H are MOS type FETs.
Since it is composed of , it is optimal for IC, and even if the number of divisions is about 100, it will not become so large. Furthermore, a servo circuit consisting of an octal ring counter 50 feeds back the count signal to the analog switches 40A to 40A.
40H, it is possible to follow instantaneous changes in the primary signal, and the response speed can be tolerated up to the frequency of the clock pulse CP. In addition, in this first embodiment, the tJP counting pulse and the DOWN counting pulse are output alternately even when the motor is stopped.
FIG. 4 shows an example of a damper circuit that is added to the output side of the dividing circuit 12 to remove this. This damper circuit 60 uses an R-S flip-flop 60A with a negative logic input and an edge trigger.
S flip-flop 60A, an AND gate 60B that outputs the logical product of the output of the terminal Q of the R-S flip-flop 60A and the UP counting pulse as a new UP counting pulse UP', and Terminal Q
Renew the logical result of the output of OW and the DOWN counting pulse.
AND gate 6 outputs as N counting pulse DOWN'
It is composed of 0C. The action of this damper circuit 60 is as shown in FIG.
When UP counting pulses and DOWN counting pulses are input alternately when stopped, the R-S flip-flop 60A repeats setting and resetting at the falling edge of the pulse, so the alternating pulses are removed on the output side. I know that there is. When this damper circuit 60 is added to the output (11') of the dividing circuit 12 of the first embodiment, it is possible to prevent the counting pulses from being outputted alternately when the circuit is stopped. As a second embodiment, an example of a dividing circuit that outputs a count signal obtained by dividing the pitch of the detection signal (primary signal) into eight is shown in Fig. m6. Buffer amplifier 2 inverts the output of buffer amplifier 2OA
In addition to 2A, a buffer amplifier 22B that inverts the output of the buffer amplifier 20B is added, and A sin
θ, A COS θ, -A s"in θ, -A cos θ 41ffl signals are applied to the resistance chain 16, and A sin θ is applied to two nodes, and
The difference from the first embodiment is that two comparators (42A, 42B) are provided, and a 3-bit reversible binary counter 62 and a decoder 64 are used as the servo circuit. Since it is sufficient to divide 90° into two, the resistance values of the resistance chains fii 16 are all set to the same value R. Furthermore, the direction reversing circuit of the first embodiment is omitted. The signal at the node is Oo, 45°,・
...Since the change is 360° = 0°, the decoder 64
This is because the phase does not change even when the output is switched from terminal 8 to terminal 1, and there is no need to send a phase inversion signal to direction discrimination circuit 66. Also, since the outputs of the comparators 42A and 42B are pulled down to 1, even if the analog switches 40A to 40H are not selected, the comparison signals J1 and J2 will be "0".
Therefore, in the direction discrimination circuit 66, the AND of the comparison signals J1 and J2 is performed, and the result is "1" or "0".
By setting the addition signal L1 or the subtraction signal L2 to "1" in accordance with the above, an UP counting pulse or a DOWN counting pulse, which is a counting signal, is obtained. In each of the above embodiments, the primary signals are two-phase signals with a phase difference of 90 degrees, but the number of primary signals and the phase difference are not limited to this, and may be two or more phases. . Further, although the number of divisions was 16 in the first embodiment and 8 in the second embodiment, the number of divisions is not limited to these, and may be H divisions of 2 or more. Furthermore, in the above embodiments, the primary signal is a sine wave, but the shape of the primary signal is not limited to this.
For example, the shape may be a triangular wave or a trapezoidal wave, etc. If the shape is different like this, the resistance value of the resistance chain is yJ
This can be easily handled by using ilB. [Effects of the Invention] As explained above, according to the present invention, a plurality of nodes of a resistance chain are inputted to a smaller number of comparators than the nodes through analog switches, so that the number of comparators is It is particularly suitable for IC implementation. In addition, since the counting signal is fed back by the servo circuit to select the analog switch, it has excellent effects such as being able to follow instantaneous changes in the primary signal and improving response speed. have

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram showing the configuration of a first embodiment of a dividing circuit of a measuring device according to the present invention, and FIG. 2 is a line diagram showing an example of a signal waveform at each node of a resistance chain in the first embodiment. 3 are diagrams showing examples of signal waveforms of each part in the first embodiment,
FIG. 4 is a circuit diagram showing the configuration of a damper circuit suitable for addition to the first embodiment, FIG. 5 is a diagram showing examples of signal waveforms of each part of the damper circuit, and FIG. A circuit diagram showing the configuration of a second embodiment of the invention, FIG. 7 is a block diagram showing an example of the overall configuration of a measuring device to which the invention is applied, and FIG. 8 is a dividing circuit using a resistance chain. Circuit diagram showing the principle of
The figure is a circuit diagram showing an example of a conventional resistance divider circuit. 10...Detector, 12...Division circuit, 14...Counter, 16...Resistance chain, a-h...Node, 32...Oscillator, CP...Clock pulse, 40A~ 40H...Analog switch, 42.42A
, 42B... Comparator, Jl, J2... Comparison signal, 50... Octal ring counter, Ll... Addition signal, L2... Subtraction signal, 62... 2! ! Counter, 64...decoder.

Claims (2)

[Claims] (1) Apply multi-phase primary signals with different phases to different nodes of a resistance chain to generate phase-shifted secondary signals at other nodes, and connect these nodes of the resistance chain with corresponding comparators. Each node of the resistance chain is connected in a dividing circuit of a measuring device that outputs a counting signal with a finer pitch than the primary signal by comparing the primary or secondary signal with a reference level. , connected to a smaller number of comparators than the nodes via analog switches, obtains a count signal synchronized with the clock pulse according to the output delay of the comparator, and feeds back the count signal to select the analog switch. A dividing circuit for a measuring device characterized by being provided with a switching servo circuit. (2) A dividing circuit for a measuring device according to claim 1, wherein one comparator is shared as the comparator.