JPH067059B2 - Dividing circuit of measuring device - Google Patents

Description

Detailed Description of the Invention [Industrial applications]

The present invention relates to a division circuit of a measuring device, and in particular, is suitable for use in a measuring device that converts a linear displacement or an angular displacement into an electric signal by a detector to electrically measure a relative displacement amount,
By applying multi-phase primary signals with different phases to different nodes of the resistance chain to generate secondary signals with different phases at other nodes, connect the nodes of these resistance chains to the corresponding comparators. The present invention relates to an improvement of a dividing circuit of a measuring device which outputs a count signal which is finer in pitch than the primary signal by comparing the primary signal or the secondary signal with a reference level.

2. Description of the Related Art In a wide range of fields from machine tools, measuring machines to portable electronic measuring machines, such as a linear displacement measuring machine shown in FIG. 7, a detector 10 periodically changes according to a relative displacement. A measuring device capable of digitally measuring a relative displacement amount by outputting a layer detection signal (primary signal), processing the signal to generate a count signal containing forward / backward information, and inputting the count signal to the counter 14. It is popular. In this measuring device,
Usually, since the resolution of the primary signal pitch is coarse, the division circuit 12 is used to obtain the subdivided count signal of the pitch. As such a dividing circuit 12, for example, a dividing circuit using a resistance chain as shown in Swiss Patent No. 407569 is well known. In principle, this division circuit has a resistance chain 1 composed of resistors R1 and R2, as shown in FIG.
For example, A sin θ, A c as primary signals at the nodes at both ends of 6
When the signal approximated by osθ (= A sin (θ + 90 °)) is applied, it is utilized that the signal approximated by A ′ sin (θ + α) is generated from the central node. Here, the amplitude A ′ and the phase difference α of the combined secondary signal are respectively expressed by the following equations. α = arc tan (R1 / R2) (2) That is, by selecting the resistance values R1 and R2, the phase difference α can be set to an arbitrary value from 0 ° to 90 °, and A sin
A signal having an arbitrary phase between θ and A cos θ is obtained. Therefore, by outputting the count signal when this signal crosses the zero level, a subdivided pitch count signal can be obtained. If the detection signal is not a sine wave, the resistance value can be changed accordingly to obtain a signal with an arbitrary phase. FIG. 9 shows an example of a conventional resistance division circuit capable of dividing the pitch of the primary signal into 16 parts. In the figure, 20A
Is a buffer amplifier for the primary signal A sin θ, and 20B is 1
A buffer amplifier for the next signal A cos θ, 22 is an inverting amplifier for applying a signal −A sin θ obtained by inverting the output of the buffer amplifier 20 A to the contact point of the resistor chain 16, 24 A to 24 A
H is a total of eight comparators provided corresponding to each node of the resistance chain 16, 26 is a reference voltage setter for supplying a reference voltage Vr for comparison to each comparator, and 28A to 28F are The comparators 24A-24
An exclusive OR gate for combining the outputs of H, 30 is
The direction discrimination circuit, 32 is an oscillator. In this division circuit 12, resistors R1, R2, R3,
The values of R4 are set to the ratio of 1: 0.707: 0.707: 1, respectively, and 180 ° is divided into 8 parts, so that 360 ° is divided into 16 parts. This resistance divider circuit is described in Swiss Patent No. 40756.
The detailed description is omitted because it is disclosed in detail in the specification No. 9.

[Problems to be Solved by the Invention]

However, in the conventional resistance division circuit shown in FIG. 9, each node of the resistance chain 16 and the comparators 24A to 24A.
Since 24H is connected 1: 1, N comparators are generally required to divide the primary signal pitch by 2N, and the number of comparators increases in proportion to the number of divisions. Therefore, the entire circuit including the comparator is integrated circuit (I
In the case of C), the characteristics of the comparator such as the potential difference between the comparison input signal and the reference level when the output of the comparator is inverted are likely to vary, and the response speed deteriorates. Furthermore, since it is necessary to individually add a hysteresis setting resistor for preventing oscillation to the comparator, the size of the integrated circuit becomes larger than that of other circuits even when it is integrated. Therefore, especially when the number of divisions becomes large, the entire IC becomes large. There were problems such as. In addition to the IC, a circuit in which a large number of comparators are provided in parallel has a problem that the response speed is poor, such as erroneous counting when the primary signal changes instantaneously. In order to solve such a problem, the applicant has already filed Japanese Patent Application No. 61-257546 (Japanese Patent Application Laid-Open No. 63-111141).
7) and Japanese Patent Application No. 61-259518 (Japanese Patent Publication No. 4-390)
18) is proposed, and by adopting the servo system,
Although the response speed about twice as high as the conventional one, that is, almost the same as the theoretical response speed is achieved, there are cases where it is desired to further improve the response speed depending on the application.

[Object of the Invention]

The present invention has been made in order to solve the above-mentioned conventional problems. The number of comparators is reduced, which is suitable for an IC, and the response speed is further improved, so that the primary signal can be reliably changed. An object of the present invention is to provide a division circuit of a measuring device that can follow.

[Means for solving problems]

According to the present invention, two-phase primary signals having different phases are applied to different nodes of a resistance chain, and phase shifts to another node.
A secondary signal is generated, and the nodes of these resistance chains are connected to the corresponding comparators to compare the primary signal or the secondary signal with a reference level to obtain a count signal which is finer in pitch than the primary signal. In a division circuit of a measuring device that outputs a plurality of analog switches connecting each node of the resistance chain to at least one comparator, and a direction for obtaining an up or down direction signal according to the output of the comparator. A discriminating circuit, a servo circuit for selecting the analog switch in a predetermined order in synchronization with the clock pulse in response to the direction signal, and a phase change of the primary signal becomes fast, and a zero-cross point of the primary signal When a predetermined delay occurs in the number of the analog switch selected by, or when the direction signal continues for a predetermined interval, the clock pattern By providing an acceleration detecting circuit for outputting a signal for switching the scan speed, it is obtained by achieving the above object.

[Action]

According to the present invention, in a dividing circuit of a measuring device, each node of a resistance chain is connected to at least one comparator via an analog switch, and a direction discriminating circuit outputs an up or down direction signal according to an output of the comparator. And the servo circuit corresponding to the direction signal selects the analog switch in a predetermined order in synchronization with the clock pulse, and when the phase change of the primary signal becomes high,
A signal for switching the clock pulse at high speed is output from the acceleration detection circuit. Therefore, not only is the number of comparators reduced to suit ICs, but when the phase change of the primary signal becomes faster, the switching speed of the analog switch is correspondingly increased, so the reaction speed is further improved. To be done. Further, when the acceleration detecting circuit is configured to output the switching signal when the analog switch number selected at the zero-cross point of the primary signal has a predetermined delay, the acceleration state is accurately determined. Can be detected. Alternatively, when the acceleration detection circuit is configured to output the switching signal when the direction signal continues for a predetermined interval, the configuration of the acceleration detection circuit is simple.

【Example】

Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. The first embodiment of the present invention is one in which the present invention is applied to a dividing circuit for generating a counting pulse obtained by dividing the phase 2π of a primary signal into 20. As shown in FIG. , 20B and the inverting amplifier 22, a total of 10
In the division circuit 12 having the resistance chain 16 including the resistors R1 to R5 and the reference voltage setting unit 26, two adjacent nodes of the resistance chain 16 are provided with two comparators 42A,
A pair of two analog switch pairs 40A to 40J for connecting to 42B sequentially, and a direction signal of up UEN or down DEN indicating the counting direction of the counting pulse according to the outputs of the comparators 42A and 42B. And a servo circuit 50 for selecting the analog switch pairs 40A to 40J in a predetermined order in synchronization with the counting clock pulse CP3 or CP2 in response to the direction signals UEN and DEN. Clock pulse types CP1 (for control), CP2 (for high-speed counting), CP3
(For resistance counting) is input, the phase change of the primary signal becomes fast, and a clock pulse C for slow (normal) counting is input.
When it becomes impossible to follow at P3, an acceleration detection circuit 52 that outputs an alarm signal AL for switching the clock pulse to the high-speed counting clock pulse CP2, and a clock pulse CP3 according to the output signal AL of the acceleration detection circuit 52.
Or a clock pulse selection circuit 54 for selecting CP2,
A count pulse generation circuit 56 for generating count pulses UP and DN by the output of the clock pulse selection circuit 54 and the output of the direction discrimination circuit 46 is provided. As the detection signal (primary signal) input from the detector,
There may be a signal close to a triangular wave or a trapezoidal wave, but for the sake of convenience, the description will be made assuming that it is approximated by a sine wave and the phase difference is also 90 °. Therefore, from the detector, A sin θ (= φA), A
It is considered that a primary signal of sin (θ + 90 °) = A cos θ (= φB) is input to the division circuit 12. Here, θ is a phase corresponding to the displacement. The primary signals φA and φB input from the detector are input via buffer amplifiers 20A and 20B, respectively.
From, the phase is further shifted by 180 ° by the inverting amplifier 22 1
The next signal A sin (θ + 180 °) = − A sin θ is generated. The resistance chain 16 is composed of a total of 10 resistors,
The primary signal is applied to three nodes a, f, k. Regarding the resistance values of the resistors R1 to R5, the phase of the secondary signal generated at the other nodes b to j is 180 ° / 10 = from the node a.
It is set to gradually shift by 18 °. When the primary signal changes in response to the displacement of the object to be measured, the secondary signal accordingly changes with a phase shift. In this embodiment, since the phase difference of 180 ° is divided into 10 equal parts, 360 °
Will be divided into 20 equal parts, and 20 divisions will be achieved. If the detection signal is not a sine wave, it can be dealt with by adjusting the resistance value. The nodes a to k of the resistance chain 16 are connected through 10 sets of analog switch pairs 40A to 40J correspondingly provided,
The comparator 42A for each combination of adjacent nodes,
It is input to one input terminal of 42B. The reference voltage Vr is applied from the reference voltage setter 26 to the other input terminal of each of the comparators 42A and 42B. Further, in this embodiment, comparators 42C and 42D to which the primary signals φA and φB are directly connected are provided,
The same reference voltage Vr is applied from the reference voltage setting device 26 to the comparators 42C and 42D. The outputs a and b of the two attached comparators 42C and 42D are input to the acceleration detection circuit 52 together with the count signals (internal count values) A, B, C, D and E of the servo circuit 50. There is. The analog switch pairs 40A-40J are connected to the output of the decoder 50A of the servo circuit 50. When a counting pulse is input to the decoder 50A, "1" is generated at the corresponding output terminal. Therefore, only one analog switch pair is selected at any one time and is in a conductive state.
The other analog switch pair in the non-selected state is in a high input resistance state, that is, in a state where the connection is considered to be disconnected. For example, when the terminal 0 of the decoder 50A is "1",
When the analog switch pair 40A is selected and becomes conductive, the signal at the node a is input to the comparator 42A and the signal at the node b is input to the comparator 42B, and when these signals are both smaller than the reference level Vr, the comparator 42A
The comparison signals J1 and J2 of the outputs A and 42B are both "1". The direction discriminating circuit 46, when the output signal E of the servo circuit 50 is at "0" level, the comparators 42A and 42A.
When the output signals J1 and J2 of B both become "1", it acts so that the up direction signal UEN becomes "1".
Further, when both the signals J1 and J2 become "0", the down direction signal DEN is made to be "1". on the other hand,
When the signal E is at "1" level, the direction signals UEN, D
Create a signal with EN switched. Otherwise,
The bidirectional signals UEN and DEN are both set to "0" level. The bidirectional signals UEN and DEN are latched at the timing of the control clock pulse CP1. As shown in FIG. 1, the servo circuit 50 includes a decoder 50A whose output terminals are connected to the analog switch pairs 40A to 40J, and a clock pulse CP3 for counting the direction signals UEN and DEN output from the direction discrimination circuit 46. C
P2 counts and the decoder 50A counts the count signal A,
BCD counter 50B for inputting B, C and D, and the BC
It is composed of a binary counter 50C which cooperates with the D counter 50B to generate a counting signal E. This BC
The D counter 50B counts up or counts down in synchronization with the counting clock pulse CP3 or CP2 in accordance with the direction signals UEN and DEN fed from the direction discriminating circuit 46, and becomes 2 when the count value reaches 10.
It sends an up pulse to the advance counter 50C, while BC
When the count value of the D counter 50B is zero, the binary counter 5
Subtract 1 from 0C. The count value of the BCD counter 50B becomes one value between 0 and 9 in the decoder 50A, only one corresponding analog switch pair 40A to 40J is selected, and the adjacent node of the resistor chain 16 and the comparator 42 are selected.
A and 42B are connected. As shown in detail in FIG. 2, the acceleration detection circuit 52 receives a D-flip flip (F / F) to which the output a of the comparator 42C and the normal clock pulse CP1 are input.
52A, a D-F / F 52B to which the output b of the comparator 42D and the normal clock pulse CP1 are input.
And the D-F / F52C to which the output of the D-F / F52A and the high-speed counting clock pulse CP2 are input,
-F / F52B output and high speed counting clock pulse CP
D-F / F52D to which 2 is input, and the D-F / F5
An AND gate 52E which outputs a negative logical product of the output a1 of 2A and the output of DF / F 52C, and conversely DF / F5
An AND gate 52F for outputting a logical product of the negation of the output a1 of 2A and the output of the DF / F 52C, and the DF / F5.
An AND gate 52G that outputs a negative logical product of the output b1 of 2B and the output of D-F / F 52D, and conversely D-F / F5
An AND gate 52H that outputs the logical product of the output b1 of 2B and the D-F / F 52D, an output a1 of the D-F / F 52A, an output b1 of the D-F / F 52B, the AND gates 52E, 52F, 52G. , 52H zero cross outputs AR, AF, BR, BF, and the internal count value input from the servo circuit 50, there is a predetermined delay in the number of the analog switch pair selected at the zero cross point of the primary signal. Discrimination decoder 52I for discriminating whether or not, DF / F for outputting alarm signal AL to which the output P of discrimination decoder 52I and low-speed counting clock pulse CP3 are input
It consists of F52J. The truth table of the discrimination decoder 52I is as shown in Table 1 below. To facilitate understanding of this truth table, the primary signal φA,
FIG. 3 shows the relationship between the phase θ of φB and the count value (internal count value) in the servo circuit 50. In FIG. 3, when the phase θ is stationary at point P, for example, the internal count value is 9, and the analog switch pair 40J at the lowest stage is stable and the output of the direction discriminating circuit 46 is bidirectional. Signals UEN, D
Both EN are zero. Also, when the phase θ moves to the Q point,
The internal count value becomes 10, the output of the decoder 50A is 0, and the uppermost analog switch pair 40A is selected. For example, in the column i of the truth table, the input (output of the DF / F 52B) b1 of the discrimination decoder 52I is “1” and the same is input (output of the AND gate 52F) AF.
Is "1", and shows the state in which the phase has changed from point P to point Q in FIG. At this time, originally, the internal count value should be 9 or 10, but when the count value of 5 to 15 cannot be followed and the alarm signal AL is set to "1". In short, at the zero-cross point of the primary signal,
When the internal count value, that is, the number of the selected analog switch pair is delayed from the predetermined number, the alarm signal AL is output. Other than this, the alarm signal AL is "0" in the lowermost column l showing the combination except the upper three columns of the truth table. The counting pulse generating circuit 56 outputs the counting clock pulse CP3 or CP2 selected by the clock pulse selecting circuit 54 and the direction signal U output from the direction discriminating circuit 46, respectively.
It is composed of two AND gates 56A and 56B for outputting a logical product with EN and DEN as counting signals UP and DN, and up or down counting pulses UP and D synchronized with the clock pulse selected by the clock pulse selecting circuit 54.
Output N. The operation of the embodiment will be described below. FIG. 4 shows a timing chart when the phase θ of the primary signal increases clockwise from zero in FIG. 3 described above. In the initial state, a clock pulse C for low speed (normal) counting
P3 is selected. When the primary signal changes faster than the clock pulse CP3 and the phase θ moves from the point R to the point S in FIG. 3, the zero-cross signal r is output, but the internal count value is 2, and j in Table 1 is used.
Since the column does not match, the alarm signal AL does not become "1". Therefore, the UP counting pulse remains synchronized with the clock pulse CP3 for low speed counting. Next, when the phase θ shifts from the point P in FIG. 3 to the point Q, the zero-cross signal p (AF) is output, and the first internal count value is 3
The alarm signal AL is "1" because it matches the condition in column k of the table.
Becomes Therefore, the clock pulse selection circuit 5 of FIG.
The clock pulse CP2 for high speed counting is selected in 4 and U
The P counting pulse is recovered in synchronism with the clock pulse CP2. In this embodiment, when the analog switch number selected at the zero-cross point of the primary signal has a predetermined delay, the alarm signal AL is output and the clock pulse is switched at high speed. The state in which the clock pulse CP2 is required can be accurately determined. Next, a second embodiment of the present invention will be described in detail. In the second embodiment, as shown in FIG. 5, the acceleration detection circuit 60 is provided with a D-F / F to which the direction signal UEN output from the direction discrimination circuit 46 and the low-speed counting clock pulse CP3 are input.
60A, a D-F / F 60B to which the direction signal DEN and the clock pulse CP3 are input, and a D-F / F6 to which the output of the D-F / F 60A and the clock pulse CP3 are input.
0C, the D-F / F 60D to which the output of the D-F / F 60B and the clock pulse CP3 are input, and the direction signal UE
3-input AND gate 60E for outputting a logical product of the outputs of N, DF / F 60A, 60C, and direction signals DEN, D-
3-input AND gate 60F for outputting a logical product of outputs of F / Fs 60B and 60D, and AND gates 60E and 60F
The OR gate 60G for outputting the logical sum of the outputs of the OR gate and the D-F / F 60H for receiving the output of the OR gate 60G and the clock pulse CP3 and outputting the alarm signal F. In this acceleration detection circuit 60, the direction signals UEN and DEN output from the direction discriminator circuit 46 are the clock pulses CP for low speed counting.
The alarm signal F is output when the level is "1" for three consecutive times of three or more. Accordingly, if three consecutive up or down counting pulses are output in synchronization with the clock pulse CP3, it is regarded as overspeed, and the alarm signal F
Will be output. FIG. 6 shows a timing chart of the acceleration detection circuit 60. When the phase θ of the primary signal changes at high speed and the normal slow clock pulse CP3 for low speed counting cannot synchronize, the direction signal UEN is continuously set. The level becomes “1” or higher than the pulse, and the alarm signal F becomes “1”. Therefore, the first
The clock pulse selecting circuit 54 in the figure selects the high-speed counting clock pulse CP2 and outputs a high-speed clock pulse. Since the other points are the same as those in the first embodiment, the description thereof will be omitted. In the second embodiment, the discrimination decoder 52I of the first embodiment is unnecessary and the structure of the acceleration detecting circuit is simple. In the above embodiment, switching of the analog switch pair was carried out sequentially, but the clock pulse CP for high speed counting was used.
When 2 is selected, for example, skip 3 pairs and 4
It is also possible to select for each pair of eyes. Although the decoder 50A is used for the servo circuit 50 in the above embodiment, a ring counter may be used instead. Further, in the above-mentioned embodiment, the present invention uses the servo circuit to connect the adjacent nodes of the resistance chain as proposed by the applicant in Japanese Patent Application No. 61-259518 (Japanese Patent Publication No. 4-39018).
Although the present invention has been applied to a dividing circuit in which the comparators are sequentially connected, the scope of application of the present invention is not limited to this, and the applicant of the present invention has applied it to Japanese Patent Application No. 61-257546 (Japanese Patent Laid-Open No. 63-257546).
It is apparent that the present invention can be similarly applied to a division circuit in which each node of the resistance chain is individually connected to one or two comparators by a servo circuit as proposed in (111417).

【The invention's effect】

As described above, according to the present invention, the number of comparators can be made smaller than the number of nodes of the resistance chain, and particularly I
Suitable for C conversion. Further, the response speed is further improved, and even if the primary signal changes abruptly, it can be reliably followed. Further, it has an excellent effect that it can follow a rapid phase change of the primary signal exceeding the switching frequency of the analog switch pair determined by the response speed of the comparator and the direction discriminating circuit.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing an overall configuration of a first embodiment of a division circuit of a measuring device according to the present invention, and FIG. 2 is a circuit diagram showing a configuration of an acceleration detection circuit used in the first embodiment. 3, FIG. 3 is a diagram for explaining the operation of the first embodiment, FIG. 4 is the same timing chart, and FIG. 5 shows the acceleration detection circuit used in the second embodiment of the present invention. FIG. 6 is a circuit diagram showing the configuration, FIG. 6 is a timing chart for explaining the operation of the second embodiment, and FIG. 7 is a block diagram showing an example of the overall configuration of the measuring apparatus to which the present invention is applied. FIG. 8 is a circuit diagram showing the principle of a division circuit using a resistance chain, and FIG. 9 is a circuit diagram showing an example of a conventional resistance division circuit. 10 ... Detector, 12 ... Division circuit, 14 ... Counter, 16 ... Resistance chain, ak ... Node, CP1-CP3 ... Clock pulse, 40A-40J ... Analog switch pair, 42A, 42B ... Comparator, 46 ... Direction discrimination circuit , UEN, DEN ... Direction signal, 50 ... Servo circuit, 52, 60 ... Acceleration detection circuit, 54 ... Clock pulse selection circuit, AL, F ... Alarm (switch) signal.

Claims (2)

[Claims] 1. A multiphase primary signal having a different phase from each other is applied to a node having a different resistance chain to generate a secondary signal having a phase shift to another node, and the nodes of the resistance chain are associated with each other. In a division circuit of a measuring device, which is connected to a comparator and outputs a count signal which is finer in pitch than the primary signal by comparing the primary signal or the secondary signal with a reference level, each of the resistance chains A plurality of analog switches whose nodes are connected to at least one comparator, a direction discriminating circuit for obtaining an up or down direction signal according to the output of the comparator, and the analog signal corresponding to the direction signal. A servo circuit that selects a switch in a predetermined order in synchronization with a clock pulse, and a phase change of the primary signal becomes fast, and the switch is selected at a zero cross point of the primary signal. A division circuit for a measuring device, comprising: an acceleration detection circuit for outputting a signal for switching the clock pulse at a high speed when a predetermined delay occurs in the analog switch number. 2. A multi-phase primary signal having a different phase from each other is applied to a node having a different resistance chain to generate a secondary signal having a phase difference at another contact, and the nodes of the resistance chain are associated with each other. In a division circuit of a measuring device, which is connected to a comparator and outputs a count signal which is finer in pitch than the primary signal by comparing the primary signal or the secondary signal with a reference level, each of the resistance chains A plurality of analog switches whose nodes are connected to at least one comparator, a direction discriminating circuit for obtaining an up or down direction signal according to the output of the comparator, and the analog signal corresponding to the direction signal. A servo circuit that selects a switch in a predetermined order in synchronization with a clock pulse; and when the phase change of the primary signal becomes fast and the direction signal continues for a predetermined interval, A division circuit of a measuring device, which is provided with an acceleration detection circuit that outputs a signal for switching a lock pulse at high speed.