JPS63113312A - Dividing circuit of measuring device - Google Patents

Abstract

PURPOSE:To reduce the number of comparators, by constituting the title circuit so that the nodal points of a resistor linkage are inputted to two comparators through analogue switches. CONSTITUTION:In the dividing circuit of a measuring device, the nodal points a-i of a resistor linkage 16 are connected to at least one of two comparators 42A, 42B through analogue switches 40A-40P. When the outputs of two comparators 42A, 42B are simultaneously at a high level or a low level, the count signal synchronous to a clock pulse CP is obtained and fed back. Then, an octal ring counter 50 is provided as a servo circuit successively selecting analogue switches 40A-40P connecting the adjacent nodal points a-i to the comparators 42A, 42B different from each other two at a time. By the above- mentioned constitution, the number of the comparators are reduced and this constitution is suitable for forming IC.

Description

[Detailed description of the invention] [Industrial application field]

The present invention relates to a dividing circuit for a measuring device, and is particularly suitable for use in a measuring device that electrically measures the amount of relative displacement by converting linear displacement or angular displacement into an electrical signal using a detector.
Two primary signals with different phases are applied to different nodes of a resistance chain to generate a secondary signal with a phase shift at another node, and these nodes of the resistance chain are connected to corresponding comparators. The present invention relates to an improvement in a dividing circuit of a measuring device that outputs a count signal whose pitch is finer than that of the primary signal by comparing the primary signal or the secondary signal with a reference level.

[Conventional technology]

In a wide range of fields such as machine tools, measuring instruments, and portable electronic measuring instruments, for example, the linear displacement measuring machine shown in FIG. The counter 14 outputs a signal (primary signal) and processes the signal to generate a count signal including forward/reverse information.
Measuring devices that can digitally measure the amount of relative displacement by inputting the information into the data are now in widespread use. In this measuring device, since the pitch of the primary signal usually has a coarse resolution, a dividing circuit 12 is used to obtain count signals of finely divided pitches. As the dividing circuit 12, for example, Swiss Patent No. 4075
Divider circuits using resistive chains are well known, as shown in US Pat. In principle, this dividing circuit, as shown in FIG. 6, sends primary signals such as A sin θ, A COS to nodes at both ends of a resistance chain 16 consisting of resistors R1 and R2.
When a signal approximated by θ (=A 5in (θ+90°)) is applied, the signal approximated by A′5in (θ+a
) is used to generate a signal approximated by Here, the amplitude A' and phase difference α of the synthesized secondary signal are expressed by the following equations. A'=Ar "D2 +R22/ (R1+R2)...
・・・・・・(1) a=arctan(R1/R2) --------
--(2) That is, by selecting the resistance values R1 and R2, the phase difference α
can be set to any value from O@ to 90°, resulting in a signal with any phase between A sin θ and A COS θ. Therefore, by outputting a count signal when this signal crosses the zero level, a count signal of subdivided pitches can be obtained. Note that when the detection signal is not a sine wave, a signal with an arbitrary phase can be obtained by changing the resistance value accordingly. FIG. 7 shows an example of a conventional resistance divider circuit that can divide the pitch of the primary signal into 16.
is a buffer amplifier for the primary signal A sin θ, 20B is a buffer amplifier for the primary signal A CO3θ, and 22 is a signal −A sin obtained by inverting the output of the buffer amplifier 20A.
an inverting amplifier for applying θ to the nodes of the resistance chain 16;
24A to 24H are a total of eight comparators provided corresponding to each node of the resistance chain 16; 26 is a reference voltage setting device for supplying a reference voltage vr for comparison to each comparator; 28A to 24H; 28F is an exclusive OR gate for combining the outputs of the comparators 24A to 24H, 30 is a direction discrimination circuit, and 32 is an oscillator. In this dividing circuit 12, resistors R1, R2, R3,
The values of R4 are 1:0.707:0.707:
Since the ratio is set to 1 and 180° is divided into 8, 360° is divided into 16. This resistor divider circuit is disclosed in Swiss Patent No. 40756.
Since it is disclosed in detail in No. 9 M'8, detailed explanation will be omitted.

[Problems that the invention attempts to solve]

However, in the conventional resistance divider circuit shown in FIG.
Since 24H are connected in a manner that 1=1, generally when dividing the pitch of the primary signal by 2N, N comparators are required, and the number of comparators increases in proportion to the number of divisions. Therefore, the entire circuit including the comparator is integrated circuit (IC).
), the characteristics of the comparator, such as the potential difference between the comparison input signal and the reference level when the output of the comparator is inverted, tend to vary, and the response speed deteriorates. Furthermore, it is necessary to add a hysteresis setting resistor to each comparator to prevent oscillation, so even if it is integrated, it will be larger compared to other circuits. , 111k, the overall IC becomes larger. In addition to IC implementation, circuits in which many comparators are arranged in parallel also have the problem of poor response speed, such as erroneous counting when the primary signal changes instantaneously.

[Purpose of the invention]

The present invention has been made to solve the above-mentioned conventional problems, and is suitable for engineering C by reducing the number of comparators, and improves response speed so that even if the primary signal changes instantaneously, it can be followed. It is an object of the present invention to provide a dividing circuit for a measuring device that can be used in a measuring device and that also prevents a meaningless count signal from being output when the phase of a primary signal does not change.

[Means to solve the problem]

The present invention applies multi-phase primary signals with mutually different phases to different nodes of a resistance chain, and applies two phase-shifted primary signals to another point.
By generating secondary signals and connecting the nodes of these resistance chains with corresponding comparators to compare the primary or secondary signals with a reference level, a counting signal with a finer pitch than the primary signal can be generated. In the dividing circuit of the measuring device, each node of the resistance chain is connected via an analog switch to at least one of the two comparators, so that the outputs of the two comparators are simultaneously at a high level or Obtaining a count signal synchronized with the clock pulse when the level is low, and feeding back the count signal to sequentially select two analog switches each connecting adjacent nodes to different comparators among the analog switches. By providing a servo circuit to
The above objective has been achieved. Further, in an embodiment of the present invention, the resistor 3! ! ! Each node of M is connected to two comparators via an analog switch. Furthermore, in another embodiment of the invention, each node of the resistance chain is alternately connected to a different comparator via an analog switch.

[Effect]

The present invention provides that in the dividing circuit of the measuring device, each node of the resistance chain is connected to at least one of the two comparators via an analog switch, so that the outputs of the two comparators are simultaneously at a high level or When the level is low, a count signal synchronized with the clock pulse is obtained, and the count signal is fed back to sequentially connect two analog switches, each of which connects adjacent nodes of the analog switches to different comparators. A servo circuit is provided for selection. Therefore, the number of comparators is reduced, making it suitable for IC implementation. Furthermore, even if the primary signal changes instantaneously, it can be tracked and the response accuracy is improved. Furthermore, if the order 1f of the primary signal does not change, meaningless counting signals will not be output. Furthermore, if each node of the resistance chain is connected to two comparators via an analog switch, the configuration of the servo circuit is simple. Alternatively, if each node of the resistance chain is alternately connected to different comparators via an analog switch, processing at the time of direction reversal is easy.

【Example】

Embodiments of the present invention will be described in detail below with reference to the drawings. The first embodiment of the present invention is an application of the present invention to a 16-division division circuit similar to the conventional example, and as shown in FIG. 22 amplifiers and 3 resistors! ! In a dividing circuit 12 having a chain 16, a reference voltage setter 26, and an oscillator 32, each node a-h of the resistance chain 16 is connected to two comparators 42A, 42B, and the comparator 4
When the comparison signals J1 and J2 of the outputs of 2A and 42B are simultaneously at high level or low level, the direction reversing circuit 114,
The direction discrimination circuit 46, AND gates 48A, 48B, and latch circuit 48C generate counting signals (UP counting pulse and D
OWN counting pulses) and feeding back the counting signal to the analog switches 40A to 40P.
An octal ring counter 5 as a servo circuit that sequentially selects two analog switches each connecting adjacent nodes to different comparators 42A and 42B.
0 is set. The detection signal (primary signal) input from the detector is:
There may be signals close to 30,000 waves or trapezoidal waves, but for convenience, we will approximate them as sine waves and state the following assuming that the phase difference is also 90°. Therefore, As1nθ, As1n(θ
+90°) = ACO8θ primary signal is considered to be output to the dividing circuit 12. 22, where θ is the phase corresponding to the displacement. Primary signal A sin θ input from the detector, ACOS
θ is input via buffer amplifiers 2OA and 20B, respectively, and from A sin θ, an inverting amplifier 22 outputs a primary signal A 5in (θ+180°) whose phase is shifted by 180
')=-ASinθ is generated. The resistance chain 16 is composed of a total of 8 resistors, and 1
The following signals are applied to nodes a, e, and i, respectively. The resistance values of resistors R1, R2, R3, and R4 are: ・The ratio is 1
:0.707:0.707:1, so that the phase of the secondary signals generated at other nodes b to h is 180'/8=22.5 from node a. °
It is set to shift gradually. The signals at each node at this time are shown in FIG. 2. When the primary signal changes as shown in the figure in accordance with the displacement of the object to be measured, the secondary signal changes with a phase shift accordingly. In this first embodiment, the phase difference of 1゛80° is divided into 8 equal parts, so as will be described later, 360° is divided into 16 equal parts, and 16 divisions are achieved. Note that if the detection signal is not a sine wave, this can be handled by adjusting the resistance value. - The nodes a to h of the resistance chain 16 are connected to eight analog switches 40A, 40C, . . . 400, which are provided correspondingly.
The node b-i is connected to one input of the second comparator 42A through eight correspondingly provided analog switches 40B, 40D, . . . , 40P. The other inputs of the comparators 42A and 42B are connected to the reference voltage Vr,
In this case, 0■ is applied. The analog switches 40A to 40P are 2 as shown in the figure.
A set of these is connected to the output of a reversible octal ring counter 50, which is a servo circuit. In this ring counter 50, when a counting pulse is input to the UP terminal or the DN terminal, the output "1" rotates the output terminal in the rightward or leftward direction. Therefore, only one of the analog switches 1ffi is selected and is in a conductive state, and the other non-selected analog switches are in a high input resistance state, that is, a state in which the connection is considered disconnected. When terminal 1 of 50 is "1", analog switches 40A and 40B are selected and are in the opposite state,
The signal at node a is input to the comparator 42A, and the signal at node S is input to the comparator 42B, and when both of these signals are greater than the zero level, both comparison signals J1 and J2 become "
1". Output 1 and output 8 of the octal ring counter 50 are also input to the direction inversion circuit 44. This is because, as will be described later, when switching from output 1 to output 8 or vice versa, comparison signals J1 and J2 of comparators 42A and 42B are inverted, so even if J1 and J2 are inverted, This is to generate the inversion signal K so that the forward/backward determination is not reversed. The direction reversal circuit 44 is connected to the octal ring counter 50.
a pulse expander 44A to which the output 1 of the octal ring counter 50 is input; a pulse expander 44B to which the output 8 of the octal ring counter 50 is input; an AND gate 44C which outputs the AND of the pulse expanders 44A and 44B; The AND gate 44C
The T flip-flop 44D generates an inverted signal K whose level is inverted every time the output of the octal ring counter 50 changes from 1 to 8 or vice versa based on the output of the octal ring counter 50. Therefore, the direction inversion circuit 44 outputs an inversion signal K for identifying when the output of the octal ring counter 50 is switched from 1 to 8 or vice versa. The direction discrimination circuit 46 includes the comparators 42A, 4
an AND gate 46A that outputs the logical product of the comparison signals J1 and J2 inputted from 2B and the inverted signal inputted from the direction inversion circuit 44; An AND gate 46B that outputs a logical product, and an OR gate 46C that outputs the logical sum of the AND gates 46A and 46B as an addition signal L1.
An exclusive OR gate 46D outputs the exclusive OR of the comparison signals L1 and J2, and the AND of the negation of the output of the exclusive OR gate 46D and the negation of the output of the OR gate 46C is output as a subtraction signal L2. and an AND gate 46E. Therefore, in this direction discrimination circuit 46, an addition signal L1 and a subtraction signal L2 are created from the comparison signals J1, J2 and the inverted signal K. The truth table of this direction discrimination circuit 46 is shown in Table 1 below. Table 1 On the other hand, from the oscillator 32, for example, 7 in 500 or 4
A tarok pulse CP of Mm is supplied. Therefore,
When the clock pulse CP is input when the addition signal L1 is "1", the UP counting pulse is output, and at the same time, the octal ring counter 50 is input to the DN f14, so the output terminal rotates to the left. Conversely, when the subtraction signal L2 is "1", a DOWN counting pulse is output, and the output terminal of the ring counter 50 rotates to the right. The UP counting pulse and the DOWN counting pulse constitute a counting signal. Therefore, when a certain set of analog switches is selected and the values of comparison signals J1 and J2 are different, in a stable state y, both addition signal Ll and subtraction signal L2 become "0", and meaningless counting pulses are output. Never. The operation of the first embodiment will be described below with reference to FIGS. 2 and 3. FIG. 3 shows a time chart of the signals at each part of the dividing circuit 12 when the primary signal at node a changes from a to roi to c to 2 to ho in FIG. First, in state A, terminal 3 of ring counter 50 is “1”.
”, and the inverted signal is also “1”. At this time, the node C is connected to the comparator 42A, and the node d is connected to the comparator 42B, and from FIG. 2, the comparison signals J1 and J2 are "0" and "1", respectively, so the addition signal L1 is Since the subtraction signal L2 and the subtraction signal L2 both become zero, no count signal is output. After this, on the way from i to mouth, both comparison signals J1 and J2 become "1", and only the addition signal L1 becomes "1", so
At the input of the clock pulse CP, an UP counting pulse, which is a counting signal, is output, and is fed back to the DN terminal of the octal ring counter 50, which is a servo circuit, and outputs "1".
rotates to terminal 2. Therefore, resistance series 5! Nodes b and C of i16 are connected to comparators 42A and 42B, respectively, and comparison signals J1 and J2 are "0" and "1", respectively.
Therefore, a counting pulse is not output, but an UP counting pulse is output when moving to the mouth. Next, when changing from B → A → C, the comparison signal J1,
Since J2 both become "0" periodically, the subtraction signal L2 becomes "1", a DOW N counting pulse is output as a counting signal, and the output "1" of the ring counter 50 is output from terminal 2→
Rotates 3→... Next, when the output of the ring counter 50 moves from terminal 8 to terminal 1 before and after position 2, the direction reversal circuit 44 is activated, and the inversion signal K becomes "0" at one point in FIG. Become. In the middle of position 2-H, comparison signals J1 and J2 are both "1".
” However, since the inverted signal K is “0”, the subtraction signal L2 becomes “1” from the truth table, and a DOWN count pulse is output. At this time, due to the action of the direction reversing circuit 44,
Even if the output of the ring counter 50 moves from terminal 8 to terminal 1,
It can be seen that the counting direction is maintained correctly. In this way, a pulse divided into 8 is obtained at 180°, so 16 divisions are achieved at 360°. Next, consider a case where the phase of the primary signal instantaneously changes by about 90 degrees. In this case, a counting pulse is output every time a clock pulse CP is input, and the output of the ring counter 50 is rotated until the outputs of the comparators 42A and 42B are inverted, and it is understood that the counting can be followed. Next, as a second embodiment of the present invention, FIG. 4 shows an example of a dividing circuit that outputs a count signal obtained by dividing the pitch of the detection signal (primary signal) into eight. In this second embodiment, a buffer amplifier 2 that inverts the output of the buffer amplifier 2OA similar to the first embodiment is used.
In addition to 2A, a buffer amplifier 22B that inverts the output of the buffer amplifier 20B is added, and A si
nθ, A CO3θ, -A Sinθ, -A CO3θ
48 signals are applied to the resistance chain 16, and further,
As1nθ is applied to two nodes, a 3-bit reversible binary counter 62 and a decoder 64 are used as the servo circuit, and the output of the decoder 64 is applied via OR gates 65A to 65H. each analog switch 40A so as to select two analog switches at the same time.
This embodiment differs from the first embodiment in that it is connected to 40H and that the number of analog switches is halved. Note that in the case of 8 divisions, it is sufficient to divide 90° into 2, so the resistance values of the resistance chain 16 are all set to the same value R. Furthermore, the direction reversal circuit of the first embodiment is also omitted. This directly divides the phase of the primary signal from 0° to 360° into 8, so the signal at each node of the resistance chain 16 is 04.45 @,
...Since the change is 360°=04, the decoder 64
This is because the phase does not change even when the output is switched from terminal 8 to terminal 1, and there is no need to send a phase inversion signal to direction discrimination circuit 66. In the direction discrimination circuit 66, the comparison signals J1 and J2 are logically summed, and the "1" signal is added to the addition signal L according to "0".
1 or by setting the subtraction signal L2 to "1",
An UP counting pulse or a DOWN counting pulse, which is a counting signal, is obtained by inputting the clock pulse CP. This counting pulse is fed back to a 3-bit reversible binary counter 62, which is part of the servo circuit. Also in this second embodiment, as in the first embodiment, the outputs of the comparison signals J1 and J2 are rQJ rl, or rl, rQ
When the combination is J, a stable state is reached in which no counting pulse is output. In this second embodiment, there is no need to generate a phase inversion signal and a direction inversion circuit can be omitted, so the configuration is simple. In each of the above embodiments, the primary signals are two-phase signals with a phase difference of 90 degrees, but the number of primary signals and the phase difference are not limited to this, and may be two or more phases. . Further, although the number of divisions was 16 in the first embodiment and 8 in the second embodiment, the number of divisions is not limited to these, and may be any number of divisions greater than or equal to 2. Furthermore, in all of the above implementations, the primary signal was a sine wave, but the shape of the primary signal is not limited to this; for example, it may be a triangular wave, a trapezoidal wave, etc. , When the shapes are different in this way, it can be easily handled by adjusting the resistance value of the resistance series πi by iA.

【Effect of the invention】

As explained above, according to the present invention, each node of the resistance chain is inputted to two comparators via an analog switch, so the number of comparators can be made smaller than the number of nodes of the resistance chain. It is particularly suitable for IC implementation. Further, since the counting signal is fed back by the servo circuit to select the analog switch, even if the primary signal changes instantaneously, it can be followed, and the response speed can be improved. Furthermore, when the phase of the primary signal does not change, there are excellent effects such as no meaningless count signal being output.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram showing the configuration of a first embodiment of a dividing circuit of a measuring device according to the present invention, and FIG. 2 is a circuit diagram showing the configuration of a resistor 3! in the first embodiment. ! FIG. 3 is a diagram showing examples of signal waveforms at each node of the chain; FIG. 3 is a diagram showing examples of signal waveforms at each part in the first embodiment; FIG. 4 is a diagram showing the configuration of the second embodiment of the invention. 5 is a block diagram showing an example of the overall configuration of a measuring device to which the present invention is applied; FIG. 6 is a circuit diagram showing the principle of a dividing circuit using a resistance chain; FIG. 1 is a circuit diagram showing an example of a conventional resistance dividing port. DESCRIPTION OF SYMBOLS 10... Detector, 12... Dividing circuit, 14... Counter, 16... Resistance chain, a-i... Node, 32... Oscillator, CP... Clock pulse, 40A~ 40P...Analog switch, 42A, 42
B... Comparator, Jl, J2... Comparison signal, 50... Octal ring counter, Ll... Addition signal, L2... Subtraction signal, 62... Binary counter, 64... decoder.

Claims (3)

[Claims] (1) Apply multi-phase primary signals with different phases to different nodes of a resistance chain to generate phase-shifted secondary signals at other nodes, and connect these nodes of the resistance chain with corresponding comparators. Each node of the resistance chain is connected in a dividing circuit of a measuring device that outputs a counting signal with a finer pitch than the primary signal by comparing the primary or secondary signal with a reference level. , connected to at least one of the two comparators via an analog switch to obtain a counting signal synchronized with the clock pulse when the outputs of the two comparators are simultaneously at a high level or a low level; A dividing circuit for a measuring device, comprising a servo circuit that feeds back the counting signal and sequentially selects two analog switches each connecting adjacent nodes to different comparators from among the analog switches. (2) A dividing circuit for a measuring device according to claim 1, wherein each node of the resistance chain is connected to two comparators via an analog switch. (3) A dividing circuit for a measuring device according to claim 1, wherein each node of the resistance chain is alternately connected to a different comparator via an analog switch.