CN117394825A - Capturing circuit and micro-processing chip - Google Patents

Abstract

The application provides a capture circuit and a micro-processing chip, wherein the capture circuit comprises 1 oscillator delay line and 3 capture delay lines, clock signals are provided for the 3 capture delay lines through the oscillator delay lines, and the positions of edges of signals to be detected are determined jointly by the 3 capture delay lines. The capture circuit provided by the embodiment of the application has at least the following advantages: 1) The clock signal is provided through the oscillator delay line, a phase-locked loop circuit is not required to be additionally arranged, and the system clock is not relied on; 2) Since the positions where the edges of the signal to be detected occur are determined together by 3 capture delay lines, the length of each capture delay line may be less than one clock cycle; 3) The phase difference between clock signals corresponding to different capture delay lines is set through the number ratio of the capture delay elements in the different capture delay lines, so that the design of the clock signals and the capture delay elements is more flexible.

Description

Capturing circuit and micro-processing chip

Technical Field

The present application relates to the field of electronic technology, and in particular, to a capture circuit and a microprocessor chip.

Background

In a large number of industrial and consumer equipment and instruments, signals such as voltage, current, capacitance, speed, distance and the like are commonly required to be measured, and the measurement accuracy directly influences the accuracy of the equipment and instruments. The high-precision digital pulse signal width measurement is widely applied to pulse sequence period/duty ratio measurement, instantaneous speed measurement, voltage measurement crossing isolation boundaries, distance/sonar measurement and scanning, capacitive touch sensing and other applications in precision instruments, sonar, robot servo, switching power supplies, power devices, touch screens and other devices.

In a digital signal processing device, signals such as voltage, capacitance, speed, distance and the like are converted and quantized into digital pulse signals (pulse signals for short) through analog-digital conversion, and then the pulse signals are measured. Specifically, the pulse signal width measurement is to use a sampling clock (frequency is f) and represent the width of a pulse signal as a real number including an integer part and a fractional part with the clock period of the sampling clock as a reference unit. The decimal part is generated by the fact that the edges of the pulse signals are not aligned with the edges of the sampling clock, and is derived from the head part and the tail part of the pulse signals. The relationship between the width lambda of the pulse signal and f, mu, alpha and beta is as follows: λ= (μ+1- α - β) ×1/f. Wherein μ is an integer fraction and 1- α - β is a fractional fraction.

The measurement precision of the traditional digital signal measurement circuit is 1/f of the clock period of 1 sampling clock, only the integral part mu of the width lambda of the pulse signal can be measured, and the decimal part 1-alpha-beta of the width of the pulse signal can not be measured. If the measurement accuracy is to be improved, only the clock frequency of the sampling clock can be improved, so that the power consumption and the complexity of the hardware circuit are greatly increased.

It should be noted that the information disclosed in the background section of the present application is only intended to enhance understanding of the general background of the present application and should not be taken as an acknowledgement or any form of suggestion that this information forms the prior art that is already known to a person skilled in the art.

Disclosure of Invention

The utility model provides a capture circuit and micro-processing chip to in order to solve in the prior art if want to improve measurement accuracy, can only improve the clock frequency of sampling clock, thereby greatly increased the problem of hardware circuit's consumption and complexity.

In a first aspect, embodiments of the present application provide a capture circuit, including:

the oscillator delay line comprises N time sequence delay elements and logic gates, wherein the N time sequence delay elements and the logic gates are sequentially coupled into a ring shape to generate an initial clock signal, and N is more than or equal to 2;

a first capture delay line comprising a plurality of a capture delay elements coupled in sequence to pass a first clock signal along a first signal path in a first direction and to pass a signal to be detected along a second signal path in a second direction opposite the first direction;

a second capture delay line comprising B capture delay elements coupled in sequence to pass a second clock signal along a third signal path in the first direction and to pass a signal to be detected along a fourth signal path in the second direction;

A third capture delay line comprising C capture delay elements coupled in sequence to pass a third clock signal along a fifth signal path in the first direction and to pass a signal to be detected along a sixth signal path in the second direction;

each capture delay element forms a trigger and provides a bit output, the output is determined by a clock signal and/or a signal to be detected, the first clock signal, the second clock signal and the third clock signal are clock signals generated according to the initial clock signal, a first phase difference exists between the first clock signal and the second clock signal, a second phase difference exists between the second clock signal and the third clock signal, the first phase difference is determined by the sum of the number of capture delay elements of the capture delay line and the number of capture delay elements of the first capture delay line, and the second phase difference is determined by the sum of the number of capture delay elements of the capture delay line and the number of capture delay elements of the second capture delay line.

The design of 3 capture delay lines is particularly suitable for situations where the number of capture delay elements 100 must be halved and the number of capture delay elements 100 (e.g., 15, 18, etc.) cannot be halved, and the design of 3 capture delay lines in this application may provide a good solution for this application scenario.

In some possible implementations, the method further includes: the first clock signal and the initial clock signal have no phase difference,

a first phase shifter for shifting the phase of the first clock signal (or the initial clock signal) and outputting a second clock signal;

the second phase shifter is used for shifting the phase of the second clock signal and outputting a third clock signal; alternatively, the first clock signal (or the initial clock signal) is phase-shifted, and a third clock signal is output.

In some possible implementations, a first phase difference exists between a first clock signal and the second clock signal, a second phase difference exists between the second clock signal and the third clock signal, n=a+b+c, the first phase difference is a/n×360°, and the second phase difference is B/n×360 °.

In some possible implementations, a=b=c, and the first phase difference and the second phase difference are each 120 °.

In some possible implementations, a+.b+.c.

In some possible implementations, a+.b=c, a+.b+.c, or a+.c+.b.

In some possible implementations, the first clock signal and the initial clock signal have a phase difference α, and the first phase shifter is configured to phase shift a/(a+b+c) 360 ° + α of the initial clock signal, and output a second clock signal;

The second phase shifter is used for shifting the phase of the second clock signal by B/(A+B+C) 360 degrees and outputting a third clock signal; or, shifting the phase of the first clock signal by a/(a+b+c) 360 ° +b/(a+b+c) 360 °, and outputting a third clock signal; or, shifting the initial clock signal by a/(a+b+c) 360 ° +b/(a+b+c) 360 ° +α, and outputting a third clock signal.

The phase shifting phase of the phase shifter can be adaptively designed according to the number of different capture delay units in the three capture delay lines, so that the design flexibility is improved.

In some possible implementations, the first clock signal, the second clock signal, and the third clock signal are delayed by a specified length relative to the initial clock signal.

In some possible implementations, the capture delay element includes:

a first nand gate including a first input terminal, a second input terminal, and an output terminal, the first input terminal of the first nand gate being configured to receive a clock signal transferred in the first direction;

the second NAND gate comprises a first input end, a second input end and an output end, wherein the first input end of the second NAND gate is electrically connected with the output end of the first NAND gate, the second input end of the second NAND gate is provided with 1, and the output end of the second NAND gate is used for outputting a clock signal in the first direction;

The first input end of the third NAND gate is used for receiving a signal to be detected transmitted in the second direction;

the first input end of the fourth NAND gate is provided with 1, the second input end of the fourth NAND gate is electrically connected with the output end of the third NAND gate, and the output end of the fourth NAND gate is used for outputting a signal to be detected in the second direction;

the second input end of the first NAND gate is electrically connected with the second input end of the fourth NAND gate, and the first input end of the second NAND gate is electrically connected with the second input end of the third NAND gate.

In some possible implementations, the timing delay element includes:

the fifth NAND gate comprises a first input end, a second input end and an output end, wherein the first input end of the fifth NAND gate is used for being connected with the output end of the last time sequence delay element, and the second input end of the fifth NAND gate is provided with 1;

the sixth NAND gate comprises a first input end, a second input end and an output end, wherein the first input end of the sixth NAND gate is provided with 1, the second input end of the sixth NAND gate is electrically connected with the output end of the fifth NAND gate, and the output end of the sixth NAND gate is used for being connected with the input end of the next time sequence delay element.

In some possible implementations, the method further includes:

and the multiplexer is coupled to the signal input ends of the first capture delay line, the second capture delay line and the third capture delay line and is used for providing the signal to be detected, or the inverted signal of the signal to be detected or the signal after the phase shift treatment of the signal to be detected to the first capture delay line, the second capture delay line and the third capture delay line.

In a second aspect, embodiments of the present application provide a micro-processing chip, including the capture circuit of any one of the first aspects.

The capture circuit provided by the embodiment of the application has at least the following advantages:

1) The clock signal is provided through the oscillator delay line, a phase-locked loop circuit is not required to be additionally arranged, and the system clock is not relied on;

2) Since the positions where the edges of the signal to be detected occur are determined together by 3 capture delay lines, the length of each capture delay line may be less than one clock cycle;

3) The phase difference between clock signals corresponding to different capture delay lines is set through the number ratio of the capture delay elements in the different capture delay lines, so that the design of the clock signals and the capture delay elements is more flexible.

Drawings

In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings that are needed in the embodiments will be briefly described below, it being obvious that the drawings in the following description are only some embodiments of the present application, and that other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.

Fig. 1 is a schematic structural diagram of a capturing delay element according to an embodiment of the present application;

FIG. 2 is a schematic diagram of a capturing delay line according to an embodiment of the present application;

fig. 3 is a schematic structural diagram of a timing delay element according to an embodiment of the present application;

fig. 4 is a schematic structural diagram of an oscillator delay line according to an embodiment of the present disclosure;

fig. 5 is a schematic structural diagram of a capturing circuit according to an embodiment of the present application;

FIG. 6 is a timing diagram of a clock signal according to an embodiment of the present disclosure;

FIG. 7 is a schematic diagram of another capturing circuit according to an embodiment of the present disclosure;

FIG. 8 is a signal timing diagram of edge detection using the capture circuit of FIG. 7;

FIG. 9 is a schematic diagram of another capturing circuit according to an embodiment of the present disclosure;

FIG. 10 is a schematic diagram of another capturing circuit according to an embodiment of the present disclosure;

fig. 11 is a schematic structural diagram of a micro-processing chip according to an embodiment of the present application.

Detailed Description

For a better understanding of the technical solutions of the present application, embodiments of the present application are described in detail below with reference to the accompanying drawings.

It should be understood that the described embodiments are merely some, but not all, of the embodiments of the present application. All other embodiments, based on the embodiments herein, which would be apparent to one of ordinary skill in the art without making any inventive effort, are intended to be within the scope of the present application.

The terminology used in the embodiments of the application is for the purpose of describing particular embodiments only and is not intended to be limiting of the application. As used in this application and the appended claims, the singular forms "a," "an," and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise.

It should be understood that the term "and/or" as used herein is merely one way of describing an association of associated objects, meaning that there may be three relationships, e.g., a and/or b, which may represent: the first and second cases exist separately, and the first and second cases exist separately. In addition, the character "/" herein generally indicates that the front and rear associated objects are an "or" relationship.

Referring to fig. 1, a schematic structural diagram of a capturing delay element according to an embodiment of the present application is provided. As shown in fig. 1, the capture delay element 100 includes a first nand gate 110, a second nand gate 120, a third nand gate 130, and a fourth nand gate 140. Wherein the first input 111 of the first nand gate 110 is configured to receive a first signal, such as a clock signal, transmitted in a first direction (right to left); the first input end 121 of the second nand gate 120 is electrically connected to the output end 113 of the first nand gate 110, the second input end 122 of the second nand gate 120 is set to 1, and the output end 123 of the second nand gate 120 is used for outputting a first signal in a first direction; the first input 131 of the third nand gate 130 is configured to receive a second signal, such as a signal to be detected, transmitted in a second direction (from left to right); the first input terminal 141 of the fourth nand gate 140 is set to 1, the second input terminal 142 of the fourth nand gate 140 is electrically connected to the output terminal 133 of the third nand gate 130, and the output terminal 143 of the fourth nand gate 140 is configured to output the second signal in the second direction; the second input 112 of the first nand gate 110 is electrically connected to the second input 142 of the fourth nand gate 140, and the first input 121 of the second nand gate 120 is electrically connected to the second input 132 of the third nand gate 130. In addition, the output 143 of the fourth NAND gate 140 provides one output bit. That is, the capture delay element 100 may receive two signals input in opposite directions and provide a one-bit output.

It should be noted that the capture delay element 100 is described in fig. 1 by taking a nand gate as an example. However, it should be understood by those skilled in the art that other logic circuits may be used to implement the relevant functions of the capture delay element 100 instead of nand gates, and all of them are within the scope of this application.

Referring to fig. 2, a schematic diagram of a capturing delay line according to an embodiment of the present application is provided. As shown in fig. 2, the acquisition delay line 200 includes M acquisition delay elements 100, which M acquisition delay elements 100 are coupled together in sequence to form the acquisition delay line 200. A first signal (e.g., clock signal synclk, which may also be referred to as "SYNCIN" in other parts of the document) is received on the lower signal path of the acquisition delay line 200 and passes right to left through the lower signal path of the acquisition delay line 200. A second signal (e.g., ECAPxIN x, the signal to be detected, which may also be referred to herein as "ASYNCIN") is received on the upper signal path of the acquisition delay line 200 and passes from left to right through the upper signal path of the acquisition delay line 200.

Specifically, a high ("1") input corresponding to the rising edge of the clock signal SYSCLK captures the delay element 100- (M-1), causing the first NAND gate 110- (M-1) of the delay element 100- (M-1) to produce a low ("0") output; the low ("0") input of the first NAND gate 110- (M-1) to the second NAND gate 120- (M-1) results in the second NAND gate 120- (M-1) producing a high ("1") output such that the rising edge passes right to left as shown by the lower arrow in FIG. 2. Meanwhile, the low ("0") input of the first NAND gate 110- (M-1) to the third NAND gate 120- (M-1) results in a high ("1") output of the third NAND gate 120- (M-1) without any other inputs; the high ("1") input of the third NAND gate 120- (M-1) to the fourth NAND gate 140- (M-1) results in a low ("0") output of the fourth NAND gate 140- (M-1), i.e., the output bit HR (M-1) of the capture delay element 100- (M-1) is set to 0. As the rising edge passes from right to left, the output bits of the corresponding capture delay elements are sequentially set to 0, i.e., the output is determined by the clock signal.

Similarly, a high ("1") input to the capture delay element 100-0 corresponding to the rising edge of the signal to be detected ECAPxIN [ x ], causes the third nand gate 130-0 of the capture delay element 100-0 to generate a low ("0") output; the low ("0") input of the third NAND gate 130-0 to the fourth NAND gate 140-0 results in a high ("1") output of the fourth NAND gate 140-0 such that the rising edge passes from left to right, as shown by the upper arrow in FIG. 2. Meanwhile, the output bit HR (0) of the capture delay element 100-0 is set to 1 without any other input. As the rising edge passes from left to right, the output bits of the corresponding capture delay elements are sequentially set to 1, i.e., the output is determined by the signal to be detected.

It will be appreciated that the clock signal SYSCLK and the signal to be detected ECAPxIN [ x ] will eventually meet, after the clock signal SYSCLK and the signal to be detected ECAPxIN [ x ] meet, the state of the output bit of the capture delay element 100 will not change, and the clock signal SYSCLK and the signal to be detected ECAPxIN [ x ] will not propagate any further. Thus, the state of the output bit of the capture delay element 100 depends on which of the clock signal SYSCLK and the signal ECAPxIN [ x ] to be detected has a rising edge that reaches the capture delay element 100 first. Specifically, if the rising edge of the clock signal SYSCLK reaches the capture delay element 100 first, the state of the output bit of the capture delay element 100 is low ("0"); if the rising edge of the signal to be detected ECAPxIN [ x ] reaches the capture delay element 100 first, the state of the output bit of the capture delay element 100 is high ("1"). Thus, movement of the two signals will result in a series of "1" s starting from capture delay element 100-0 and a series of "0" s starting from capture delay element 100- (M-1). I.e. the output is determined by the clock signal and the signal to be detected.

Since the clock signal SYSCLK always propagates through half of the capture delay line 200, the state of the output bit of the right half of the capture delay line 200 is always 0. For example, if the rising edges of the clock signal SYSCLK and the signal ECAPxIN [ x ] to be detected occur simultaneously, the capture delay line 200 is frozen in the middle, i.e., the states of the output bits of the left half of the capture delay line 200 are all 1; the states of the output bits of the right half are all 0. If the rising edge of the signal to be detected ECAPxIN [ x ] is later than the rising edge of the clock signal SYSCLK, the state of the output bit of the left half of the capture delay line 200 is partially 1 and partially 0; the states of the output bits of the right half are all 0. The number of "1's" in the output bits of the left half of the capture delay line 200 will depend on the time difference between the clock signal SYSCLK and the signal ECAPxIN [ x ] to be detected. Therefore, by decoding the number of 1 s in HR [ M-1:0] of the capture delay line 200, the position of the signal to be detected ECAPxIN [ x ] relative to the clock signal SYSCLK can be determined, thereby realizing high resolution of pulse width measurement.

Referring to fig. 3, a schematic structural diagram of a timing delay element according to an embodiment of the present application is provided. As shown in fig. 3, the timing delay element 300 includes a fifth nand gate 310 and a sixth nand gate 320. The first input terminal 311 of the fifth nand gate 310 is connected to the output terminal of the last timing delay element, and the second input terminal 312 of the fifth nand gate 310 is set to 1; the first input terminal 3231 of the sixth nand gate 320 is set to 1, the second input terminal 322 of the sixth nand gate 320 is electrically connected to the output terminal 313 of the fifth nand gate 310, and the output terminal 323 of the sixth nand gate 320 is used for connecting to the input terminal of the next timing delay element.

It should be noted that the timing delay element 300 is illustrated in fig. 3 by taking a nand gate as an example. However, it should be understood by those skilled in the art that other logic circuits may be used to implement the relevant functions of the timing delay element 300 instead of nand gates, and all of them are within the scope of this application.

Referring to fig. 4, a schematic structural diagram of an oscillator delay line according to an embodiment of the present application is provided. As shown in FIG. 4, the oscillator delay line 400 includes N sequential delay elements 300, N.gtoreq.2. The N sequential delay elements 300 are sequentially coupled together to form an oscillator delay line 400. In addition, the oscillator delay line 400 further includes a seventh nand gate 401, a first input terminal of the seventh nand gate 401 is configured to receive the enable control signal hrclk_en, a second input terminal of the seventh nand gate 401 is electrically connected to an output terminal of the timing delay element 300- (N-1) (one timing delay element at the end), and an output terminal of the seventh nand gate 401 is electrically connected to a first input terminal of the timing delay element 300-0 (one timing delay element at the end) such that the N timing units and the seventh nand gate 401 form a loop.

When the enable control signal hrclk_en is high ("1"), the oscillator delay line 400 forms an oscillator, which may then generate a clock signal. To facilitate distinguishing from other clock signals later, the clock signal generated by the oscillator delay line 400 is referred to as the "initial clock signal HRCLK". Let the delay of the signal generated by the timing delay element 300 be δ, the relationship between the clock cycle THRCLK of the initial clock signal HRCLK output after the oscillator is stabilized, the delay δ of the timing delay element 300, and the number N of the timing delay elements 300 is: thrclk= 2*N ×δ, N is an even number.

It should be noted that, as a person skilled in the art may also use other logic gates instead of the seventh nand gate 401 to implement the relevant function according to actual needs. Alternatively, the seventh nand gate 401 is omitted in the oscillator delay line 400 so that the output terminal of the endmost one of the timing delay elements 300 is electrically connected to the input terminal of the frontmost one of the timing delay elements 300, forming a loop. However, in this case, if an oscillator is formed, the number N of the timing delay elements 300 in the oscillator delay line 400 should be an odd number.

With continued reference to FIG. 2, since the clock signal SYSCLK always propagates through half of the capture delay line 200, the length of the capture delay line 200 must span 2 clock cycles of the clock signal SYSCLK in order to accurately capture the position where the edge of the signal to be detected ECAPxIN [ x ] occurs. Meanwhile, the resolution of the pulse width measurement depends on the clock period TSYSCLK of the clock signal SYSCLK and the number M of capture delay elements 100, specifically: TSYSCLK divided by (M/2). It should be noted that, the length of the capturing delay line 200 refers to a time period required for a signal to pass from one end of the capturing delay line 200 to the other end.

From another perspective, a capture delay line 200 having a specified length can only support a particular clock frequency. If the system clock is relied upon, the length of the capture delay line 200 may not be flexibly adjustable. In addition, in some application scenarios, the system clock may run at a different frequency, resulting in that the system clock may not be available for the circuit. Greater flexibility can be achieved by providing the acquisition delay line with a dedicated clock that is independent of the system clock, but this results in increased circuit costs due to the need to add phase locked loop circuitry to the dedicated clock circuit.

In summary, the capture delay line 200 shown in fig. 2 has at least the following problems: 1) Since a capture delay line with a specified length can only support a specific clock frequency, if it depends on the system clock, the length of the capture delay line cannot be flexibly adjusted; 2) If a special clock independent of the system clock is provided for the acquisition delay line, a phase-locked loop circuit needs to be added, thus resulting in increased circuit cost; 3) The length of the capture delay line needs to be designed to be greater than two clock cycles to function properly.

In view of the above problems, an embodiment of the present application provides a capturing circuit, including 1 oscillator delay line and 3 capturing delay lines, where clock signals are provided to the 3 capturing delay lines by the oscillator delay line, and the positions where edges of a signal to be detected occur are determined by the 3 capturing delay lines together. The capture circuit provided by the embodiment of the application has at least the following advantages: 1) The clock signal is provided through the oscillator delay line, a phase-locked loop circuit is not required to be additionally arranged, and the system clock is not relied on; 2) Since the positions where the edges of the signal to be detected occur are determined together by 3 capture delay lines, the length of each capture delay line may be less than one clock cycle; 3) The phase difference between clock signals corresponding to different capture delay lines is set through the number ratio of the capture delay elements in the different capture delay lines, so that the design of the clock signals and the capture delay elements is more flexible. The detailed description is provided below in connection with specific implementations.

Referring to fig. 5, a schematic structural diagram of a capturing circuit according to an embodiment of the present application is provided. As shown in fig. 5, the capturing circuit includes one oscillator delay line 400 and 3 capturing delay lines 200 (a first capturing delay line 201, a second capturing delay line 202, and a third capturing delay line 203). Wherein the oscillator delay line 400 includes N sequential delay elements 300, N.gtoreq.2; the first capture delay line 201 includes a capture delay elements 100; the second capture delay line 202 includes B capture delay elements 100; the third capture delay line 203 includes C capture delay elements 100.

When the oscillator delay line 400 is operated, the oscillator delay line 400 may generate an initial clock signal HRCLK, and further, may generate a first clock signal HRCLK1, a second clock signal HRCLK2, and a third clock signal HRCLK3 according to the initial clock signal HRCLK, which are respectively provided to the 3 capture delay lines 200. That is, in the embodiment of the present application, the clock signal is provided through the oscillator delay line 400, and thus, no additional phase-locked loop circuit is required and is not dependent on the system clock.

Referring to fig. 6, a timing diagram of a clock signal according to an embodiment of the present application is provided. As shown in fig. 6, there is a first phase difference between the first clock signal HRCLK1 and the second clock signal HRCLK2, and a second phase difference between the second clock signal HRCLK2 and the third clock signal HRCLK 3. In the embodiment of the application, one clock period of the clock signal can be divided into 3 time intervals by the phase difference between different clock signals. In time interval a, the location where the edge of the signal ECAPxIN [ x ] to be detected occurs is provided by the first capture delay line 201. Specifically, the first capture delay line 201 passes the first clock signal HRCLK1 along a first signal path in a first direction (right to left) and passes the signal ECAPxIN [ x ] to be detected along a second signal path in a second direction (left to right) opposite to the first direction. In time interval B, the location where the edge of the signal ECAPxIN [ x ] to be detected occurs is provided by the second capture delay line 202. Specifically, the second capture delay line 202 passes the second clock signal HRCLK2 in the first direction along the third signal path and passes the signal ECAPxIN [ x ] to be detected in the second direction along the fourth signal path. In time interval C, the position where the edge of the signal ECAPxIN [ x ] to be detected occurs is provided by the third capture delay line 203. Specifically, the third capture delay line 203 passes the third clock signal HRCLK3 in the first direction along the fifth signal path and passes the signal to be detected ECAPxIN [ x ] in the second direction along the sixth signal path.

That is, each capture delay line 200 is only responsible for detecting a certain time interval in one clock cycle, and the positions where the edges of the signal ECAPxIN [ x ] to be detected occur are determined by the 3 capture delay lines 200 together. As described above, when signal edge detection is performed using one capture delay line 200 shown in fig. 2, in order to accurately capture the position where the edge of the signal ECAPxIN [ x ] to be detected occurs, the capture delay line 200 must span 2 clock cycles. In the embodiment of the present application, since the positions where the edges of the signal ECAPxIN [ x ] to be detected occur are determined together by the 3 capture delay lines 200, the length of each capture delay line 200 may be less than one clock period.

It is understood that the length of the capture delay line 200 may be characterized by the number of capture delay elements 100 in the capture delay line 200. Since the "number ratio of the capture delay elements 100 in the different capture delay lines 200" is associated with the "phase difference between the clock signals corresponding to the different capture delay lines 200", the phase difference between the clock signals corresponding to the different capture delay lines 200 can be "determined" by the "number ratio of the capture delay elements 100 in the different capture delay lines 200". Specifically, the phase difference between the first clock signal HRCLK1 and the second clock signal HRCLK2, i.e., the first phase difference is a/(a+b+c) 360 °; the phase difference between the second clock signal HRCLK2 and the third clock signal HRCLK3, i.e., the second phase difference, is B/(a+b+c) 360 °. Wherein A, B, C is the number of capture delay elements 100 in the first, second and third capture delay lines 201, 202 and 203, respectively. Illustratively, when a=b=c, the first phase difference and the second phase difference are both 120 °. When a=2b=c, the first phase difference is 90 °, and the second phase difference is 180 °.

In addition, the embodiment of the present application does not limit the number of the capturing delay elements 100 in the 3 capturing delay lines 200 and the ratio of the number of the capturing delay elements 100 in the different capturing delay lines 200. Illustratively, the number relationship of capture delay elements 100 in 3 capture delay lines 200 may be configured to: a=b= C, A +.b+. C, A +.b=c or a=b+.c, specific a=b=c=1 or a=1, b=2, c=3 or a+.2, b+.2, c+.2 or a=0, b+.1, c+.1, where only two capture delay lines are working, n=2, the phase difference of the phase shift is determined by B, C, such as phase difference B/(b+c) ×360.

In summary, in the embodiment of the present application, the number of the capturing delay elements 100 in the different capturing delay lines 200 may be flexibly configured, and the phase difference between the clock signals corresponding to the different capturing delay lines 200 may be set by the number ratio of the capturing delay elements 100 in the different capturing delay lines 200, so that the design of the clock signals and the capturing delay elements 100 is more flexible.

In addition, in some possible application scenarios, the number of capture delay elements 100 must be equal, i.e. the lengths of the different capture delay lines 200 must be equal. If there are only two capture delay lines 200 and the number of capture delay elements 100 (e.g., 15, 18, etc.) cannot be halved, then the design requirements cannot be met. However, the design of 3 capture delay lines 200 in the embodiments of the present application may provide a good solution for this application scenario.

With continued reference to fig. 5, in an embodiment of the present application, the acquisition circuit further includes a first phase shifter and a second phase shifter. After the oscillator delay line 400 generates the initial clock signal HRCLK, the first clock signal HRCLK1 may be determined according to the initial clock signal HRCLK. The first clock signal HRCLK1 may be the same signal as the initial clock signal HRCLK, or may be a signal delayed by a certain time (e.g., delayed by 1/6 clock cycle) from the initial clock signal HRCLK. The delay of the initial clock signal HRCLK may reserve time for the phase shifting operations of the subsequent first phase shifter and second phase shifter.

After obtaining the first clock signal HRCLK1, the first phase shifter may phase shift the first clock signal HRCLK1 to obtain the second clock signal HRCLK2; the second phase shifter may phase shift the second clock signal HRCLK2 to obtain a third clock signal HRCLK3. Of course, in some possible implementations, the second phase shifter may also directly phase shift the first clock signal HRCLK1 to obtain the third clock signal HRCLK3. For example, if the first phase difference and the second phase difference are both 120 °, the first clock signal HRCLK1 may be phase-shifted by 120 ° by the first phase shifter to obtain the second clock signal HRCLK2; the second clock signal HRCLK2 is phase-shifted by 120 ° by the second phase shifter to obtain a third clock signal HRCLK3. Or, shifting the first clock signal HRCLK1 by 120 ° by the first phase shifter to obtain the second clock signal HRCLK2; the first clock signal HRCLK1 is phase-shifted by 240 ° by the second phase shifter to obtain a third clock signal HRCLK3.

In some possible implementations, the first clock signal and the initial clock signal have a phase difference α (α may be a positive value or a negative value), and the first phase shifter is configured to phase shift a/(a+b+c) by 360 ° +α, and output the second clock signal; the second phase shifter is used for shifting the phase of the second clock signal by B/(A+B+C) 360 degrees and outputting a third clock signal; or, shifting the phase of the first clock signal by a/(a+b+c) 360 ° +b/(a+b+c) 360 °, and outputting a third clock signal; alternatively, the initial clock signal is phase shifted by a/(a+b+c) 360 ° +b/(a+b+c) 360 ° +α.

In some possible implementations, the first clock signal HRCLK1, the second clock signal HRCLK2, and the third clock signal HRCLK3 with a specified phase difference may also be obtained directly at different nodes of the oscillator delay line 400, which also falls within the scope of the generalization of the "clock signal generated from the initial clock signal HRCLK". It is understood that at this time, the first phase shifter and the second phase shifter in the acquisition circuit may be omitted.

With continued reference to fig. 5, in an embodiment of the present application, the acquisition circuit further includes a multiplexer 510. The first input 511 of the multiplexer 510 is for receiving the signal ECAPxIN [ x ] to be detected, and the second input 512 is for receiving an inverse signal of the signal ECAPxIN [ x ] to be detected. The output 514 of the multiplexer 510 is electrically connected to the first capture delay line 201, the second capture delay line 202 and the third capture delay line 203, respectively. The control terminal 514 of the multiplexer 510 receives the control signal CAPIN, and gates the connection between the first input terminal 511 and the output terminal 514 according to the control signal CAPIN to provide the first capture delay line 201, the second capture delay line 202 and the third capture delay line 203 with the signal ECAPxIN [ x ] to be detected; alternatively, the connection between the second input 512 and the output 514 is gated to provide the first capture delay line 201, the second capture delay line 202, and the third capture delay line 203 with an inverted signal of the signal ECAPxIN [ x ] to be detected.

In some possible implementations, the multiplexer 510 may further receive the phase-shifted signal ECAPxIN [ x ] of the signal ECAPxIN [ x ] to provide the phase-shifted signal ECAPxIN [ x ] of the signal ECAPxIN ] to the first capturing delay line 201, the second capturing delay line 202 and the third capturing delay line 203 through the selection of the control signal CAPIN, that is, the inverter design in the drawing may be changed to one or more phase shifters in conjunction with fig. 5, so that the phase-shifted signal ECAPxIN [ x ] of the signal ECAPxIN [ x ] is respectively input to the corresponding capturing delay line for subsequent data processing.

In order to facilitate understanding, the technical solutions provided in the embodiments of the present application are described in detail below in conjunction with specific implementations.

Referring to fig. 7, a schematic structural diagram of another capturing circuit according to an embodiment of the present application is provided. As shown in fig. 7, the capturing circuit includes 1 oscillator delay line 400 and 3 capturing delay lines 200 (a first capturing delay line 201, a second capturing delay line 202, and a third capturing delay line 203). The oscillator delay line 400 includes 6 timing delay elements 300, and each capturing delay line 200 includes 6 capturing delay elements 100.

When the enable control signal hrclk_en of the seventh nand gate 401 in the oscillator delay line 400 is low ("0"), the oscillator delay line 400 does not operate, and when the enable control signal hrclk_en of the oscillator delay line 400 is high ("1"), the oscillator delay line 400400 constitutes an oscillator, generates the initial clock signal HRCLK, and thus the first clock signal HRCLK1 can be determined according to the initial clock signal HRCLK. Since the number of the timing delay elements 300 in the 3 capturing delay lines 200 is equal, the first phase difference a/(a+b+c) ×360° =120°. That is, the first phase shifter may phase shift the first clock signal HRCLK1 by 120 ° to obtain the second clock signal HRCLK2. Similarly, the second phase difference B/(a+b+c) ×360° =120°, and the second phase shifter may shift the second clock signal HRCLK2 by 120 ° to obtain the third clock signal HRCLK3. Accordingly, each capture delay line 200 is responsible for 1/3 clock cycle detection. Specifically, the position where the edge of the signal to be detected ECAPxIN [ x ] occurs is determined by the first capturing delay line 201 in 0 to 1/3 period; determining, by the second capture delay line 202, where edges of the signal to be detected ECAPxIN [ x ] occur during 1/3-2/3 cycles; the position where the edge of the signal ECAPxIN [ x ] to be detected occurs is determined by the third capturing delay line 203 in 2/3 to 3/3 cycles.

Referring to fig. 8, a signal timing diagram for edge detection using the capture circuit shown in fig. 7 is shown. As shown in fig. 8, in the time interval a, the first clock signal HRCLK1 is high, and the rising edge of the first clock signal HRCLK1 propagates along the first signal path from right to left in the first capturing delay line 201. The rising edge of the signal to be detected ECAPxIN [ x ] goes high in time interval a and propagates along the second signal path from left to right in the first acquisition delay line 201. The output of the first capture delay line 201 is latched in HR1[5:0] and sent out after a short delay. In time interval B, the second clock signal HRCLK2 is high and the rising edge of the second clock signal HRCLK2 propagates along the third signal path right-to-left in the second capture delay line 202. During time interval B, the signal to be detected ECAPxIN [ x ] is high, which propagates along the fourth signal path from left to right in the second capture delay line 202. The output of the second capture delay line 202 is latched in HR2[5:0] and sent out after a short delay. In time interval C, the third clock signal HRCLK3 is high and the rising edge of the third clock signal HRCLK3 propagates through the fifth signal path right-to-left in the third capture delay line 203. In time interval C, the signal to be detected ECAPxIN [ x ] is high, which propagates from left to right along the sixth signal path in the third acquisition delay line 203. The output of the third capture delay line 203 is latched in HR3[5:0] and sent out after a short delay.

When the HR1[5:0], HR2[5:0] and HR3[5:0]3 values are all captured, the 3 values are connected to form HROUT [5:0], the number of 1 in HROUT [5:0] is counted to determine the HR value, the HR value can represent the position of the rising edge of the signal ECAPxIN [ x ] to be detected in one clock period, the decimal part of the pulse width can be determined, and high-precision measurement of the pulse width is realized.

As described above, since the clock signal always propagates through half of the capture delay line 200, the state of the output bits in the right half of the capture delay line 200 is always 0, and these values do not need to be captured and transmitted, therefore only half of the output bits in HROUT [5:0] need to be counted. Accordingly, when the total number of the capturing delay elements 100 in the 3 capturing delay lines 200 is M, the resolution of the capturing circuit is: the clock period THRCLK of the clock signal is divided by M/2.

Illustratively, in the capture circuit shown in fig. 7, 6 capture delay elements 100 are included in each capture delay line 200, and thus, 3 output bits are required in each capture delay line 200. The relationship between the detected signals ECAPxIN [ x ], HROUT [5:0], HR values and capture values is shown in Table one. Wherein the data in the signal to be detected ECAPxIN [ x ] represents the relative position of the edge (e.g., rising edge) of the signal to be detected ECAPxIN [ x ] and the clock signal. For example, when the edge of the signal to be detected ECAPxIN [ x ] is located at 1/9 of the clock signal, the capture value (1/9) +5 can be determined by counting the 1 duty cycle in HROUT [5:0] captured by the capture circuit to 111_111_110, and determining that the HR value is 1/9. Wherein the value "5" of the portion represents an integer portion of the pulse width in the signal to be detected ECAPxIN [ x ]. Similarly, when the edge of the signal ECAPxIN [ x ] to be detected is located at other positions of the clock signal, a corresponding capture value can be obtained through the capture circuit, so that high-precision measurement of pulse width is realized.

Table one:

ECAPxIN[x]	HROUT[5:0]	HR value	Capturing values
				0	111_111_111	0	0+5
1/9	111_111_110	1/9	(1/9)+5
				2/9	111_111_100	2/9	(2/9)+5
3/9	111_111_000	3/9	(3/9)+5
				4/9	111_110_000	4/9	(4/9)+5
5/9	111_100_000	5/9	(5/9)+5
				6/9	111_000_000	6/9	(6/9)+5
7/9	110_000_000	7/9	(7/9)+5
				8/9	100_000_000	8/9	(8/9)+5
9/9	000_000_000	9/9	(9/9)+5

Referring to fig. 9, a schematic diagram of another capturing circuit according to an embodiment of the present application is provided. As shown in fig. 9, the oscillator delay line 400 of the capture circuit includes 15 timing delay elements 300, and the first capture delay line 201 includes 5 capture delay elements 100; the second capture delay line 202 includes 5 capture delay elements 100 therein; the third capture delay line 203 includes 5 capture delay elements 100 therein. That is, the number N of timing delay elements 300 in the oscillator delay line 400=the number a of capture delay elements 100 in the first capture delay line 201+the number B of capture delay elements 100 in the second capture delay line 202+the number C of capture delay elements 100 in the third capture delay line 203.

In the present embodiment, each timing delay element 300 and each capture delay element 100 have similar delays. It will be appreciated that in this case, when n=a+b+c, the lengths of the 3 capturing delay lines 200 are matched to the clock period of the clock signal generated by the oscillator delay line 400, and each capturing delay line 200 is used to detect a signal of 1/3 clock period due to a=b=c.

For details of the embodiments of the present application, reference may be made to the descriptions of the foregoing embodiments, which are not repeated herein for brevity.

Referring to fig. 10, a schematic diagram of another capturing circuit according to an embodiment of the present application is provided. As shown in fig. 10, the embodiment of the present application differs from the embodiment shown in fig. 9 in that the second capture delay line 202 includes 4 capture delay elements 100. It will be appreciated that if the capture delay line 200 includes 5 capture delay elements 100, a 1/3 clock cycle signal can be detected, and when the number of capture delay elements 100 is one less (including 4 capture delay elements 100), a signal that loses (1/3 clock cycle) timing (1/5) is estimated to have some effect on the final capture result. However, if there are more capture delay elements 100 in one capture delay line 200, for example, 50 capture delay elements 100, when the number of capture delay elements 100 is one less (including 49 capture delay elements 100), the signal that would lose (1/3 clock period) timing (1/50) is estimated to have less impact on the final capture result, usually at acceptable signal loss. That is, even if the length of the acquisition delay line 200 does not match the preset clock period, normal signal detection can be performed as long as the gap is not too large.

Note that, in the embodiment of the present application, a=c+.b is taken as an example for explanation. The capture delay elements 100 in the 3 capture delay lines 200 may be configured in other quantitative relationships as desired by those skilled in the art. For example, a+.b=c, a=b+.c, or a+.b+.c, this is not a specific limitation of the embodiments of the present application.

For details of the embodiments of the present application, reference may be made to the descriptions of the foregoing embodiments, which are not repeated herein for brevity.

Corresponding to the above embodiment, the embodiment of the present application also provides a micro-processing chip.

Referring to fig. 11, a schematic structural diagram of a micro-processing chip according to an embodiment of the present application is provided. As shown in fig. 11, the micro-processing chip includes a capture circuit. For details of the capturing circuit, reference may be made to the description of the above embodiments, and for brevity of description, details are not repeated here.

In a specific implementation, the micro processing chip may be a micro central control chip, a system on chip, or the like, which can process digital signals and analog signals, or perform functions such as signal control, instruction processing, and operation, for example, by using a control module, a DSP, an MPU, a micro CPU, or the like.

For details of the embodiments of the present application, reference may be made to the descriptions of the foregoing embodiments, which are not repeated herein for brevity.

In the embodiments of the present application, "at least one" means one or more, and "a plurality" means two or more. "and/or", describes an association relation of association objects, and indicates that there may be three kinds of relations, for example, a and/or B, and may indicate that a alone exists, a and B together, and B alone exists. Wherein A, B may be singular or plural. The character "/" generally indicates that the context-dependent object is an "or" relationship. "at least one of the following" and the like means any combination of these items, including any combination of single or plural items. For example, at least one of a, b and c may represent: a, b, c, a-b, a-c, b-c, or a-b-c, wherein a, b, c may be single or plural.

Those of ordinary skill in the art will appreciate that the various elements and algorithm steps described in the embodiments disclosed herein can be implemented as a combination of electronic hardware, computer software, and electronic hardware. Whether such functionality is implemented as hardware or software depends upon the particular application and design constraints imposed on the solution. Skilled artisans may implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the present application.

It will be clear to those skilled in the art that, for convenience and brevity of description, specific working procedures of the above-described systems, apparatuses and units may refer to corresponding procedures in the foregoing method embodiments, and are not repeated herein.

In several embodiments provided herein, any of the functions, if implemented in the form of software functional units and sold or used as a stand-alone product, may be stored in a computer-readable storage medium. Based on such understanding, the technical solution of the present application may be embodied essentially or in a part contributing to the prior art or in a part of the technical solution, in the form of a software product stored in a storage medium, including several instructions for causing a computer device (which may be a personal computer, a server, or a network device, etc.) to perform all or part of the steps of the methods described in the embodiments of the present application. And the aforementioned storage medium includes: a U-disk, a removable hard disk, a read-only memory (ROM), a random access memory (random access memory, RAM), a magnetic disk, or an optical disk, or other various media capable of storing program codes.

The foregoing is merely specific embodiments of the present application, and any person skilled in the art may easily conceive of changes or substitutions within the technical scope of the present application, which should be covered by the protection scope of the present application. The protection scope of the present application shall be subject to the protection scope of the claims.

Claims (11)

1. A capture circuit, comprising:

the oscillator delay line comprises N time sequence delay elements and logic gates, wherein the N time sequence delay elements and the logic gates are sequentially coupled into a ring shape to generate an initial clock signal, and N is more than or equal to 2;

a first capture delay line comprising a plurality of a capture delay elements coupled in sequence to pass a first clock signal along a first signal path in a first direction and to pass a signal to be detected along a second signal path in a second direction opposite the first direction;

a second capture delay line comprising B capture delay elements coupled in sequence to pass a second clock signal along a third signal path in the first direction and to pass a signal to be detected along a fourth signal path in the second direction;

A third capture delay line comprising C capture delay elements coupled in sequence to pass a third clock signal along a fifth signal path in the first direction and to pass a signal to be detected along a sixth signal path in the second direction;

each capture delay element forms a trigger and provides a bit output, the output is determined by a clock signal and/or a signal to be detected, the first clock signal, the second clock signal and the third clock signal are clock signals generated according to the initial clock signal, a first phase difference exists between the first clock signal and the second clock signal, a second phase difference exists between the second clock signal and the third clock signal, the first phase difference is determined by the sum of the number of capture delay elements of the capture delay line and the number of capture delay elements of the first capture delay line, and the second phase difference is determined by the sum of the number of capture delay elements of the capture delay line and the number of capture delay elements of the second capture delay line.

2. The capture circuit of claim 1, further comprising:

the first phase shifter is used for shifting the phase of the first clock signal and outputting a second clock signal;

The second phase shifter is used for shifting the phase of the second clock signal and outputting a third clock signal; alternatively, the first clock signal is phase-shifted, and a third clock signal is output.

3. The capture circuit of claim 1, wherein the first clock signal and the initial clock signal have a phase difference α, and the first phase shifter is configured to phase shift the initial clock signal by a/(a+b+c) 360 ° + α, and output a second clock signal;

the second phase shifter is used for shifting the phase of the second clock signal by B/(A+B+C) 360 degrees and outputting a third clock signal; or, shifting the phase of the first clock signal by a/(a+b+c) 360 ° +b/(a+b+c) 360 °, and outputting a third clock signal; or, shifting the initial clock signal by a/(a+b+c) 360 ° +b/(a+b+c) 360 ° +α, and outputting a third clock signal.

4. The capture circuit of claim 1, wherein the first clock signal and the second clock signal have a first phase difference, the second clock signal and the third clock signal have a second phase difference, N = a + B + C, the first phase difference being a/N x 360 ° and the second phase difference being B/N x 360 °.

5. The acquisition circuit of claim 4 wherein a = B = C, the first phase difference and the second phase difference each being 120 °.

6. The capture circuit of claim 4, wherein a noteqb noteqc, or a noteqb = C, or a =b noteqc, or a =c noteqb.

7. The capture circuit of claim 1, wherein the first clock signal, the second clock signal, and the third clock signal are delayed relative to the initial clock signal by a specified length.

8. The capture circuit of claim 1, wherein the capture delay element comprises:

a first nand gate including a first input terminal, a second input terminal, and an output terminal, the first input terminal of the first nand gate being configured to receive a clock signal transferred in the first direction;

the second NAND gate comprises a first input end, a second input end and an output end, wherein the first input end of the second NAND gate is electrically connected with the output end of the first NAND gate, the second input end of the second NAND gate is provided with 1, and the output end of the second NAND gate is used for outputting a clock signal in the first direction;

the first input end of the third NAND gate is used for receiving a signal to be detected transmitted in the second direction;

The first input end of the fourth NAND gate is provided with 1, the second input end of the fourth NAND gate is electrically connected with the output end of the third NAND gate, and the output end of the fourth NAND gate is used for outputting a signal to be detected in the second direction;

the second input end of the first NAND gate is electrically connected with the second input end of the fourth NAND gate, and the first input end of the second NAND gate is electrically connected with the second input end of the third NAND gate.

9. The capture circuit of claim 1, wherein the timing delay element comprises:

the fifth NAND gate comprises a first input end, a second input end and an output end, wherein the first input end of the fifth NAND gate is used for being connected with the output end of the last time sequence delay element, and the second input end of the fifth NAND gate is provided with 1;

the sixth NAND gate comprises a first input end, a second input end and an output end, wherein the first input end of the sixth NAND gate is provided with 1, the second input end of the sixth NAND gate is electrically connected with the output end of the fifth NAND gate, and the output end of the sixth NAND gate is used for being connected with the input end of the next time sequence delay element.

10. The capture circuit of claim 1, further comprising:

and the multiplexer is coupled to the signal input ends of the first capture delay line, the second capture delay line and the third capture delay line and is used for providing the signal to be detected, or the inverted signal of the signal to be detected or the signal after the phase shift treatment of the signal to be detected to the first capture delay line, the second capture delay line and the third capture delay line.

11. A microprocessor chip comprising the capture circuit of any one of claims 1-10.