JPS63111035U - - Google Patents

Info

Publication number
JPS63111035U
JPS63111035U JP149987U JP149987U JPS63111035U JP S63111035 U JPS63111035 U JP S63111035U JP 149987 U JP149987 U JP 149987U JP 149987 U JP149987 U JP 149987U JP S63111035 U JPS63111035 U JP S63111035U
Authority
JP
Japan
Prior art keywords
external control
control signal
level
amplifier
attenuation
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP149987U
Other languages
Japanese (ja)
Other versions
JPH0528837Y2 (en
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP1987001499U priority Critical patent/JPH0528837Y2/ja
Publication of JPS63111035U publication Critical patent/JPS63111035U/ja
Application granted granted Critical
Publication of JPH0528837Y2 publication Critical patent/JPH0528837Y2/ja
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

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  • Noise Elimination (AREA)
  • Circuits Of Receivers In General (AREA)
  • Input Circuits Of Receivers And Coupling Of Receivers And Audio Equipment (AREA)

Description

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本考案の一実施例のブロツク図、第2
図は第1図におけるコンパレータ7の動作を説明
するための図、第3図は本考案の実施例の動作を
説明するためのS/N特性図、第4図は従来のA
GCループのブロツク図、第5図は第4図の動作
を説明するためのS/N特性図。 図中、2……AGC増幅器、3……プログラマ
ブル減衰器、4……レベル検出器、5……AGC
ループフイルタ、6……直流増幅器、7……コン
パレータ、8……レベル変換器、9……復調器。
Fig. 1 is a block diagram of an embodiment of the present invention;
The figure is a diagram for explaining the operation of the comparator 7 in Figure 1, Figure 3 is an S/N characteristic diagram for explaining the operation of the embodiment of the present invention, and Figure 4 is a diagram for explaining the operation of the comparator 7 in Figure 1.
5 is a block diagram of the GC loop, and FIG. 5 is an S/N characteristic diagram for explaining the operation of FIG. 4. In the figure, 2...AGC amplifier, 3...Programmable attenuator, 4...Level detector, 5...AGC
Loop filter, 6... DC amplifier, 7... Comparator, 8... Level converter, 9... Demodulator.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] 入力信号レベル変化を一定レベルに抑えるAG
C増幅器と、レベル検出器と、ループフイルタ及
び直流増幅器とを含むAGCループにおいて、利
得又は減衰量が外部制御信号によつて決定される
プログラマブル減衰器と、AGC電圧をあらかじ
め定められた基準電圧と比較する手段と、該比較
手段の出力信号を前記外部制御信号に変換するレ
ベル変換器とを付加したことを特徴とする自動S
/N改善回路。
AG that suppresses input signal level changes to a constant level
In an AGC loop including a C amplifier, a level detector, a loop filter, and a DC amplifier, a programmable attenuator whose gain or attenuation is determined by an external control signal, and a programmable attenuator whose gain or attenuation is determined by an external control signal; An automatic S characterized in that it further comprises a comparing means and a level converter for converting the output signal of the comparing means into the external control signal.
/N improvement circuit.
JP1987001499U 1987-01-10 1987-01-10 Expired - Lifetime JPH0528837Y2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1987001499U JPH0528837Y2 (en) 1987-01-10 1987-01-10

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1987001499U JPH0528837Y2 (en) 1987-01-10 1987-01-10

Publications (2)

Publication Number Publication Date
JPS63111035U true JPS63111035U (en) 1988-07-16
JPH0528837Y2 JPH0528837Y2 (en) 1993-07-23

Family

ID=30779462

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1987001499U Expired - Lifetime JPH0528837Y2 (en) 1987-01-10 1987-01-10

Country Status (1)

Country Link
JP (1) JPH0528837Y2 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO1998010514A1 (en) * 1996-09-05 1998-03-12 Mitsubishi Denki Kabushiki Kaisha Gain controlling method and receiver

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6091730A (en) * 1983-10-26 1985-05-23 Matsushita Electric Ind Co Ltd Radio receiver

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6091730A (en) * 1983-10-26 1985-05-23 Matsushita Electric Ind Co Ltd Radio receiver

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO1998010514A1 (en) * 1996-09-05 1998-03-12 Mitsubishi Denki Kabushiki Kaisha Gain controlling method and receiver

Also Published As

Publication number Publication date
JPH0528837Y2 (en) 1993-07-23

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