JPS60150814U - AGC circuit - Google Patents
AGC circuitInfo
- Publication number
- JPS60150814U JPS60150814U JP3816784U JP3816784U JPS60150814U JP S60150814 U JPS60150814 U JP S60150814U JP 3816784 U JP3816784 U JP 3816784U JP 3816784 U JP3816784 U JP 3816784U JP S60150814 U JPS60150814 U JP S60150814U
- Authority
- JP
- Japan
- Prior art keywords
- agc circuit
- amplifier
- controls
- detection signal
- variable attenuator
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Control Of Amplification And Gain Control (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Abstract] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
第１区は従来のＡＧＣ回路の要部ブロック図、第２図は
従来の入力信号とループゲインとの特性曲線図、第３図
は本考案と一実施例の要部ブロック図、第４図は本考案
の入力信号とループゲインとの特性曲線図、第５図は本
考案の他の実施例の要部回路図である。
１．３は増幅器、２は可変減衰器１４は検波器、５は直
流増幅器、６はループゲイン抑制回路、Ｒ１，Ｒ２は抵
抗、コはツェナーダイオード、ＤＩ、Ｄ２．Ｄ３はダイ
オードである。Section 1 is a block diagram of the main parts of a conventional AGC circuit, Fig. 2 is a characteristic curve diagram of the conventional input signal and loop gain, Fig. 3 is a block diagram of the main parts of the present invention and an embodiment, and Fig. 4 5 is a characteristic curve diagram of the input signal and loop gain of the present invention, and FIG. 5 is a main circuit diagram of another embodiment of the present invention. 1.3 is an amplifier, 2 is a variable attenuator 14 is a detector, 5 is a DC amplifier, 6 is a loop gain suppression circuit, R1, R2 are resistors, ko is a Zener diode, DI, D2. D3 is a diode.
Claims (1)
器の前段に設けた可変減衰器を制御し、前記増幅器の出
力レベルを一定化するＡＧＣ回路に於いて、前記可変減
衰器を制御する前記検出信号のレベルを抑制する為の抵
抗とダイオードとからなるループゲイン抑制回路を設け
たことを特徴とするＡＧＣ回路。In an AGC circuit that controls a variable attenuator provided before the amplifier using a detection signal that detects the output level of the amplifier to keep the output level of the amplifier constant, the detection signal that controls the variable attenuator is An AGC circuit characterized by providing a loop gain suppression circuit consisting of a resistor and a diode for suppressing the level.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3816784U JPS60150814U (en) | 1984-03-19 | 1984-03-19 | AGC circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3816784U JPS60150814U (en) | 1984-03-19 | 1984-03-19 | AGC circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS60150814U true JPS60150814U (en) | 1985-10-07 |
Family
ID=30544920
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP3816784U Pending JPS60150814U (en) | 1984-03-19 | 1984-03-19 | AGC circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS60150814U (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS63246015A (en) * | 1987-04-01 | 1988-10-13 | Oki Electric Ind Co Ltd | Preventing circuit for over input of automatic output control circuit |
-
1984
- 1984-03-19 JP JP3816784U patent/JPS60150814U/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS63246015A (en) * | 1987-04-01 | 1988-10-13 | Oki Electric Ind Co Ltd | Preventing circuit for over input of automatic output control circuit |
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