JPS63111028U - - Google Patents
Info
- Publication number
- JPS63111028U JPS63111028U JP79087U JP79087U JPS63111028U JP S63111028 U JPS63111028 U JP S63111028U JP 79087 U JP79087 U JP 79087U JP 79087 U JP79087 U JP 79087U JP S63111028 U JPS63111028 U JP S63111028U
- Authority
- JP
- Japan
- Prior art keywords
- flip
- flop
- msb
- output
- gate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000010586 diagram Methods 0.000 description 3
Landscapes
- Manipulation Of Pulses (AREA)
Description
第１図は本考案カウンタ回路の一例を示す構成
ブロツク図、第２図はバイナリーカウンタの内部
データの変化を示す図、第３図はカウンタの上限
リミツトの動作を示す波形図である。
ＣＵ……バイナリーカウンタ、ＦＦ１，ＦＦ２
，ＦＦ３……フリツプフロツプ、Ｇ１〜Ｇ７……
ゲート、ＩＶ１，ＩＶ２……インバータ。
FIG. 1 is a block diagram showing an example of the counter circuit of the present invention, FIG. 2 is a diagram showing changes in internal data of the binary counter, and FIG. 3 is a waveform diagram showing the operation of the upper limit of the counter. CU...Binary counter, FF1, FF2
, FF3... flip-flop, G1~G7...
Gate, IV1, IV2...Inverter.
Claims (1)
印加されるバイナリーカウンタＣＵと、このバイ
ナリーカウンタの計数値が上下限値を越えた時以
外のＭＳＢの変化による動作を禁止する信号を保
持する第１のフリツプフロツプＦＦ１と、回路が
上下限リミツトにかかつたことを記憶する第２の
フリツプフロツプＦＦ２と、前記バイナリーカウ
ンタのＭＳＢ出力を入力し当該ＭＳＢ出力が上限
か下限かを区別する第３のフリツプフロツプＦＦ
３と、前記第１、第２のフリツプフロツプからの
信号及びＭＳＢ出力を入力するゲートＧ２と、こ
のゲートの出力と前記第３のフリツプフロツプの
出力とを入力しその出力端が前記バイナリーカウ
ンタのアツプ／ダウン端子に接続されたゲートＧ
３，Ｇ４とを備えたカウンタ回路。 A binary counter CU to which a pulse signal to be counted is applied to the up/down terminal, and a first counter that holds a signal that prohibits operation due to a change in the MSB except when the count value of this binary counter exceeds the upper and lower limits. A flip-flop FF1, a second flip-flop FF2 that stores the fact that the circuit has reached the upper and lower limits, and a third flip-flop FF that receives the MSB output of the binary counter and determines whether the MSB output is the upper or lower limit.
3, a gate G2 to which the signals and MSB outputs from the first and second flip-flops are input; the output of this gate and the output of the third flip-flop are input; Gate G connected to down terminal
3, a counter circuit equipped with G4.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1987000790U JPH0731627Y2 (en) | 1987-01-07 | 1987-01-07 | Counter circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1987000790U JPH0731627Y2 (en) | 1987-01-07 | 1987-01-07 | Counter circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS63111028U true JPS63111028U (en) | 1988-07-16 |
| JPH0731627Y2 JPH0731627Y2 (en) | 1995-07-19 |
Family
ID=30778089
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1987000790U Expired - Lifetime JPH0731627Y2 (en) | 1987-01-07 | 1987-01-07 | Counter circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0731627Y2 (en) |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5568741A (en) * | 1978-11-20 | 1980-05-23 | Nec Corp | Counter circuit |
-
1987
- 1987-01-07 JP JP1987000790U patent/JPH0731627Y2/en not_active Expired - Lifetime
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5568741A (en) * | 1978-11-20 | 1980-05-23 | Nec Corp | Counter circuit |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0731627Y2 (en) | 1995-07-19 |
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