JPS63109613A - Bit number converting circuit - Google Patents

Abstract

PURPOSE:To realize both a level meter circuit and the number of bits conversion circuit by using shift information so as to apply level discrimination at the level meter circuit as to the digital data shifted already thereby minimizing the increase in the circuit scale. CONSTITUTION:Shift registers 12, 15 inputting an n-bit data 1 and outputting a high-order 1-bit data, a conversion pattern detection section 17 deciding the number of shifts of the n-bit data from the value of the high-order 1-bit data, a timing generating section 19 generating a shift clock to shift the n-bit data by the shift registers 12, 15 based on the shift information outputted from the detection section 17 and a dB conversion section 24 detecting the value of the n-bit data before shift based on the value, are provided. Thus, the shift register 15 and the timing generating circuit 17 are used in common, then the number of bits converting circuit and the level meter circuit 28 are realized simultaneously while the circuit scale increase is suppressed.

Description

[Detailed Description of the Invention] [Object of the Invention] (Industrial Field of Application) The present invention relates to a bit number conversion circuit that converts the number of bits of digital data, and particularly relates to a bit number conversion circuit that converts the number of bits of digital data. The present invention relates to a bit number conversion circuit which is characterized in that it is used in common with a meter circuit.

(Prior Art) A conventional level meter circuit is shown in FIG. This is used, for example, to digitally process an audio signal and display its level.

The number of bits of the digital data (1) to be processed now is 16.
Bit. This digital data (1) is input to the sheet register (2). The shift register (2) supplies the upper 11 bits to the dB converter (3). The dB converter (3) detects the level in 2 dB steps. That is, as shown in FIG. 4, a bit shift is performed so that the first value of the 4-bit data within the broken line frame becomes "1",
Then, the value of the 4-bit data is detected and judgment is made in 2 dB steps. The final level is determined based on the number of bit shifts and the result of the 2 dB determination.

The level determination result from the dB conversion section (3) is led to a meter processing section (4). Meter process section (4)
The next stage level meter (
5) Outputs a point-based AL signal for blinking the LED. Note that a clock is supplied to the dB conversion section (3) and the meter processing section (4) from the timing generation section (6), and both the rotation sections are driven.

The level meter (5) is, for example, a 21-segment IJ.
D, and displays the level of digital data (1) according to the instruction of the 5-bit control signal.

When recording data, the amount of recording can be increased by reducing the number of bits of the digital data (1). If we consider this in the case of audio signals, for example, long-term recording becomes possible.

FIG. 5 shows a conventional bit number conversion circuit. This is an example of converting 16-bit data into n-bit data according to the conversion rules shown in FIG. Digital data (1) is input to a shift register (7). Shift register (7
) was supplied to check the turn without converting the top 7 pits.
It is determined in which position "1" is set based on the value of the bit data, and the number of bit shifts of θ to 6 bits is determined.

The obtained shift information is guided to the timing generation section (9) and the conversion turn latch section (IQ).The timing generation section (9) generates a shift clock and conversion pattern of θ to 6-bit shift based on the shift information. Outputs the latch timing signal.

The digital data (1) is generated by the shift clock.
is shifted in the shift register (7).

The lower four pits of the shifted data are truncated, resulting in ν-bit data. However, if the value remains as it is, it cannot become the value of the minor bit data shown in FIG. Therefore, the conversion pattern latch section (II) generates a 4-pit conversion pattern according to the number of shifts as shown in FIG. Shift register (7)
The 12-bit data I outputted by is converted according to the rules shown in FIG.

(Problems to be Solved by the Invention) The above-mentioned bit number conversion circuit is required in order to equip a device equipped with the above-mentioned level meter circuit, such as a digital chill recording and reproducing device, with a long-time recording mode. However, if it is necessary to avoid an increase in the number of parts, an increase in chip area when integrated into an IC, etc., it may not be possible to separately provide the above-mentioned bit number conversion circuit.

The present invention has been made in view of such problems, and an object of the present invention is to realize both a level meter circuit and a bit number conversion circuit while minimizing the increase in circuit scale.

[Structure of the invention]

(Means for solving the problem) The bit number conversion circuit receives the upper 7 bits of 16-bit digital data and determines the shift number of θ to 6 bits based on this. This is equivalent to dividing the data into levels in 5 dB steps. The present invention focuses on this point, and uses the above shift information to perform level determination (dB conversion) on the a-#+ shifted digital data in a level meter circuit. As a result, the dB converter in the level meter circuit can always determine the level by looking at four specific pits in the shift data.

(Function) According to the present invention, since the shift register and timing generation circuit are shared, it is possible to simultaneously realize a bit number conversion circuit and a level meter circuit while suppressing an increase in circuit scale as much as possible. In addition, the level judgment in the dB conversion section of the level meter circuit can be made by simply looking at four specific pits in the data, which shortens the judgment time compared to the conventional method, which requires looking at up to 11 bits. be done.

(Embodiment) FIG. 1 shows an embodiment of a bit number conversion circuit according to the present invention. The 16-pit digital data (1) is input to the first shift register a2. Shift register Q3 is
The data (1) is output as is to the selector 0, and its absolute value α is supplied to the second shift register (L9).The second shift register (2) outputs the upper 7 bits αQ of the absolute value α to the next stage conversion pattern detection unit (1?
) is output. The detection unit αη is as described above.

The number of shifts is determined based on the 7-bit value according to the rules shown in FIG.

The shift information α peak is generated by the shift clock generator (191) in the timing generator [19] and the conversion pattern latch unit (
7). The above timing generator ← In addition to the old jit clock generator (191), the latch timing generator (192), and the addition clock generator (193)
, a memory control timing generator (194). The shift clock generator (191) is
Based on the supplied shift information (c), a shift clock Qυ for shifting the data (1) is output to the second shift register αG and the addition clock generator (193).

Further, after sending out the shift clock 12D, the shift clock generator 9 generates a latch timing generator (192).
) sends out a pulse (195) instructing timing generation. The timing generator (192) generates a pulse (
195), outputs a latch timing pulse (2) for latching the upper 4 bits of the shifted data to the conversion pattern latch unit (a).

As a result of the above, the conversion pannoon latch unit determines the conversion pattern shown in FIG. 7 based on the shift information, and according to the latch timing pulse 4, the conversion pattern is already truncated to 12 bits by the second shift register <1!9. 2 is added to the upper 4 bits of the received digital data. The digital data 3D of the subordinate bit thus converted is guided to the selector Q3.

The selector α floor selects and outputs the 16-bit data (1) in the standard mode, and the 12-bit data Gυ in the long-time mode.

Now, the addition clock generator (193) to which the above-mentioned shift clock Q1) is supplied performs a level judgment on the shifted digital data (1) based on the shift information circle. )...The addition clock @ having a pulse corresponding to (+) is supplied to the dB conversion section (2-digit addition number generator (241)).

Further, after generating the addition clock @, the addition clock generator (193) sends a timing generation instruction signal (1) to the memory control timing generator (194).
96) is output.

The dB converter @ is the addition number generator (241)
and a basic number generator (242); and an adder (243).

The basic number generator (242) receives 4-pit data (c) from 6-B to 98B of the digital data (1) shifted by the shift clock r2 from the second shift register α9. Basic number generator (242)
It is always the above-mentioned 4-pit data (goods) of 5sB to 9sB that is supplied. The reason why the level determination position is fixed in this way is because of the following relationship: Determination position after shift = Determination position before shift 0 - Number of shifts...-(II). That is,
When A=0, B=5sB to 9sB, when person=1, B
=s7sB~1QsB.

When the number of people is 2, B=8sB to 11'Bs..., and as a result, the judgment position after shifting is always fixed at 58B to 9sB.

The basic number generator (242) generates basic numbers 1 to 30 (244) shown in FIG. 2 in accordance with the input value of the 4-pit data (goods). This basic number (244) is the fourth
This corresponds to the number of the LED to be lit shown in the right column of the figure. Next, the addition number generator (241) to which the addition clock (c) is input outputs a value three times the number of pulses given by the above equation (1) as an addition number (245). This addition number (245) is the adder (243).
), and the base number (244) is incremented by K. As a result, the number output by the adder (243) becomes the LED (to) to be lit shown in the right column of FIG. 4 above.

The LED number group is input to the meter process section. The meter process section (c) is memo IJ (261)
and comparator (262), memory controller (263)
, counter (264), LED controller? (
265). The LED No. 4 (c) is input to the memo IJ (261) and the counter (264). The peak level value (LED number) is written in the memory (261) K. Also, the counter (2
64) is the LED number (to) representing the current peak value
is counted at the sampling frequency and output. The comparator (262) calculates the peak value (2) of the mesosu (261).
66) and the counter (2) corresponding to the current peak value.
64) with the count output (267) and send the result to the memory controller (20) and the LED controller (267).
265). The above memory controller? (26
3) is also supplied with the control timing signal (C) output from the memory control timing generator (194) in the timing generation unit 1, and the contents of the memory (261) are adjusted according to the comparison result (268). The memory (261) K outputs a memory control signal (269) that controls reading and writing of the memory.

In addition, the comparison result (2
70) and a count output (267) are led, and the controller 0-2 (264) outputs a blinking control signal to control the blinking of the LED of the next stage level meter (to).

〔Effect of the invention〕

According to the bit number conversion circuit of the present invention described in detail above, it is possible to combine the level meter circuit with minimizing the increase in circuit scale, and it is suitable for C conversion. Furthermore, whereas conventionally, level detection was performed based on the data value of a predetermined number of bits whose position fluctuates, according to the present invention, level detection can be performed based on the data value of a specific bit whose position is fixed, and the detection time is is shortened, and the high-speed performance of the entire circuit is not impaired.

In addition, in the present invention, 16-bit data is converted to 12-picture data, and the number of LEDs used for level display is 4.
Although the explanation has been made in terms of segments, the present invention is not limited to these specific numerical values. When these values are changed, the number of bits of the conversion pattern and its value, the basic number value, the addition number value, and the bit position of the data to be detected during dB conversion (from 5sB in this example) are changed accordingly. 9s
B) etc. can be changed.

[Brief explanation of the drawing]

FIG. 1 is a circuit block configuration diagram showing an embodiment of the bit number conversion circuit of the present invention, FIG. 2 is a correspondence diagram between detected data and basic numbers, FIG. 3 is a configuration diagram of a level meter circuit, and FIG. The figure shows the correspondence between the number of shifts and digital data, Figure 5 is a configuration diagram of a single bit number conversion circuit, Figure 6 is a comparison diagram of 16 bits vs. small bit data showing the bit number conversion rule, and Figure 7
The figure is a diagram showing the correspondence between conversion patterns and shift numbers. (1)...n-bit digital data, Q9...shift register, αD...conversion pattern detection section, αT...timing generation section, ■...conversion pattern latch section, (2)...・dB conversion section, ■...meter process section, (c)...level meter, 01)...m-bit digital data. Agent: Patent Attorney: Nori Chika, Yudo, Uji HiroI! 2 Figure 4 Figure 5 Figure 7 Figure 16 hit 12 bit 6th (!I

Claims (1)

[Claims] In a bit number conversion circuit that converts n-bit digital data to m-bit digital data, there is a shift register that inputs the n-bit data and outputs the upper 1-bit data, and a shift register that inputs the n-bit data and outputs the upper 1-bit data. a conversion pattern detection unit that determines the number of shifts of the n-bit data; a timing generation unit that generates a shift clock to shift the n-bit data in the shift register based on shift information output from the detection unit; and the shift clock. a dB conversion unit that inputs data in a fixed specific bit range output from the shift register in the n-bit data shifted using the dB conversion unit, and detects the value of the n-bit data before shifting based on the value; ,
means for displaying the n-bit data value detected by the dB conversion section; a conversion pattern latch section for inputting the shift information and outputting a conversion pattern of bits selected in accordance therewith; and a means for displaying the n-bit data value after the shift. Lower order of data (n
- m) A bit number conversion circuit characterized by comprising: means for latching upper bits of m-bit data obtained by truncating bits according to the conversion pattern and outputting it as m-bit digital data.