JPS63108452A - Inter-processor communication control system - Google Patents

Abstract

PURPOSE:To assign the interruption processing time of a replying communication to other tasks, and to improve the performance of an arithmetic processor by eliminating the replying communication from a control processor. CONSTITUTION:In order to activate another task on an arithmetic processor 14, an activating processing is executed. At such a time, when the task to be activated is absent, the processor 14 comes to be the weight condition to await an inter-processor communication from a control processor 13. When the task to be activated is present and the processor 14 executes the inter-processor communication to the control processor 13 and the inter-processor communication of the replying communication, the receiving processing of the inter- processor communication of the control processor 13 is executed. At such a time it is decided whether or not the replying communication from the processor 14 is obtained. When replying communication is started a lock byte 21 is made into the un-locking condition. When the replying communication is not started, the communication data are read from a communication data area 22 at a main memory device 11, the processing in accordance with the communication data is executed by the control processor 13 and thereafter, the lock byte 21 is made into the un-locking condition.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an inter-processor communication control method, and relates to an arithmetic processor that performs 2% high-speed scientific operations (vector operations), and a normal operating system that controls this arithmetic processor. The present invention relates to a method for controlling inter-processor communication from the arithmetic processor to the control processor in a multiprocessor system comprising a control processor and a control processor.

[Conventional technology]

Conventionally, in communication between an arithmetic processor and a control processor in such a multiprocessor system,
When inter-processor communication is performed from the arithmetic processor to the control processor in response to a request from a certain task of the arithmetic processor, the arithmetic processor waits for a reply communication from the control processor, and when there is a reply communication, the lock byte is set to an unlocked state. It was configured to start the next task after
Publication No. 2841).

[Problem that the invention seeks to solve]

In this way, conventionally, when inter-processor communication was performed from the arithmetic processor to the control processor in response to a request from a certain task of the arithmetic processor, the arithmetic processor always waited for reply communication from the control processor. I was unable to start other tasks for the waiting time.

Furthermore, there is a problem in that the performance of the arithmetic processor is degraded due to the interruption of the resolution communication.

The present invention solves these conventional problems, and its purpose is to allocate interrupt processing time for silibili communication to other tasks by eliminating silibili communication from the control processor, thereby freeing up the processing time of the arithmetic processor. The goal is to improve performance.

[Means for solving problems]

In order to achieve the above object, the present invention communicates between an arithmetic processor having a mutual communication function and a control processor that controls the arithmetic processor via a common communication area of a main storage device that can be used exclusively by a lock byte. In a communication control method from the arithmetic processor to the control processor in a multiprocessor system that sends and receives communication data, when transmitting from the arithmetic processor to the control processor, the arithmetic processor locks the lock byte and transmits the communication data. means for writing in the common communication area and transmitting a message to that effect to the control processor using the communication function, and activating the next task without waiting for reso-rai communication from the control processor; and means for the control processor to unlock the lock byte and not to send a reply communication to the arithmetic processor.

〔Example〕

Next, two aspects of the present invention will be explained with reference to the drawings.

FIG. 1 is a block diagram showing an example of the configuration of a multiprocessor system implementing the present invention. The multiprocessor system shown in FIG. 1 includes a processor 14 having an inter-processor communication means and performing high-speed scientific operations, and a control processor 13 having an inter-processor communication means and performing the functions of a normal operating system. A communication data area 22 that temporarily stores communication data during communication between the device 12 and f-rowse. A lock byte 21 for exclusive use of this communication data area 22 by both processors 13 and 14, other control information (not shown), and programs and data for running on both processors are stored. It consists of a storage device 11, an input/output processing device 15 that controls input/output, and an input/output device 16 in which programs, data, and the like are stored.

Arithmetic processor 14 and control processor 1 that controls it
The processor open communication means provided in each of the processors 3 and 3 are connected to each other via a signal line 23.

Via this signal line 23, various control signals such as a regri signal can be sent and received.

FIG. 2 is an explanatory diagram of the structure of the lock byte 21 for exclusive use of the communication data area 22 by each processor, and this example shows an 8-bit structure of the lock byte. When in the locked state, bits 0 to 3 are set to hexadecimal [8], and bits 4 to 7 are set to the device number of the processor that put the lock byte 21 in the locked state. Also, when in the unlocked state, bits θ to 7 are hexadecimal [00
] is set.

FIG. 3 is a flowchart when the control processor 13 receives interprocessor communication from the arithmetic processor 14, FIG. 4 is a flowchart when the arithmetic processor 14 sends interprocessor communication to the control processor 13, and FIG. Flowchart when the arithmetic processor 14 receives inter-processor communication from the control processor 13, FIG. 6 is a flowchart of task activation processing for activating a new task on the arithmetic processor 14. .51~53.60~6
2 indicates each step. The operation of this embodiment will be explained below with reference to each figure.

First, when the control processor 13 and the arithmetic processor 14 are started, the lock byte 21 in the main memory 11 is [00], and the arithmetic processor 14 is in a wait state because there is no task to start. There is (6
0.61).

Next, when inter-processor communication is received from the control processor 13, the reception process shown in FIG. 5 is performed. Here, in the reception process shown in FIG.
Read communication data from the communication data area 22 located in (5
1) After the arithmetic processor 14 performs processing according to the communication data (52), the arithmetic processor 14 transmits inter-processor communication of reply communication to the control processor 13 (53).

The task activation process shown in FIG. 6 is performed.

Then, when a task to be started is generated on the arithmetic processor 14 by receiving the inter-processor communication from the control processor 13 (60), the task is started (60).
2) When the task running on the arithmetic processor 14 requests inter-process communication to the control processor 13, the transmission process shown in FIG. The lock acquisition operation is performed fi(41,
42) If the device number of the processor 14 is [F], the lock byte 21 is set to [8F]. Then, one communication data is written to the communication data area 22 (43).
, is sent to the control grosser 13 using the retirement function (44).

Next, the task activation process shown in FIG. 6 is performed to activate another task on the arithmetic processor 14. At this time, if there is no task to start, the arithmetic processor 14 enters a wait state to wait for inter-processor communication from the control processor 13 (60.61). On the other hand, if there is a task to start, the primary task is started (60.
62).

The arithmetic processor 14 is the control processor 1 in FIG.
When the inter-processor communication (44) to 3 and the inter-processor communication (53) of the regri communication in FIG. 5 are executed, the inter-processor communication reception processing of the control processor 13 shown in FIG. 3 is performed. At this time, it is determined whether or not it is a resolution communication from the arithmetic processor 14.
).

If there is no resorai communication, the lock byte 21 is set to the unlocked state [OO] (33). Also, if it is not a reply communication, the communication data is read from the communication data area 22 in the main storage device 11 (31), and after the control processor 13 performs processing according to the communication data (32), the lock byte 21 is unlocked. Go to state [00]K (33).

〔Effect of the invention〕

As explained above, the present invention reduces interrupt processing time for reply communication and wait time for retry communication by eliminating retry communication from the control processor when performing inter-processor communication from the arithmetic processor to the control processor. Because the tasks are assigned to tasks on the arithmetic processor, the arithmetic processor's arithmetic speed is many times faster than the control processor, and there are no interruptions or waits for reply communications from the control processor, which has a slow arithmetic speed, and the performance of the arithmetic processor is improved. It has the effect of improving

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an example of a multiprocessor system implementing the present invention, FIG. 2 is an explanatory diagram of the lock byte 21, and FIG. 3 is a diagram showing when the control processor 13 receives inter-processor communication from the arithmetic processor 14. The processing flow of
4, the arithmetic processor 14 is the control processor 13.
FIG. 5 is a flowchart of processing when transmitting interprocessor communication; FIG. 5 is a flowchart of processing when arithmetic processor 14 receives interprocessor communication from control processor 13;
The figure is a flowchart of task activation processing for starting a new task on the arithmetic processor 14. Explanation of symbols: 11 is the main storage device, 12 is the scientific processing unit, 13 is the control processor, 14 is the arithmetic processor, 1
5 is an input/output processing device, 16 is an input/output device, 21 is a lock byte, 22 is a communication data area, and 23 is a signal line. Figure 1 Figure 3

Claims (1)

[Claims] 1. Communication data is transmitted between an arithmetic processor having a mutual communication function and a control processor that controls the arithmetic processor via a common communication area of the main storage device that can be used exclusively by a lock byte. In a communication control method from the arithmetic processor to the control processor in a multiprocessor system that sends and receives information, when transmitting from the arithmetic processor to the control processor,
the arithmetic processor locks the lock byte and writes communication data to the common communication area, and transmits this to the control processor using the communication function;
means for activating the next task without waiting for a reply communication from the control processor; and the control processor receiving the inter-processor communication from the arithmetic processor using the communication function, sets the lock byte in an unlocked state, and the control processor 1. An inter-processor communication control method, comprising means for not transmitting a reply communication to an arithmetic processor.