JPS6272050A - Inter-processor communicating control system - Google Patents

Abstract

PURPOSE:To improve the performance of the arithmetic processor by assigning the waiting time of the replaying communication to other task. CONSTITUTION:When the task is started on an arithmetic processor 4, the task to be started does not exist, the arithmetic processor 4 weights, the communication between the processors of the replying communication from a control processor 3 is received, the receiving processing is executed, the reply waiting display of a condition control word 13 to show the condition of the processor 4 at a main storage device 1, in case of 1, a locking byte 11 is made into an unlocking condition 00, and the reply waiting display of the condition control word 13 is made into 0. When in the receiving processing, the reply waiting display of the condition control word 13 is 0, after the communicating data are read from a communicating data area 12 and the processing is executed by the processor 4, the processor 4 transmits the inter-processor communication of the reply communication to the control processor 3. The control processor 3 makes the locking byte 11 into the unlocking condition 00.

Description

[Detailed description of the invention]

[Industrial Field of Application] The present invention relates to an inter-processor communication control method, and in particular to a method for performing high-speed scientific operations (Hectoral operations)/'A arithmetic processor and its arithmetic processors to perform the functions of a normal operating system. The present invention relates to a control method for inter-processor communication between the arithmetic processors in a multiprocessor system comprising a control processor and a control processor. - In this type of multiprocessor system, communication data between the arithmetic processor and the control processor is shared by both processors in a common memory device set to 1I.
One message is sent via the li11 communication area, and communication indicating that the communication data has been set in the common communication area, reply communication, etc. is performed by communication functions such as an interrupt mechanism for communication provided in both processors. Furthermore, a management area called a lock byte is usually provided to ensure that the common 11T1 communication area is not used by multiple processors at the same time and can be used exclusively by one processor. (Prior Art) Conventionally, in communication between an arithmetic processor and a control processor in such a multiprocessor system,
When a processor requests a certain task from the processor to the control processor, the processor waits for a reply 1lTI signal from the control processor, and releases the lock byte when there is a reply communication. It was configured to launch the next task after locking.
In the past, it was not possible for other tasks to determine whether a task on an arithmetic process requested interprocessor communication, so when another task was started, that task This is to prevent multiple tasks from using the single common 1111i111 communication area redundantly if further intercommunication is requested. [Problems to be Solved by the Invention] As described above, conventionally, when communication between control processors and processors is performed from an arithmetic processor at the request of a certain task of the /ji''jX processor, the arithmetic processor
Since the reply communication from the control processor is always awaited, other tasks cannot be activated for the waiting time, resulting in a decrease in the performance of the arithmetic processor. The present invention has solved these conventional problems, and its purpose is to improve the performance of an arithmetic processor by allocating the waiting time for reply communication to other tasks. [Means for Solving the Problems] In order to achieve the above object, the present invention provides an exclusive lock byte between an arithmetic processor having a mutual communication function and a control processor that controls the arithmetic processor. In a communication control method from the arithmetic processor to the control processor in a multiprocessor system that sends and receives communication data via a common communication area of an available main storage device, When transmitting from the arithmetic processor to the control processor, it determines the reply waiting indication, and if it is waiting for a reply, it waits for a reply communication from the control 10 setter, and if it is not waiting for a reply, it means for locking the lock byte and writing communication data into the common communication area, and transmitting this to the control processor by the communication function, and setting the reply wait indication to reply wait; and the operation. means for setting the lock byte to an unlocked state and resetting the reply waiting indication when the processor receives an inter-processor communication from the control processor through the communication function and if the reply waiting indication indicates waiting for a reply; , When starting a task on the arithmetic processor, if the reply waiting display is not waiting for a reply, or even if it is waiting for a reply but no inter-processor communication has been received, the task is started and the reply waiting display is means for unlocking the lock byte and activating the task after resetting the reply waiting display when indicating waiting for a reply and receiving inter-processor communication. When communication between the control processor and the processor is not requested, the reply wait indicator is set, and if there is another task to start, the arithmetic processor starts that task.The task started first takes control. When inter-processor communication with a processor is requested, the reply waiting indicator is set, and if inter-processor communication with the control processor is requested from a later activated task before the reply communication arrives, the reply waiting indicator is set. Therefore, the arithmetic processor waits for reply communication. [Embodiment] Fig. 1 is a block diagram showing an example of a multiprocessor system implementing the present invention. The multiprocessor system shown in Fig. M1 has an inter-processor communication means. Arithmetic processor 4 that performs high-speed scientific calculations
and a scientific calculation processing system 2 including a control processor 3 that has an inter-processor communication means and performs the functions of a normal operating system, a communication data area 12 that temporarily stores communication data during inter-processor communication, and a communication data area 12 that temporarily stores communication data during inter-processor communication. A lock byte 11 for exclusive use of the data area 12 by both processors 3 and 4, a status control word 13 indicating the status of the arithmetic processor 4, other control information, programs and data for operating on both processors, etc. It is composed of a main storage device Z1 in which are stored, an input/output processing device 5 that controls input/output, and an input/output device 6 in which programs, data, etc. are stored. The inter-processor communication means provided in each of the arithmetic processor 4 and the control processor 3 that controls it is connected to the signal line 1.
4, and various control signals such as reply signals can be sent and received via the signal wire 14. FIG. 2 is an explanatory diagram of the structure of the lock hide II for exclusive use of the communication data area 12 by each processor, and this example shows a lock byte having an 8-bit structure. Bits 0 to 3 are set to hexadecimal [8] when the lock state is set, and hexadecimal [8] is set to the bits when the lock state is set.

[0] is set. Bits 4 to 7 are set with the device number of the processor that has locked the lock byte 11. Figure 3 shows state control word 1 indicating the state of operation 7° rosenosa 4.
3 is a diagram showing an example of 3, in which the arithmetic processor 4 controls 1
A reply waiting display 131 indicating whether a reply communication from one processor 3 is being waited for is provided. This reply waiting display 131 is set to (11) when the arithmetic processor 4 is waiting for a reply communication from the control processor 3. FIG. 5 is a flowchart when the arithmetic processor 4 receives inter-processor communication from the control processor 3. FIG. 40-46, 50-55.60 is a flowchart of startup processing.
-66 indicate each step. The operation of this embodiment will be explained below with reference to each figure. First, when the control processor 3 and the arithmetic processor 4 are started up, the reply waiting display 131 of the status control word 13 in the main storage device I is

[0], lock-by [1 is [
00]. When a task to be started on the arithmetic processor 4 occurs (
60), since the reply waiting display +31 is not (1) and no inter-processor communication has been received, (62, 6
3) The task is launched (66). When the task running on the arithmetic processor 4 requests 1ffl communication between the control processors 3 and 4, the fourth
The transmission process shown in the figure has been performed, and the reply waiting display 13
Since 1 is (1), the lock acquisition operation for lock high [1 in the main storage device 1 is performed (42, 43),
If the device number of the arithmetic processor 4 is [F], the lock byte 11 is set to [8F]. Communication data is then written to the communication data area 12 (44) and transmitted to the control processor 3 using the communication function (45).
), and a state control word 1 indicating the state of the arithmetic process 4.
3's reply waiting display 131 is set to (1) (46)
. Next, the task activation process shown in FIG. 6 is performed to activate another task on the arithmetic processor 4. At this time, if there is no task to start, the arithmetic processor 4 enters a wait state to wait for inter-processor communication from the control processor 3 (60.61).On the other hand, if there is a task to start, the main memory The reply waiting display +31 of the status control word 13 indicating the state of the arithmetic processor 4 in step 1 is determined (62), and if the task is not waiting for a reply, the task is activated (66). , if no inter-processor communication has been received, the task is activated (63). However, if interprocessor communication has already been received, lock byte 11 in main memory L is set to Afrolock state.

[00] Nishiku64)
, a state system that indicates the state of the arithmetic processor 4? The task is started after the reply waiting display 131 for i1 word 13 is set to [O]. Next, when a task is activated on the arithmetic processor 4 or there is no task to be activated (when the arithmetic processor 4 is waiting), if an inter-processor communication of a reply communication is received from the control processor 3, the The reception process shown in FIG. If it is 11, set the lock byte 11 in the main storage device l to the unlocked state (00)51),
The reply waiting display 131 of the status control word 13 indicating the status of the arithmetic process 4 is displayed.

In addition, in the receiving process shown in FIG. 5, the reply waiting display 131 of the status control word 13 indicating the status of the arithmetic processor 4 in the main storage W11 is

If [0], read communication data from communication data area 12 in main memory 1 (53)
, after the arithmetic processor 4 performs processing according to the ill communication data (54), the arithmetic processor 4 transmits the inter-processor communication of the reply communication to the control processor 3 (54).
5). Here, the control processor 3 that has received the inter-processor communication of the reply communication sets the lock-by number 1 in the main storage device 1 to the Afro lock state [00]. In the above embodiment, the reply waiting display 131 is provided in the state control word 13 in the main storage device t, but it goes without saying that it may also be provided in the arithmetic processor 4 for control. be. [Effects of the Invention] As explained above, in the present invention, when inter-processor communication is performed from the arithmetic processor to the control processor, the waiting time for reply communication from the control processor is allocated to the task on the arithmetic processor. The calculation speed of the calculation processor is many times faster than that of the control processor.
Moreover, even if it takes time to wait for a reply communication from a control processor with a slow calculation speed, the performance of the calculation processor is not degraded, and the performance of the calculation processor can be improved.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an example of a multiprocessor system implementing the present invention, FIG. 2 is an explanatory diagram of a lock byte, FIG. 3 is an explanatory diagram of a state control word including a reply wait indication, and FIG. 4 is an operation diagram. FIG. 5 is a flow chart of processing when processor 4 sends inter-processor communication to control processor 3; FIG. 5 is a flow chart of processing when arithmetic processor 4 receives inter-processor communication from control processor 3; and FIG. 3 is a flowchart of task activation processing for starting a new task on the arithmetic processor 4; In the figure, l is the main memory, 2 is the scientific processing unit,
3 is a control processor, 4 is an arithmetic processor, 11 is Rockhide, 12 is a communication data area, 13 is a state control word,
131 is a reply waiting display. Patent Applicant NEC Corporation - Patent Attorney Susumu Uchihara, 2. Block circle of the practical example of the present invention No. 1 Transmission of Logo Calculation Processor 4 No. 4 Figure Calculation Processor 4 Flow of reception processing 1 Fig. 5 Fig. 6

Claims (1)

[Claims] Exchange of communication data between an arithmetic processor having a mutual communication function and a control processor that controls the arithmetic processor via a common communication area of a main storage device that can be used exclusively by a lock byte. A communication control method from the arithmetic processor to the control processor in a multiprocessor system that performs the following: a reply waiting indication provided in a status control word indicating the state of the arithmetic processor; and transmission from the arithmetic processor to the control processor. At times, it determines the reply waiting indication, and if it is waiting for a reply, it waits for a reply communication from the control processor, and if it is not waiting for a reply, it locks the lock byte and writes communication data to the common communication area. means for transmitting a message to that effect to the control processor through the communication function, and setting the reply wait indication to reply wait; when the arithmetic processor receives inter-processor communication from the control processor through the communication function; means for unlocking the lock byte and resetting the reply waiting indication if the reply waiting indication indicates waiting for a reply; If not waiting or waiting for a reply but not receiving inter-processor communication, the task is started, and if the reply waiting display indicates waiting for a reply and inter-processor communication is being received, the lock byte is activated. An inter-processor communication control method, comprising means for activating a task after unlocking and resetting the reply waiting display.